diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-08-17 11:10:12 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-08-17 11:10:12 -0400 |
| commit | 9d0f8140fc8a723af4eb1ec4d757847515649574 (patch) | |
| tree | 37d8ca17ea77fd6847f3ea06391665fa80f70ea0 /arch/c6x | |
| parent | ef824bfba2cce6a75c7cd740f6ad80581e75a109 (diff) | |
| parent | 01ddd9a809b9a95df097ff1b5565f806e681a606 (diff) | |
Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
Pull C6X atomic64 support from Mark Salter:
"Enable atomic64 ops in C6X
- define L1_CACHE_SHIFT
- select GENERIC_ATOMIC64"
* tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming:
C6X: select GENERIC_ATOMIC64
C6X: add Lx_CACHE_SHIFT defines
Diffstat (limited to 'arch/c6x')
| -rw-r--r-- | arch/c6x/Kconfig | 1 | ||||
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
2 files changed, 12 insertions, 5 deletions
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig index 052f81a76239..983c859e40b7 100644 --- a/arch/c6x/Kconfig +++ b/arch/c6x/Kconfig | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | config C6X | 6 | config C6X |
| 7 | def_bool y | 7 | def_bool y |
| 8 | select CLKDEV_LOOKUP | 8 | select CLKDEV_LOOKUP |
| 9 | select GENERIC_ATOMIC64 | ||
| 9 | select GENERIC_IRQ_SHOW | 10 | select GENERIC_IRQ_SHOW |
| 10 | select HAVE_ARCH_TRACEHOOK | 11 | select HAVE_ARCH_TRACEHOOK |
| 11 | select HAVE_DMA_API_DEBUG | 12 | select HAVE_DMA_API_DEBUG |
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Port on Texas Instruments TMS320C6x architecture | 2 | * Port on Texas Instruments TMS320C6x architecture |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated | 4 | * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated |
| 5 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) | 5 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| @@ -16,9 +16,14 @@ | |||
| 16 | /* | 16 | /* |
| 17 | * Cache line size | 17 | * Cache line size |
| 18 | */ | 18 | */ |
| 19 | #define L1D_CACHE_BYTES 64 | 19 | #define L1D_CACHE_SHIFT 6 |
| 20 | #define L1P_CACHE_BYTES 32 | 20 | #define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) |
| 21 | #define L2_CACHE_BYTES 128 | 21 | |
| 22 | #define L1P_CACHE_SHIFT 5 | ||
| 23 | #define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) | ||
| 24 | |||
| 25 | #define L2_CACHE_SHIFT 7 | ||
| 26 | #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) | ||
| 22 | 27 | ||
| 23 | /* | 28 | /* |
| 24 | * L2 used as cache | 29 | * L2 used as cache |
| @@ -29,7 +34,8 @@ | |||
| 29 | * For practical reasons the L1_CACHE_BYTES defines should not be smaller than | 34 | * For practical reasons the L1_CACHE_BYTES defines should not be smaller than |
| 30 | * the L2 line size | 35 | * the L2 line size |
| 31 | */ | 36 | */ |
| 32 | #define L1_CACHE_BYTES L2_CACHE_BYTES | 37 | #define L1_CACHE_SHIFT L2_CACHE_SHIFT |
| 38 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | ||
| 33 | 39 | ||
| 34 | #define L2_CACHE_ALIGN_LOW(x) \ | 40 | #define L2_CACHE_ALIGN_LOW(x) \ |
| 35 | (((x) & ~(L2_CACHE_BYTES - 1))) | 41 | (((x) & ~(L2_CACHE_BYTES - 1))) |