diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-09-06 19:48:59 -0400 |
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committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-09-06 19:48:59 -0400 |
commit | fff34b3412b9401a76ba9d021db1bd91cb0e02b6 (patch) | |
tree | 870ed2d1555004e7939d15b5099017aae61c97b8 /arch/c6x/include/asm/cache.h | |
parent | 28e1e58fb668e262648fb8ee8a24154633f40507 (diff) | |
parent | 636802ef96eebe279b22ad9f9dacfe29291e45c7 (diff) |
Merge branch 'merge' into next
Brings in various bug fixes from 3.6-rcX
Diffstat (limited to 'arch/c6x/include/asm/cache.h')
-rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Port on Texas Instruments TMS320C6x architecture | 2 | * Port on Texas Instruments TMS320C6x architecture |
3 | * | 3 | * |
4 | * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated | 4 | * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated |
5 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) | 5 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
@@ -16,9 +16,14 @@ | |||
16 | /* | 16 | /* |
17 | * Cache line size | 17 | * Cache line size |
18 | */ | 18 | */ |
19 | #define L1D_CACHE_BYTES 64 | 19 | #define L1D_CACHE_SHIFT 6 |
20 | #define L1P_CACHE_BYTES 32 | 20 | #define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) |
21 | #define L2_CACHE_BYTES 128 | 21 | |
22 | #define L1P_CACHE_SHIFT 5 | ||
23 | #define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) | ||
24 | |||
25 | #define L2_CACHE_SHIFT 7 | ||
26 | #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) | ||
22 | 27 | ||
23 | /* | 28 | /* |
24 | * L2 used as cache | 29 | * L2 used as cache |
@@ -29,7 +34,8 @@ | |||
29 | * For practical reasons the L1_CACHE_BYTES defines should not be smaller than | 34 | * For practical reasons the L1_CACHE_BYTES defines should not be smaller than |
30 | * the L2 line size | 35 | * the L2 line size |
31 | */ | 36 | */ |
32 | #define L1_CACHE_BYTES L2_CACHE_BYTES | 37 | #define L1_CACHE_SHIFT L2_CACHE_SHIFT |
38 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | ||
33 | 39 | ||
34 | #define L2_CACHE_ALIGN_LOW(x) \ | 40 | #define L2_CACHE_ALIGN_LOW(x) \ |
35 | (((x) & ~(L2_CACHE_BYTES - 1))) | 41 | (((x) & ~(L2_CACHE_BYTES - 1))) |