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authorMike Frysinger <vapier@gentoo.org>2009-06-29 14:20:10 -0400
committerMike Frysinger <vapier@gentoo.org>2009-07-16 01:52:24 -0400
commitfb4b5d3a379824d94fd71fc1aa78e9dbcb15b948 (patch)
tree104b640b09ebbc58f4eb3b67fd190bf7bf9a3912 /arch/blackfin
parent8399a74f61c69c7d233924de3dd314ca0effa16a (diff)
Blackfin: handle BF561 Core B memory regions better when SMP=n
Rather than assume Core B is always run with caches turned on, let people load into any of the on-chip memory regions. It is their business how the SRAM/Cache regions are utilized, so don't prevent them from being able to load into them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/process.c14
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h23
2 files changed, 29 insertions, 8 deletions
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 79cad0ac5892..9da36bab7ccb 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -361,7 +361,7 @@ static inline
361int in_mem_const(unsigned long addr, unsigned long size, 361int in_mem_const(unsigned long addr, unsigned long size,
362 unsigned long const_addr, unsigned long const_size) 362 unsigned long const_addr, unsigned long const_size)
363{ 363{
364 return in_mem_const_off(addr, 0, size, const_addr, const_size); 364 return in_mem_const_off(addr, size, 0, const_addr, const_size);
365} 365}
366#define IN_ASYNC(bnum, bctlnum) \ 366#define IN_ASYNC(bnum, bctlnum) \
367({ \ 367({ \
@@ -390,13 +390,13 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) 390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
392#ifdef COREB_L1_CODE_START 392#ifdef COREB_L1_CODE_START
393 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 393 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; 394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; 396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
397 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 397 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
399 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 399 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
401#endif 401#endif
402 if (in_mem_const(addr, size, L2_START, L2_LENGTH)) 402 if (in_mem_const(addr, size, L2_START, L2_LENGTH))
@@ -472,13 +472,13 @@ int _access_ok(unsigned long addr, unsigned long size)
472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) 472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
473 return 1; 473 return 1;
474#ifdef COREB_L1_CODE_START 474#ifdef COREB_L1_CODE_START
475 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 475 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
476 return 1; 476 return 1;
477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
478 return 1; 478 return 1;
479 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 479 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
480 return 1; 480 return 1;
481 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 481 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
482 return 1; 482 return 1;
483#endif 483#endif
484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) 484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index a63e15c86d90..5b96ea549a04 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -37,7 +37,6 @@
37 37
38/* Memory Map for ADSP-BF561 processors */ 38/* Memory Map for ADSP-BF561 processors */
39 39
40#ifdef CONFIG_BF561
41#define COREA_L1_CODE_START 0xFFA00000 40#define COREA_L1_CODE_START 0xFFA00000
42#define COREA_L1_DATA_A_START 0xFF800000 41#define COREA_L1_DATA_A_START 0xFF800000
43#define COREA_L1_DATA_B_START 0xFF900000 42#define COREA_L1_DATA_B_START 0xFF900000
@@ -74,6 +73,28 @@
74#define BFIN_DCACHESIZE (0*1024) 73#define BFIN_DCACHESIZE (0*1024)
75#define BFIN_DSUPBANKS 0 74#define BFIN_DSUPBANKS 0
76#endif /*CONFIG_BFIN_DCACHE*/ 75#endif /*CONFIG_BFIN_DCACHE*/
76
77/*
78 * If we are in SMP mode, then the cache settings of Core B will match
79 * the settings of Core A. If we aren't, then we assume Core B is not
80 * using any cache. This allows the rest of the kernel to work with
81 * the core in either mode as we are only loading user code into it and
82 * it is the user's problem to make sure they aren't doing something
83 * stupid there.
84 *
85 * Note that we treat the L1 code region as a contiguous blob to make
86 * the rest of the kernel simpler. Easier to check one region than a
87 * bunch of small ones. Again, possible misbehavior here is the fault
88 * of the user -- don't try to use memory that doesn't exist.
89 */
90#ifdef CONFIG_SMP
91# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
92# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
93# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
94#else
95# define COREB_L1_CODE_LENGTH 0x14000
96# define COREB_L1_DATA_A_LENGTH 0x8000
97# define COREB_L1_DATA_B_LENGTH 0x8000
77#endif 98#endif
78 99
79/* Level 2 Memory */ 100/* Level 2 Memory */