aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 17:37:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 17:37:27 -0400
commite36f561a2c88394ef2708f1ab300fe8a79e9f651 (patch)
tree385f378c4240955e4356d49686a8ef606a82a7c1 /arch/blackfin
parent70ada77920723fbc2b35e9b301022fb1e166b41b (diff)
parentdf9ee29270c11dba7d0fe0b83ce47a4d8e8d2101 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags: Fix IRQ flag handling naming MIPS: Add missing #inclusions of <linux/irq.h> smc91x: Add missing #inclusion of <linux/irq.h> Drop a couple of unnecessary asm/system.h inclusions SH: Add missing consts to sys_execve() declaration Blackfin: Rename IRQ flags handling functions Blackfin: Add missing dep to asm/irqflags.h Blackfin: Rename DES PC2() symbol to avoid collision Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header Blackfin: Split PLL code from mach-specific cdef headers
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/include/asm/ipipe.h8
-rw-r--r--arch/blackfin/include/asm/irqflags.h273
-rw-r--r--arch/blackfin/include/asm/mmu_context.h8
-rw-r--r--arch/blackfin/include/asm/system.h4
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c102
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c8
-rw-r--r--arch/blackfin/kernel/ipipe.c38
-rw-r--r--arch/blackfin/kernel/process.c4
-rw-r--r--arch/blackfin/kernel/trace.c1
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h50
-rw-r--r--arch/blackfin/mach-bf518/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h50
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c1
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c1
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c1
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h91
-rw-r--r--arch/blackfin/mach-bf533/include/mach/fio_flag.h55
-rw-r--r--arch/blackfin/mach-bf533/include/mach/pll.h57
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h44
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h57
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h50
-rw-r--r--arch/blackfin/mach-bf538/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h56
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h69
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h50
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-common/cpufreq.c4
-rw-r--r--arch/blackfin/mach-common/ints-priority.c24
-rw-r--r--arch/blackfin/mach-common/pm.c10
30 files changed, 738 insertions, 630 deletions
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index d3b40449ca0e..40f94a704c02 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -49,7 +49,7 @@
49#define prepare_arch_switch(next) \ 49#define prepare_arch_switch(next) \
50do { \ 50do { \
51 ipipe_schedule_notify(current, next); \ 51 ipipe_schedule_notify(current, next); \
52 local_irq_disable_hw(); \ 52 hard_local_irq_disable(); \
53} while (0) 53} while (0)
54 54
55#define task_hijacked(p) \ 55#define task_hijacked(p) \
@@ -57,7 +57,7 @@ do { \
57 int __x__ = __ipipe_root_domain_p; \ 57 int __x__ = __ipipe_root_domain_p; \
58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \ 58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
59 if (__x__) \ 59 if (__x__) \
60 local_irq_enable_hw(); \ 60 hard_local_irq_enable(); \
61 !__x__; \ 61 !__x__; \
62 }) 62 })
63 63
@@ -167,7 +167,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
167#define __ipipe_run_isr(ipd, irq) \ 167#define __ipipe_run_isr(ipd, irq) \
168 do { \ 168 do { \
169 if (!__ipipe_pipeline_head_p(ipd)) \ 169 if (!__ipipe_pipeline_head_p(ipd)) \
170 local_irq_enable_hw(); \ 170 hard_local_irq_enable(); \
171 if (ipd == ipipe_root_domain) { \ 171 if (ipd == ipipe_root_domain) { \
172 if (unlikely(ipipe_virtual_irq_p(irq))) { \ 172 if (unlikely(ipipe_virtual_irq_p(irq))) { \
173 irq_enter(); \ 173 irq_enter(); \
@@ -183,7 +183,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
183 __ipipe_run_irqtail(); \ 183 __ipipe_run_irqtail(); \
184 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 184 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
185 } \ 185 } \
186 local_irq_disable_hw(); \ 186 hard_local_irq_disable(); \
187 } while (0) 187 } while (0)
188 188
189#define __ipipe_syscall_watched_p(p, sc) \ 189#define __ipipe_syscall_watched_p(p, sc) \
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 813a1af3e865..41c4d70544ef 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_BFIN_IRQFLAGS_H__ 8#ifndef __ASM_BFIN_IRQFLAGS_H__
9#define __ASM_BFIN_IRQFLAGS_H__ 9#define __ASM_BFIN_IRQFLAGS_H__
10 10
11#include <mach/blackfin.h>
12
11#ifdef CONFIG_SMP 13#ifdef CONFIG_SMP
12# include <asm/pda.h> 14# include <asm/pda.h>
13# include <asm/processor.h> 15# include <asm/processor.h>
@@ -31,54 +33,108 @@ static inline unsigned long bfin_cli(void)
31 return flags; 33 return flags;
32} 34}
33 35
34#ifdef CONFIG_IPIPE
35
36#include <linux/compiler.h>
37#include <linux/ipipe_base.h>
38#include <linux/ipipe_trace.h>
39
40#ifdef CONFIG_DEBUG_HWERR 36#ifdef CONFIG_DEBUG_HWERR
41# define bfin_no_irqs 0x3f 37# define bfin_no_irqs 0x3f
42#else 38#else
43# define bfin_no_irqs 0x1f 39# define bfin_no_irqs 0x1f
44#endif 40#endif
45 41
46#define raw_local_irq_disable() \ 42/*****************************************************************************/
47 do { \ 43/*
48 ipipe_check_context(ipipe_root_domain); \ 44 * Hard, untraced CPU interrupt flag manipulation and access.
49 __ipipe_stall_root(); \ 45 */
50 barrier(); \ 46static inline void __hard_local_irq_disable(void)
51 } while (0) 47{
48 bfin_cli();
49}
50
51static inline void __hard_local_irq_enable(void)
52{
53 bfin_sti(bfin_irq_flags);
54}
55
56static inline unsigned long hard_local_save_flags(void)
57{
58 return bfin_read_IMASK();
59}
52 60
53#define raw_local_irq_enable() \ 61static inline unsigned long __hard_local_irq_save(void)
54 do { \ 62{
55 barrier(); \ 63 unsigned long flags;
56 ipipe_check_context(ipipe_root_domain); \ 64 flags = bfin_cli();
57 __ipipe_unstall_root(); \ 65#ifdef CONFIG_DEBUG_HWERR
58 } while (0) 66 bfin_sti(0x3f);
67#endif
68 return flags;
69}
70
71static inline int hard_irqs_disabled_flags(unsigned long flags)
72{
73 return (flags & ~0x3f) == 0;
74}
75
76static inline int hard_irqs_disabled(void)
77{
78 unsigned long flags = hard_local_save_flags();
79 return hard_irqs_disabled_flags(flags);
80}
81
82static inline void __hard_local_irq_restore(unsigned long flags)
83{
84 if (!hard_irqs_disabled_flags(flags))
85 __hard_local_irq_enable();
86}
87
88/*****************************************************************************/
89/*
90 * Interrupt pipe handling.
91 */
92#ifdef CONFIG_IPIPE
93
94#include <linux/compiler.h>
95#include <linux/ipipe_base.h>
96#include <linux/ipipe_trace.h>
97
98/*
99 * Interrupt pipe interface to linux/irqflags.h.
100 */
101static inline void arch_local_irq_disable(void)
102{
103 ipipe_check_context(ipipe_root_domain);
104 __ipipe_stall_root();
105 barrier();
106}
59 107
60#define raw_local_save_flags_ptr(x) \ 108static inline void arch_local_irq_enable(void)
61 do { \ 109{
62 *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ 110 barrier();
63 } while (0) 111 ipipe_check_context(ipipe_root_domain);
112 __ipipe_unstall_root();
113}
64 114
65#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) 115static inline unsigned long arch_local_save_flags(void)
116{
117 return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
118}
66 119
67#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) 120static inline int arch_irqs_disabled_flags(unsigned long flags)
121{
122 return flags == bfin_no_irqs;
123}
68 124
69#define raw_local_irq_save_ptr(x) \ 125static inline void arch_local_irq_save_ptr(unsigned long *_flags)
70 do { \ 126{
71 *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ 127 x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
72 barrier(); \ 128 barrier();
73 } while (0) 129}
74 130
75#define raw_local_irq_save(x) \ 131static inline unsigned long arch_local_irq_save(void)
76 do { \ 132{
77 ipipe_check_context(ipipe_root_domain); \ 133 ipipe_check_context(ipipe_root_domain);
78 raw_local_irq_save_ptr(&(x)); \ 134 return __hard_local_irq_save();
79 } while (0) 135}
80 136
81static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) 137static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
82{ 138{
83 /* 139 /*
84 * Merge virtual and real interrupt mask bits into a single 140 * Merge virtual and real interrupt mask bits into a single
@@ -87,130 +143,79 @@ static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
87 return (real & ~(1 << 31)) | ((virt != 0) << 31); 143 return (real & ~(1 << 31)) | ((virt != 0) << 31);
88} 144}
89 145
90static inline int raw_demangle_irq_bits(unsigned long *x) 146static inline int arch_demangle_irq_bits(unsigned long *x)
91{ 147{
92 int virt = (*x & (1 << 31)) != 0; 148 int virt = (*x & (1 << 31)) != 0;
93 *x &= ~(1L << 31); 149 *x &= ~(1L << 31);
94 return virt; 150 return virt;
95} 151}
96 152
97static inline void local_irq_disable_hw_notrace(void) 153/*
154 * Interface to various arch routines that may be traced.
155 */
156#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
157static inline void hard_local_irq_disable(void)
98{ 158{
99 bfin_cli(); 159 if (!hard_irqs_disabled()) {
160 __hard_local_irq_disable();
161 ipipe_trace_begin(0x80000000);
162 }
100} 163}
101 164
102static inline void local_irq_enable_hw_notrace(void) 165static inline void hard_local_irq_enable(void)
103{ 166{
104 bfin_sti(bfin_irq_flags); 167 if (hard_irqs_disabled()) {
168 ipipe_trace_end(0x80000000);
169 __hard_local_irq_enable();
170 }
105} 171}
106 172
107#define local_save_flags_hw(flags) \ 173static inline unsigned long hard_local_irq_save(void)
108 do { \
109 (flags) = bfin_read_IMASK(); \
110 } while (0)
111
112#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
113
114#define irqs_disabled_hw() \
115 ({ \
116 unsigned long flags; \
117 local_save_flags_hw(flags); \
118 irqs_disabled_flags_hw(flags); \
119 })
120
121static inline void local_irq_save_ptr_hw(unsigned long *flags)
122{ 174{
123 *flags = bfin_cli(); 175 unsigned long flags = hard_local_save_flags();
124#ifdef CONFIG_DEBUG_HWERR 176 if (!hard_irqs_disabled_flags(flags)) {
125 bfin_sti(0x3f); 177 __hard_local_irq_disable();
126#endif 178 ipipe_trace_begin(0x80000001);
179 }
180 return flags;
127} 181}
128 182
129#define local_irq_save_hw_notrace(flags) \ 183static inline void hard_local_irq_restore(unsigned long flags)
130 do { \
131 local_irq_save_ptr_hw(&(flags)); \
132 } while (0)
133
134static inline void local_irq_restore_hw_notrace(unsigned long flags)
135{ 184{
136 if (!irqs_disabled_flags_hw(flags)) 185 if (!hard_irqs_disabled_flags(flags)) {
137 local_irq_enable_hw_notrace(); 186 ipipe_trace_end(0x80000001);
187 __hard_local_irq_enable();
188 }
138} 189}
139 190
140#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
141# define local_irq_disable_hw() \
142 do { \
143 if (!irqs_disabled_hw()) { \
144 local_irq_disable_hw_notrace(); \
145 ipipe_trace_begin(0x80000000); \
146 } \
147 } while (0)
148# define local_irq_enable_hw() \
149 do { \
150 if (irqs_disabled_hw()) { \
151 ipipe_trace_end(0x80000000); \
152 local_irq_enable_hw_notrace(); \
153 } \
154 } while (0)
155# define local_irq_save_hw(flags) \
156 do { \
157 local_save_flags_hw(flags); \
158 if (!irqs_disabled_flags_hw(flags)) { \
159 local_irq_disable_hw_notrace(); \
160 ipipe_trace_begin(0x80000001); \
161 } \
162 } while (0)
163# define local_irq_restore_hw(flags) \
164 do { \
165 if (!irqs_disabled_flags_hw(flags)) { \
166 ipipe_trace_end(0x80000001); \
167 local_irq_enable_hw_notrace(); \
168 } \
169 } while (0)
170#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ 191#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
171# define local_irq_disable_hw() local_irq_disable_hw_notrace() 192# define hard_local_irq_disable() __hard_local_irq_disable()
172# define local_irq_enable_hw() local_irq_enable_hw_notrace() 193# define hard_local_irq_enable() __hard_local_irq_enable()
173# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags) 194# define hard_local_irq_save() __hard_local_irq_save()
174# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags) 195# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
175#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ 196#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
176 197
177#else /* CONFIG_IPIPE */ 198#else /* CONFIG_IPIPE */
178 199
179static inline void raw_local_irq_disable(void) 200/*
180{ 201 * Direct interface to linux/irqflags.h.
181 bfin_cli(); 202 */
182} 203#define arch_local_save_flags() hard_local_save_flags()
183static inline void raw_local_irq_enable(void) 204#define arch_local_irq_save(flags) __hard_local_irq_save()
184{ 205#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
185 bfin_sti(bfin_irq_flags); 206#define arch_local_irq_enable() __hard_local_irq_enable()
186} 207#define arch_local_irq_disable() __hard_local_irq_disable()
187 208#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
188#define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0) 209#define arch_irqs_disabled() hard_irqs_disabled()
189
190#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
191 210
192static inline unsigned long __raw_local_irq_save(void) 211/*
193{ 212 * Interface to various arch routines that may be traced.
194 unsigned long flags = bfin_cli(); 213 */
195#ifdef CONFIG_DEBUG_HWERR 214#define hard_local_irq_save() __hard_local_irq_save()
196 bfin_sti(0x3f); 215#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
197#endif 216#define hard_local_irq_enable() __hard_local_irq_enable()
198 return flags; 217#define hard_local_irq_disable() __hard_local_irq_disable()
199}
200#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
201 218
202#define local_irq_save_hw(flags) raw_local_irq_save(flags)
203#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
204#define local_irq_enable_hw() raw_local_irq_enable()
205#define local_irq_disable_hw() raw_local_irq_disable()
206#define irqs_disabled_hw() irqs_disabled()
207 219
208#endif /* !CONFIG_IPIPE */ 220#endif /* !CONFIG_IPIPE */
209
210static inline void raw_local_irq_restore(unsigned long flags)
211{
212 if (!raw_irqs_disabled_flags(flags))
213 raw_local_irq_enable();
214}
215
216#endif 221#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index e1a9b4624f91..3828c70e7a2e 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -97,8 +97,8 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next
97} 97}
98 98
99#ifdef CONFIG_IPIPE 99#ifdef CONFIG_IPIPE
100#define lock_mm_switch(flags) local_irq_save_hw_cond(flags) 100#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
101#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags) 101#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
102#else 102#else
103#define lock_mm_switch(flags) do { (void)(flags); } while (0) 103#define lock_mm_switch(flags) do { (void)(flags); } while (0)
104#define unlock_mm_switch(flags) do { (void)(flags); } while (0) 104#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
@@ -205,9 +205,9 @@ static inline void destroy_context(struct mm_struct *mm)
205} 205}
206 206
207#define ipipe_mm_switch_protect(flags) \ 207#define ipipe_mm_switch_protect(flags) \
208 local_irq_save_hw_cond(flags) 208 flags = hard_local_irq_save_cond()
209 209
210#define ipipe_mm_switch_unprotect(flags) \ 210#define ipipe_mm_switch_unprotect(flags) \
211 local_irq_restore_hw_cond(flags) 211 hard_local_irq_restore_cond(flags)
212 212
213#endif 213#endif
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index dde19b1d25f5..19e2c7c3e63a 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -117,7 +117,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
117 unsigned long tmp = 0; 117 unsigned long tmp = 0;
118 unsigned long flags; 118 unsigned long flags;
119 119
120 local_irq_save_hw(flags); 120 flags = hard_local_irq_save();
121 121
122 switch (size) { 122 switch (size) {
123 case 1: 123 case 1:
@@ -139,7 +139,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
139 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); 139 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
140 break; 140 break;
141 } 141 }
142 local_irq_restore_hw(flags); 142 hard_local_irq_restore(flags);
143 return tmp; 143 return tmp;
144} 144}
145 145
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index dc07ed08b37f..ca1c1f9debd6 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -349,13 +349,13 @@ inline void portmux_setup(unsigned short per)
349void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ 349void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
350{ \ 350{ \
351 unsigned long flags; \ 351 unsigned long flags; \
352 local_irq_save_hw(flags); \ 352 flags = hard_local_irq_save(); \
353 if (arg) \ 353 if (arg) \
354 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ 354 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
355 else \ 355 else \
356 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ 356 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
357 AWA_DUMMY_READ(name); \ 357 AWA_DUMMY_READ(name); \
358 local_irq_restore_hw(flags); \ 358 hard_local_irq_restore(flags); \
359} \ 359} \
360EXPORT_SYMBOL(set_gpio_ ## name); 360EXPORT_SYMBOL(set_gpio_ ## name);
361 361
@@ -371,14 +371,14 @@ void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
371{ \ 371{ \
372 unsigned long flags; \ 372 unsigned long flags; \
373 if (ANOMALY_05000311 || ANOMALY_05000323) \ 373 if (ANOMALY_05000311 || ANOMALY_05000323) \
374 local_irq_save_hw(flags); \ 374 flags = hard_local_irq_save(); \
375 if (arg) \ 375 if (arg) \
376 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ 376 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
377 else \ 377 else \
378 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ 378 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
379 if (ANOMALY_05000311 || ANOMALY_05000323) { \ 379 if (ANOMALY_05000311 || ANOMALY_05000323) { \
380 AWA_DUMMY_READ(name); \ 380 AWA_DUMMY_READ(name); \
381 local_irq_restore_hw(flags); \ 381 hard_local_irq_restore(flags); \
382 } \ 382 } \
383} \ 383} \
384EXPORT_SYMBOL(set_gpio_ ## name); 384EXPORT_SYMBOL(set_gpio_ ## name);
@@ -391,11 +391,11 @@ void set_gpio_toggle(unsigned gpio)
391{ 391{
392 unsigned long flags; 392 unsigned long flags;
393 if (ANOMALY_05000311 || ANOMALY_05000323) 393 if (ANOMALY_05000311 || ANOMALY_05000323)
394 local_irq_save_hw(flags); 394 flags = hard_local_irq_save();
395 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); 395 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
396 if (ANOMALY_05000311 || ANOMALY_05000323) { 396 if (ANOMALY_05000311 || ANOMALY_05000323) {
397 AWA_DUMMY_READ(toggle); 397 AWA_DUMMY_READ(toggle);
398 local_irq_restore_hw(flags); 398 hard_local_irq_restore(flags);
399 } 399 }
400} 400}
401EXPORT_SYMBOL(set_gpio_toggle); 401EXPORT_SYMBOL(set_gpio_toggle);
@@ -408,11 +408,11 @@ void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
408{ \ 408{ \
409 unsigned long flags; \ 409 unsigned long flags; \
410 if (ANOMALY_05000311 || ANOMALY_05000323) \ 410 if (ANOMALY_05000311 || ANOMALY_05000323) \
411 local_irq_save_hw(flags); \ 411 flags = hard_local_irq_save(); \
412 gpio_array[gpio_bank(gpio)]->name = arg; \ 412 gpio_array[gpio_bank(gpio)]->name = arg; \
413 if (ANOMALY_05000311 || ANOMALY_05000323) { \ 413 if (ANOMALY_05000311 || ANOMALY_05000323) { \
414 AWA_DUMMY_READ(name); \ 414 AWA_DUMMY_READ(name); \
415 local_irq_restore_hw(flags); \ 415 hard_local_irq_restore(flags); \
416 } \ 416 } \
417} \ 417} \
418EXPORT_SYMBOL(set_gpiop_ ## name); 418EXPORT_SYMBOL(set_gpiop_ ## name);
@@ -433,11 +433,11 @@ unsigned short get_gpio_ ## name(unsigned gpio) \
433 unsigned long flags; \ 433 unsigned long flags; \
434 unsigned short ret; \ 434 unsigned short ret; \
435 if (ANOMALY_05000311 || ANOMALY_05000323) \ 435 if (ANOMALY_05000311 || ANOMALY_05000323) \
436 local_irq_save_hw(flags); \ 436 flags = hard_local_irq_save(); \
437 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ 437 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
438 if (ANOMALY_05000311 || ANOMALY_05000323) { \ 438 if (ANOMALY_05000311 || ANOMALY_05000323) { \
439 AWA_DUMMY_READ(name); \ 439 AWA_DUMMY_READ(name); \
440 local_irq_restore_hw(flags); \ 440 hard_local_irq_restore(flags); \
441 } \ 441 } \
442 return ret; \ 442 return ret; \
443} \ 443} \
@@ -460,11 +460,11 @@ unsigned short get_gpiop_ ## name(unsigned gpio) \
460 unsigned long flags; \ 460 unsigned long flags; \
461 unsigned short ret; \ 461 unsigned short ret; \
462 if (ANOMALY_05000311 || ANOMALY_05000323) \ 462 if (ANOMALY_05000311 || ANOMALY_05000323) \
463 local_irq_save_hw(flags); \ 463 flags = hard_local_irq_save(); \
464 ret = (gpio_array[gpio_bank(gpio)]->name); \ 464 ret = (gpio_array[gpio_bank(gpio)]->name); \
465 if (ANOMALY_05000311 || ANOMALY_05000323) { \ 465 if (ANOMALY_05000311 || ANOMALY_05000323) { \
466 AWA_DUMMY_READ(name); \ 466 AWA_DUMMY_READ(name); \
467 local_irq_restore_hw(flags); \ 467 hard_local_irq_restore(flags); \
468 } \ 468 } \
469 return ret; \ 469 return ret; \
470} \ 470} \
@@ -525,14 +525,14 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
525 if (check_gpio(gpio) < 0) 525 if (check_gpio(gpio) < 0)
526 return -EINVAL; 526 return -EINVAL;
527 527
528 local_irq_save_hw(flags); 528 flags = hard_local_irq_save();
529 if (ctrl) 529 if (ctrl)
530 reserve(wakeup, gpio); 530 reserve(wakeup, gpio);
531 else 531 else
532 unreserve(wakeup, gpio); 532 unreserve(wakeup, gpio);
533 533
534 set_gpio_maskb(gpio, ctrl); 534 set_gpio_maskb(gpio, ctrl);
535 local_irq_restore_hw(flags); 535 hard_local_irq_restore(flags);
536 536
537 return 0; 537 return 0;
538} 538}
@@ -690,7 +690,7 @@ int peripheral_request(unsigned short per, const char *label)
690 690
691 BUG_ON(ident >= MAX_RESOURCES); 691 BUG_ON(ident >= MAX_RESOURCES);
692 692
693 local_irq_save_hw(flags); 693 flags = hard_local_irq_save();
694 694
695 /* If a pin can be muxed as either GPIO or peripheral, make 695 /* If a pin can be muxed as either GPIO or peripheral, make
696 * sure it is not already a GPIO pin when we request it. 696 * sure it is not already a GPIO pin when we request it.
@@ -701,7 +701,7 @@ int peripheral_request(unsigned short per, const char *label)
701 printk(KERN_ERR 701 printk(KERN_ERR
702 "%s: Peripheral %d is already reserved as GPIO by %s !\n", 702 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
703 __func__, ident, get_label(ident)); 703 __func__, ident, get_label(ident));
704 local_irq_restore_hw(flags); 704 hard_local_irq_restore(flags);
705 return -EBUSY; 705 return -EBUSY;
706 } 706 }
707 707
@@ -730,7 +730,7 @@ int peripheral_request(unsigned short per, const char *label)
730 printk(KERN_ERR 730 printk(KERN_ERR
731 "%s: Peripheral %d function %d is already reserved by %s !\n", 731 "%s: Peripheral %d function %d is already reserved by %s !\n",
732 __func__, ident, P_FUNCT2MUX(per), get_label(ident)); 732 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
733 local_irq_restore_hw(flags); 733 hard_local_irq_restore(flags);
734 return -EBUSY; 734 return -EBUSY;
735 } 735 }
736 } 736 }
@@ -741,7 +741,7 @@ int peripheral_request(unsigned short per, const char *label)
741 portmux_setup(per); 741 portmux_setup(per);
742 port_setup(ident, PERIPHERAL_USAGE); 742 port_setup(ident, PERIPHERAL_USAGE);
743 743
744 local_irq_restore_hw(flags); 744 hard_local_irq_restore(flags);
745 set_label(ident, label); 745 set_label(ident, label);
746 746
747 return 0; 747 return 0;
@@ -780,10 +780,10 @@ void peripheral_free(unsigned short per)
780 if (!(per & P_DEFINED)) 780 if (!(per & P_DEFINED))
781 return; 781 return;
782 782
783 local_irq_save_hw(flags); 783 flags = hard_local_irq_save();
784 784
785 if (unlikely(!is_reserved(peri, ident, 0))) { 785 if (unlikely(!is_reserved(peri, ident, 0))) {
786 local_irq_restore_hw(flags); 786 hard_local_irq_restore(flags);
787 return; 787 return;
788 } 788 }
789 789
@@ -794,7 +794,7 @@ void peripheral_free(unsigned short per)
794 794
795 set_label(ident, "free"); 795 set_label(ident, "free");
796 796
797 local_irq_restore_hw(flags); 797 hard_local_irq_restore(flags);
798} 798}
799EXPORT_SYMBOL(peripheral_free); 799EXPORT_SYMBOL(peripheral_free);
800 800
@@ -828,7 +828,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
828 if (check_gpio(gpio) < 0) 828 if (check_gpio(gpio) < 0)
829 return -EINVAL; 829 return -EINVAL;
830 830
831 local_irq_save_hw(flags); 831 flags = hard_local_irq_save();
832 832
833 /* 833 /*
834 * Allow that the identical GPIO can 834 * Allow that the identical GPIO can
@@ -837,7 +837,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
837 */ 837 */
838 838
839 if (cmp_label(gpio, label) == 0) { 839 if (cmp_label(gpio, label) == 0) {
840 local_irq_restore_hw(flags); 840 hard_local_irq_restore(flags);
841 return 0; 841 return 0;
842 } 842 }
843 843
@@ -846,7 +846,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
846 dump_stack(); 846 dump_stack();
847 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", 847 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
848 gpio, get_label(gpio)); 848 gpio, get_label(gpio));
849 local_irq_restore_hw(flags); 849 hard_local_irq_restore(flags);
850 return -EBUSY; 850 return -EBUSY;
851 } 851 }
852 if (unlikely(is_reserved(peri, gpio, 1))) { 852 if (unlikely(is_reserved(peri, gpio, 1))) {
@@ -855,7 +855,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
855 printk(KERN_ERR 855 printk(KERN_ERR
856 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 856 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
857 gpio, get_label(gpio)); 857 gpio, get_label(gpio));
858 local_irq_restore_hw(flags); 858 hard_local_irq_restore(flags);
859 return -EBUSY; 859 return -EBUSY;
860 } 860 }
861 if (unlikely(is_reserved(gpio_irq, gpio, 1))) { 861 if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
@@ -871,7 +871,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
871 reserve(gpio, gpio); 871 reserve(gpio, gpio);
872 set_label(gpio, label); 872 set_label(gpio, label);
873 873
874 local_irq_restore_hw(flags); 874 hard_local_irq_restore(flags);
875 875
876 port_setup(gpio, GPIO_USAGE); 876 port_setup(gpio, GPIO_USAGE);
877 877
@@ -888,13 +888,13 @@ void bfin_gpio_free(unsigned gpio)
888 888
889 might_sleep(); 889 might_sleep();
890 890
891 local_irq_save_hw(flags); 891 flags = hard_local_irq_save();
892 892
893 if (unlikely(!is_reserved(gpio, gpio, 0))) { 893 if (unlikely(!is_reserved(gpio, gpio, 0))) {
894 if (system_state == SYSTEM_BOOTING) 894 if (system_state == SYSTEM_BOOTING)
895 dump_stack(); 895 dump_stack();
896 gpio_error(gpio); 896 gpio_error(gpio);
897 local_irq_restore_hw(flags); 897 hard_local_irq_restore(flags);
898 return; 898 return;
899 } 899 }
900 900
@@ -902,7 +902,7 @@ void bfin_gpio_free(unsigned gpio)
902 902
903 set_label(gpio, "free"); 903 set_label(gpio, "free");
904 904
905 local_irq_restore_hw(flags); 905 hard_local_irq_restore(flags);
906} 906}
907EXPORT_SYMBOL(bfin_gpio_free); 907EXPORT_SYMBOL(bfin_gpio_free);
908 908
@@ -913,7 +913,7 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
913{ 913{
914 unsigned long flags; 914 unsigned long flags;
915 915
916 local_irq_save_hw(flags); 916 flags = hard_local_irq_save();
917 917
918 /* 918 /*
919 * Allow that the identical GPIO can 919 * Allow that the identical GPIO can
@@ -922,19 +922,19 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
922 */ 922 */
923 923
924 if (cmp_label(gpio, label) == 0) { 924 if (cmp_label(gpio, label) == 0) {
925 local_irq_restore_hw(flags); 925 hard_local_irq_restore(flags);
926 return 0; 926 return 0;
927 } 927 }
928 928
929 if (unlikely(is_reserved(special_gpio, gpio, 1))) { 929 if (unlikely(is_reserved(special_gpio, gpio, 1))) {
930 local_irq_restore_hw(flags); 930 hard_local_irq_restore(flags);
931 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", 931 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
932 gpio, get_label(gpio)); 932 gpio, get_label(gpio));
933 933
934 return -EBUSY; 934 return -EBUSY;
935 } 935 }
936 if (unlikely(is_reserved(peri, gpio, 1))) { 936 if (unlikely(is_reserved(peri, gpio, 1))) {
937 local_irq_restore_hw(flags); 937 hard_local_irq_restore(flags);
938 printk(KERN_ERR 938 printk(KERN_ERR
939 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 939 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
940 gpio, get_label(gpio)); 940 gpio, get_label(gpio));
@@ -946,7 +946,7 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
946 reserve(peri, gpio); 946 reserve(peri, gpio);
947 947
948 set_label(gpio, label); 948 set_label(gpio, label);
949 local_irq_restore_hw(flags); 949 hard_local_irq_restore(flags);
950 port_setup(gpio, GPIO_USAGE); 950 port_setup(gpio, GPIO_USAGE);
951 951
952 return 0; 952 return 0;
@@ -959,18 +959,18 @@ void bfin_special_gpio_free(unsigned gpio)
959 959
960 might_sleep(); 960 might_sleep();
961 961
962 local_irq_save_hw(flags); 962 flags = hard_local_irq_save();
963 963
964 if (unlikely(!is_reserved(special_gpio, gpio, 0))) { 964 if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
965 gpio_error(gpio); 965 gpio_error(gpio);
966 local_irq_restore_hw(flags); 966 hard_local_irq_restore(flags);
967 return; 967 return;
968 } 968 }
969 969
970 unreserve(special_gpio, gpio); 970 unreserve(special_gpio, gpio);
971 unreserve(peri, gpio); 971 unreserve(peri, gpio);
972 set_label(gpio, "free"); 972 set_label(gpio, "free");
973 local_irq_restore_hw(flags); 973 hard_local_irq_restore(flags);
974} 974}
975EXPORT_SYMBOL(bfin_special_gpio_free); 975EXPORT_SYMBOL(bfin_special_gpio_free);
976#endif 976#endif
@@ -983,7 +983,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
983 if (check_gpio(gpio) < 0) 983 if (check_gpio(gpio) < 0)
984 return -EINVAL; 984 return -EINVAL;
985 985
986 local_irq_save_hw(flags); 986 flags = hard_local_irq_save();
987 987
988 if (unlikely(is_reserved(peri, gpio, 1))) { 988 if (unlikely(is_reserved(peri, gpio, 1))) {
989 if (system_state == SYSTEM_BOOTING) 989 if (system_state == SYSTEM_BOOTING)
@@ -991,7 +991,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
991 printk(KERN_ERR 991 printk(KERN_ERR
992 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", 992 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
993 gpio, get_label(gpio)); 993 gpio, get_label(gpio));
994 local_irq_restore_hw(flags); 994 hard_local_irq_restore(flags);
995 return -EBUSY; 995 return -EBUSY;
996 } 996 }
997 if (unlikely(is_reserved(gpio, gpio, 1))) 997 if (unlikely(is_reserved(gpio, gpio, 1)))
@@ -1002,7 +1002,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
1002 reserve(gpio_irq, gpio); 1002 reserve(gpio_irq, gpio);
1003 set_label(gpio, label); 1003 set_label(gpio, label);
1004 1004
1005 local_irq_restore_hw(flags); 1005 hard_local_irq_restore(flags);
1006 1006
1007 port_setup(gpio, GPIO_USAGE); 1007 port_setup(gpio, GPIO_USAGE);
1008 1008
@@ -1016,13 +1016,13 @@ void bfin_gpio_irq_free(unsigned gpio)
1016 if (check_gpio(gpio) < 0) 1016 if (check_gpio(gpio) < 0)
1017 return; 1017 return;
1018 1018
1019 local_irq_save_hw(flags); 1019 flags = hard_local_irq_save();
1020 1020
1021 if (unlikely(!is_reserved(gpio_irq, gpio, 0))) { 1021 if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
1022 if (system_state == SYSTEM_BOOTING) 1022 if (system_state == SYSTEM_BOOTING)
1023 dump_stack(); 1023 dump_stack();
1024 gpio_error(gpio); 1024 gpio_error(gpio);
1025 local_irq_restore_hw(flags); 1025 hard_local_irq_restore(flags);
1026 return; 1026 return;
1027 } 1027 }
1028 1028
@@ -1030,7 +1030,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1030 1030
1031 set_label(gpio, "free"); 1031 set_label(gpio, "free");
1032 1032
1033 local_irq_restore_hw(flags); 1033 hard_local_irq_restore(flags);
1034} 1034}
1035 1035
1036static inline void __bfin_gpio_direction_input(unsigned gpio) 1036static inline void __bfin_gpio_direction_input(unsigned gpio)
@@ -1052,10 +1052,10 @@ int bfin_gpio_direction_input(unsigned gpio)
1052 return -EINVAL; 1052 return -EINVAL;
1053 } 1053 }
1054 1054
1055 local_irq_save_hw(flags); 1055 flags = hard_local_irq_save();
1056 __bfin_gpio_direction_input(gpio); 1056 __bfin_gpio_direction_input(gpio);
1057 AWA_DUMMY_READ(inen); 1057 AWA_DUMMY_READ(inen);
1058 local_irq_restore_hw(flags); 1058 hard_local_irq_restore(flags);
1059 1059
1060 return 0; 1060 return 0;
1061} 1061}
@@ -1070,9 +1070,9 @@ void bfin_gpio_irq_prepare(unsigned gpio)
1070 port_setup(gpio, GPIO_USAGE); 1070 port_setup(gpio, GPIO_USAGE);
1071 1071
1072#ifdef CONFIG_BF54x 1072#ifdef CONFIG_BF54x
1073 local_irq_save_hw(flags); 1073 flags = hard_local_irq_save();
1074 __bfin_gpio_direction_input(gpio); 1074 __bfin_gpio_direction_input(gpio);
1075 local_irq_restore_hw(flags); 1075 hard_local_irq_restore(flags);
1076#endif 1076#endif
1077} 1077}
1078 1078
@@ -1094,7 +1094,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1094 return -EINVAL; 1094 return -EINVAL;
1095 } 1095 }
1096 1096
1097 local_irq_save_hw(flags); 1097 flags = hard_local_irq_save();
1098 1098
1099 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1099 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1100 gpio_set_value(gpio, value); 1100 gpio_set_value(gpio, value);
@@ -1105,7 +1105,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1105#endif 1105#endif
1106 1106
1107 AWA_DUMMY_READ(dir); 1107 AWA_DUMMY_READ(dir);
1108 local_irq_restore_hw(flags); 1108 hard_local_irq_restore(flags);
1109 1109
1110 return 0; 1110 return 0;
1111} 1111}
@@ -1120,11 +1120,11 @@ int bfin_gpio_get_value(unsigned gpio)
1120 1120
1121 if (unlikely(get_gpio_edge(gpio))) { 1121 if (unlikely(get_gpio_edge(gpio))) {
1122 int ret; 1122 int ret;
1123 local_irq_save_hw(flags); 1123 flags = hard_local_irq_save();
1124 set_gpio_edge(gpio, 0); 1124 set_gpio_edge(gpio, 0);
1125 ret = get_gpio_data(gpio); 1125 ret = get_gpio_data(gpio);
1126 set_gpio_edge(gpio, 1); 1126 set_gpio_edge(gpio, 1);
1127 local_irq_restore_hw(flags); 1127 hard_local_irq_restore(flags);
1128 return ret; 1128 return ret;
1129 } else 1129 } else
1130 return get_gpio_data(gpio); 1130 return get_gpio_data(gpio);
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 87b25b1b30ed..8de92299b3ee 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -318,7 +318,7 @@ void flush_switched_cplbs(unsigned int cpu)
318 318
319 nr_cplb_flush[cpu]++; 319 nr_cplb_flush[cpu]++;
320 320
321 local_irq_save_hw(flags); 321 flags = hard_local_irq_save();
322 _disable_icplb(); 322 _disable_icplb();
323 for (i = first_switched_icplb; i < MAX_CPLBS; i++) { 323 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
324 icplb_tbl[cpu][i].data = 0; 324 icplb_tbl[cpu][i].data = 0;
@@ -332,7 +332,7 @@ void flush_switched_cplbs(unsigned int cpu)
332 bfin_write32(DCPLB_DATA0 + i * 4, 0); 332 bfin_write32(DCPLB_DATA0 + i * 4, 0);
333 } 333 }
334 _enable_dcplb(); 334 _enable_dcplb();
335 local_irq_restore_hw(flags); 335 hard_local_irq_restore(flags);
336 336
337} 337}
338 338
@@ -348,7 +348,7 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
348 return; 348 return;
349 } 349 }
350 350
351 local_irq_save_hw(flags); 351 flags = hard_local_irq_save();
352 current_rwx_mask[cpu] = masks; 352 current_rwx_mask[cpu] = masks;
353 353
354 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { 354 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
@@ -373,5 +373,5 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
373 addr += PAGE_SIZE; 373 addr += PAGE_SIZE;
374 } 374 }
375 _enable_dcplb(); 375 _enable_dcplb();
376 local_irq_restore_hw(flags); 376 hard_local_irq_restore(flags);
377} 377}
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 1a496cd71ba2..3b1da4aff2a1 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -219,10 +219,10 @@ int __ipipe_syscall_root(struct pt_regs *regs)
219 219
220 ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs); 220 ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
221 221
222 local_irq_save_hw(flags); 222 flags = hard_local_irq_save();
223 223
224 if (!__ipipe_root_domain_p) { 224 if (!__ipipe_root_domain_p) {
225 local_irq_restore_hw(flags); 225 hard_local_irq_restore(flags);
226 return 1; 226 return 1;
227 } 227 }
228 228
@@ -230,7 +230,7 @@ int __ipipe_syscall_root(struct pt_regs *regs)
230 if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0) 230 if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0)
231 __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); 231 __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
232 232
233 local_irq_restore_hw(flags); 233 hard_local_irq_restore(flags);
234 234
235 return -ret; 235 return -ret;
236} 236}
@@ -239,14 +239,14 @@ unsigned long ipipe_critical_enter(void (*syncfn) (void))
239{ 239{
240 unsigned long flags; 240 unsigned long flags;
241 241
242 local_irq_save_hw(flags); 242 flags = hard_local_irq_save();
243 243
244 return flags; 244 return flags;
245} 245}
246 246
247void ipipe_critical_exit(unsigned long flags) 247void ipipe_critical_exit(unsigned long flags)
248{ 248{
249 local_irq_restore_hw(flags); 249 hard_local_irq_restore(flags);
250} 250}
251 251
252static void __ipipe_no_irqtail(void) 252static void __ipipe_no_irqtail(void)
@@ -279,9 +279,9 @@ int ipipe_trigger_irq(unsigned irq)
279 return -EINVAL; 279 return -EINVAL;
280#endif 280#endif
281 281
282 local_irq_save_hw(flags); 282 flags = hard_local_irq_save();
283 __ipipe_handle_irq(irq, NULL); 283 __ipipe_handle_irq(irq, NULL);
284 local_irq_restore_hw(flags); 284 hard_local_irq_restore(flags);
285 285
286 return 1; 286 return 1;
287} 287}
@@ -293,7 +293,7 @@ asmlinkage void __ipipe_sync_root(void)
293 293
294 BUG_ON(irqs_disabled()); 294 BUG_ON(irqs_disabled());
295 295
296 local_irq_save_hw(flags); 296 flags = hard_local_irq_save();
297 297
298 if (irq_tail_hook) 298 if (irq_tail_hook)
299 irq_tail_hook(); 299 irq_tail_hook();
@@ -303,7 +303,7 @@ asmlinkage void __ipipe_sync_root(void)
303 if (ipipe_root_cpudom_var(irqpend_himask) != 0) 303 if (ipipe_root_cpudom_var(irqpend_himask) != 0)
304 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY); 304 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
305 305
306 local_irq_restore_hw(flags); 306 hard_local_irq_restore(flags);
307} 307}
308 308
309void ___ipipe_sync_pipeline(unsigned long syncmask) 309void ___ipipe_sync_pipeline(unsigned long syncmask)
@@ -344,10 +344,10 @@ void __ipipe_stall_root(void)
344{ 344{
345 unsigned long *p, flags; 345 unsigned long *p, flags;
346 346
347 local_irq_save_hw(flags); 347 flags = hard_local_irq_save();
348 p = &__ipipe_root_status; 348 p = &__ipipe_root_status;
349 __set_bit(IPIPE_STALL_FLAG, p); 349 __set_bit(IPIPE_STALL_FLAG, p);
350 local_irq_restore_hw(flags); 350 hard_local_irq_restore(flags);
351} 351}
352EXPORT_SYMBOL(__ipipe_stall_root); 352EXPORT_SYMBOL(__ipipe_stall_root);
353 353
@@ -356,10 +356,10 @@ unsigned long __ipipe_test_and_stall_root(void)
356 unsigned long *p, flags; 356 unsigned long *p, flags;
357 int x; 357 int x;
358 358
359 local_irq_save_hw(flags); 359 flags = hard_local_irq_save();
360 p = &__ipipe_root_status; 360 p = &__ipipe_root_status;
361 x = __test_and_set_bit(IPIPE_STALL_FLAG, p); 361 x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
362 local_irq_restore_hw(flags); 362 hard_local_irq_restore(flags);
363 363
364 return x; 364 return x;
365} 365}
@@ -371,10 +371,10 @@ unsigned long __ipipe_test_root(void)
371 unsigned long flags; 371 unsigned long flags;
372 int x; 372 int x;
373 373
374 local_irq_save_hw_smp(flags); 374 flags = hard_local_irq_save_smp();
375 p = &__ipipe_root_status; 375 p = &__ipipe_root_status;
376 x = test_bit(IPIPE_STALL_FLAG, p); 376 x = test_bit(IPIPE_STALL_FLAG, p);
377 local_irq_restore_hw_smp(flags); 377 hard_local_irq_restore_smp(flags);
378 378
379 return x; 379 return x;
380} 380}
@@ -384,10 +384,10 @@ void __ipipe_lock_root(void)
384{ 384{
385 unsigned long *p, flags; 385 unsigned long *p, flags;
386 386
387 local_irq_save_hw(flags); 387 flags = hard_local_irq_save();
388 p = &__ipipe_root_status; 388 p = &__ipipe_root_status;
389 __set_bit(IPIPE_SYNCDEFER_FLAG, p); 389 __set_bit(IPIPE_SYNCDEFER_FLAG, p);
390 local_irq_restore_hw(flags); 390 hard_local_irq_restore(flags);
391} 391}
392EXPORT_SYMBOL(__ipipe_lock_root); 392EXPORT_SYMBOL(__ipipe_lock_root);
393 393
@@ -395,9 +395,9 @@ void __ipipe_unlock_root(void)
395{ 395{
396 unsigned long *p, flags; 396 unsigned long *p, flags;
397 397
398 local_irq_save_hw(flags); 398 flags = hard_local_irq_save();
399 p = &__ipipe_root_status; 399 p = &__ipipe_root_status;
400 __clear_bit(IPIPE_SYNCDEFER_FLAG, p); 400 __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
401 local_irq_restore_hw(flags); 401 hard_local_irq_restore(flags);
402} 402}
403EXPORT_SYMBOL(__ipipe_unlock_root); 403EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 01f98cb964d2..c86a3ed5f48f 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -65,11 +65,11 @@ static void default_idle(void)
65#ifdef CONFIG_IPIPE 65#ifdef CONFIG_IPIPE
66 ipipe_suspend_domain(); 66 ipipe_suspend_domain();
67#endif 67#endif
68 local_irq_disable_hw(); 68 hard_local_irq_disable();
69 if (!need_resched()) 69 if (!need_resched())
70 idle_with_irq_disabled(); 70 idle_with_irq_disabled();
71 71
72 local_irq_enable_hw(); 72 hard_local_irq_enable();
73} 73}
74 74
75/* 75/*
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index 59fcdf6b0138..05b550891ce5 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -15,6 +15,7 @@
15#include <linux/kallsyms.h> 15#include <linux/kallsyms.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/fs.h> 17#include <linux/fs.h>
18#include <linux/irq.h>
18#include <asm/dma.h> 19#include <asm/dma.h>
19#include <asm/trace.h> 20#include <asm/trace.h>
20#include <asm/fixed_code.h> 21#include <asm/fixed_code.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index e548e9d1d6fa..29498e59e71f 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -1058,54 +1058,4 @@
1058/* These need to be last due to the cdef/linux inter-dependencies */ 1058/* These need to be last due to the cdef/linux inter-dependencies */
1059#include <asm/irq.h> 1059#include <asm/irq.h>
1060 1060
1061/* Writing to PLL_CTL initiates a PLL relock sequence. */
1062static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1063{
1064 unsigned long flags, iwr0, iwr1;
1065
1066 if (val == bfin_read_PLL_CTL())
1067 return;
1068
1069 local_irq_save_hw(flags);
1070 /* Enable the PLL Wakeup bit in SIC IWR */
1071 iwr0 = bfin_read32(SIC_IWR0);
1072 iwr1 = bfin_read32(SIC_IWR1);
1073 /* Only allow PPL Wakeup) */
1074 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1075 bfin_write32(SIC_IWR1, 0);
1076
1077 bfin_write16(PLL_CTL, val);
1078 SSYNC();
1079 asm("IDLE;");
1080
1081 bfin_write32(SIC_IWR0, iwr0);
1082 bfin_write32(SIC_IWR1, iwr1);
1083 local_irq_restore_hw(flags);
1084}
1085
1086/* Writing to VR_CTL initiates a PLL relock sequence. */
1087static __inline__ void bfin_write_VR_CTL(unsigned int val)
1088{
1089 unsigned long flags, iwr0, iwr1;
1090
1091 if (val == bfin_read_VR_CTL())
1092 return;
1093
1094 local_irq_save_hw(flags);
1095 /* Enable the PLL Wakeup bit in SIC IWR */
1096 iwr0 = bfin_read32(SIC_IWR0);
1097 iwr1 = bfin_read32(SIC_IWR1);
1098 /* Only allow PPL Wakeup) */
1099 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1100 bfin_write32(SIC_IWR1, 0);
1101
1102 bfin_write16(VR_CTL, val);
1103 SSYNC();
1104 asm("IDLE;");
1105
1106 bfin_write32(SIC_IWR0, iwr0);
1107 bfin_write32(SIC_IWR1, iwr1);
1108 local_irq_restore_hw(flags);
1109}
1110
1111#endif /* _CDEF_BF52X_H */ 1061#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
new file mode 100644
index 000000000000..d5502988896b
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 12f2ad45314e..11fb27bc427d 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -1110,54 +1110,4 @@
1110/* These need to be last due to the cdef/linux inter-dependencies */ 1110/* These need to be last due to the cdef/linux inter-dependencies */
1111#include <asm/irq.h> 1111#include <asm/irq.h>
1112 1112
1113/* Writing to PLL_CTL initiates a PLL relock sequence. */
1114static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1115{
1116 unsigned long flags, iwr0, iwr1;
1117
1118 if (val == bfin_read_PLL_CTL())
1119 return;
1120
1121 local_irq_save_hw(flags);
1122 /* Enable the PLL Wakeup bit in SIC IWR */
1123 iwr0 = bfin_read32(SIC_IWR0);
1124 iwr1 = bfin_read32(SIC_IWR1);
1125 /* Only allow PPL Wakeup) */
1126 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1127 bfin_write32(SIC_IWR1, 0);
1128
1129 bfin_write16(PLL_CTL, val);
1130 SSYNC();
1131 asm("IDLE;");
1132
1133 bfin_write32(SIC_IWR0, iwr0);
1134 bfin_write32(SIC_IWR1, iwr1);
1135 local_irq_restore_hw(flags);
1136}
1137
1138/* Writing to VR_CTL initiates a PLL relock sequence. */
1139static __inline__ void bfin_write_VR_CTL(unsigned int val)
1140{
1141 unsigned long flags, iwr0, iwr1;
1142
1143 if (val == bfin_read_VR_CTL())
1144 return;
1145
1146 local_irq_save_hw(flags);
1147 /* Enable the PLL Wakeup bit in SIC IWR */
1148 iwr0 = bfin_read32(SIC_IWR0);
1149 iwr1 = bfin_read32(SIC_IWR1);
1150 /* Only allow PPL Wakeup) */
1151 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1152 bfin_write32(SIC_IWR1, 0);
1153
1154 bfin_write16(VR_CTL, val);
1155 SSYNC();
1156 asm("IDLE;");
1157
1158 bfin_write32(SIC_IWR0, iwr0);
1159 bfin_write32(SIC_IWR1, iwr1);
1160 local_irq_restore_hw(flags);
1161}
1162
1163#endif /* _CDEF_BF52X_H */ 1113#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
new file mode 100644
index 000000000000..24f1d7c02325
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 842b4fa76ea9..84a06f677dff 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -25,6 +25,7 @@
25#include <asm/bfin5xx_spi.h> 25#include <asm/bfin5xx_spi.h>
26#include <asm/portmux.h> 26#include <asm/portmux.h>
27#include <asm/dpmc.h> 27#include <asm/dpmc.h>
28#include <mach/fio_flag.h>
28 29
29/* 30/*
30 * Name the Board for the /proc/cpuinfo 31 * Name the Board for the /proc/cpuinfo
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 7349970db978..b8474cac6b03 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -22,6 +22,7 @@
22#include <asm/dma.h> 22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h> 23#include <asm/bfin5xx_spi.h>
24#include <asm/portmux.h> 24#include <asm/portmux.h>
25#include <mach/fio_flag.h>
25 26
26/* 27/*
27 * Name the Board for the /proc/cpuinfo 28 * Name the Board for the /proc/cpuinfo
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index c457eaa60239..29c219eff2ff 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -24,6 +24,7 @@
24#include <asm/reboot.h> 24#include <asm/reboot.h>
25#include <asm/portmux.h> 25#include <asm/portmux.h>
26#include <asm/dpmc.h> 26#include <asm/dpmc.h>
27#include <mach/fio_flag.h>
27 28
28/* 29/*
29 * Name the Board for the /proc/cpuinfo 30 * Name the Board for the /proc/cpuinfo
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index feb2392c43ea..401e524f5321 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -7,11 +7,6 @@
7#ifndef _CDEF_BF532_H 7#ifndef _CDEF_BF532_H
8#define _CDEF_BF532_H 8#define _CDEF_BF532_H
9 9
10#include <asm/blackfin.h>
11
12/*include all Core registers and bit definitions*/
13#include "defBF532.h"
14
15/*include core specific register pointer definitions*/ 10/*include core specific register pointer definitions*/
16#include <asm/cdef_LPBlackfin.h> 11#include <asm/cdef_LPBlackfin.h>
17 12
@@ -655,90 +650,4 @@
655/* These need to be last due to the cdef/linux inter-dependencies */ 650/* These need to be last due to the cdef/linux inter-dependencies */
656#include <asm/irq.h> 651#include <asm/irq.h>
657 652
658#if ANOMALY_05000311
659#define BFIN_WRITE_FIO_FLAG(name) \
660static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
661{ \
662 unsigned long flags; \
663 local_irq_save_hw(flags); \
664 bfin_write16(FIO_FLAG_##name, val); \
665 bfin_read_CHIPID(); \
666 local_irq_restore_hw(flags); \
667}
668BFIN_WRITE_FIO_FLAG(D)
669BFIN_WRITE_FIO_FLAG(C)
670BFIN_WRITE_FIO_FLAG(S)
671BFIN_WRITE_FIO_FLAG(T)
672
673#define BFIN_READ_FIO_FLAG(name) \
674static inline u16 bfin_read_FIO_FLAG_##name(void) \
675{ \
676 unsigned long flags; \
677 u16 ret; \
678 local_irq_save_hw(flags); \
679 ret = bfin_read16(FIO_FLAG_##name); \
680 bfin_read_CHIPID(); \
681 local_irq_restore_hw(flags); \
682 return ret; \
683}
684BFIN_READ_FIO_FLAG(D)
685BFIN_READ_FIO_FLAG(C)
686BFIN_READ_FIO_FLAG(S)
687BFIN_READ_FIO_FLAG(T)
688
689#else
690#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
691#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
692#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
693#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
694#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
695#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
696#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
697#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
698#endif
699
700/* Writing to PLL_CTL initiates a PLL relock sequence. */
701static __inline__ void bfin_write_PLL_CTL(unsigned int val)
702{
703 unsigned long flags, iwr;
704
705 if (val == bfin_read_PLL_CTL())
706 return;
707
708 local_irq_save_hw(flags);
709 /* Enable the PLL Wakeup bit in SIC IWR */
710 iwr = bfin_read32(SIC_IWR);
711 /* Only allow PPL Wakeup) */
712 bfin_write32(SIC_IWR, IWR_ENABLE(0));
713
714 bfin_write16(PLL_CTL, val);
715 SSYNC();
716 asm("IDLE;");
717
718 bfin_write32(SIC_IWR, iwr);
719 local_irq_restore_hw(flags);
720}
721
722/* Writing to VR_CTL initiates a PLL relock sequence. */
723static __inline__ void bfin_write_VR_CTL(unsigned int val)
724{
725 unsigned long flags, iwr;
726
727 if (val == bfin_read_VR_CTL())
728 return;
729
730 local_irq_save_hw(flags);
731 /* Enable the PLL Wakeup bit in SIC IWR */
732 iwr = bfin_read32(SIC_IWR);
733 /* Only allow PPL Wakeup) */
734 bfin_write32(SIC_IWR, IWR_ENABLE(0));
735
736 bfin_write16(VR_CTL, val);
737 SSYNC();
738 asm("IDLE;");
739
740 bfin_write32(SIC_IWR, iwr);
741 local_irq_restore_hw(flags);
742}
743
744#endif /* _CDEF_BF532_H */ 653#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
new file mode 100644
index 000000000000..d0bfba0b083b
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_FIO_FLAG_H
8#define _MACH_FIO_FLAG_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13#if ANOMALY_05000311
14#define BFIN_WRITE_FIO_FLAG(name) \
15static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
16{ \
17 unsigned long flags; \
18 flags = hard_local_irq_save(); \
19 bfin_write16(FIO_FLAG_##name, val); \
20 bfin_read_CHIPID(); \
21 hard_local_irq_restore(flags); \
22}
23BFIN_WRITE_FIO_FLAG(D)
24BFIN_WRITE_FIO_FLAG(C)
25BFIN_WRITE_FIO_FLAG(S)
26BFIN_WRITE_FIO_FLAG(T)
27
28#define BFIN_READ_FIO_FLAG(name) \
29static inline u16 bfin_read_FIO_FLAG_##name(void) \
30{ \
31 unsigned long flags; \
32 u16 ret; \
33 flags = hard_local_irq_save(); \
34 ret = bfin_read16(FIO_FLAG_##name); \
35 bfin_read_CHIPID(); \
36 hard_local_irq_restore(flags); \
37 return ret; \
38}
39BFIN_READ_FIO_FLAG(D)
40BFIN_READ_FIO_FLAG(C)
41BFIN_READ_FIO_FLAG(S)
42BFIN_READ_FIO_FLAG(T)
43
44#else
45#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
46#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
47#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
48#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
49#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
50#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
51#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
52#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
53#endif
54
55#endif /* _MACH_FIO_FLAG_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
new file mode 100644
index 000000000000..169c106d0edb
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index 91825c9bd226..fbeb35e14135 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1750,48 +1750,4 @@
1750/* These need to be last due to the cdef/linux inter-dependencies */ 1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h> 1751#include <asm/irq.h>
1752 1752
1753/* Writing to PLL_CTL initiates a PLL relock sequence. */
1754static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1755{
1756 unsigned long flags, iwr;
1757
1758 if (val == bfin_read_PLL_CTL())
1759 return;
1760
1761 local_irq_save_hw(flags);
1762 /* Enable the PLL Wakeup bit in SIC IWR */
1763 iwr = bfin_read32(SIC_IWR);
1764 /* Only allow PPL Wakeup) */
1765 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1766
1767 bfin_write16(PLL_CTL, val);
1768 SSYNC();
1769 asm("IDLE;");
1770
1771 bfin_write32(SIC_IWR, iwr);
1772 local_irq_restore_hw(flags);
1773}
1774
1775/* Writing to VR_CTL initiates a PLL relock sequence. */
1776static __inline__ void bfin_write_VR_CTL(unsigned int val)
1777{
1778 unsigned long flags, iwr;
1779
1780 if (val == bfin_read_VR_CTL())
1781 return;
1782
1783 local_irq_save_hw(flags);
1784 /* Enable the PLL Wakeup bit in SIC IWR */
1785 iwr = bfin_read32(SIC_IWR);
1786 /* Only allow PPL Wakeup) */
1787 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1788
1789 bfin_write16(VR_CTL, val);
1790 SSYNC();
1791 asm("IDLE;");
1792
1793 bfin_write32(SIC_IWR, iwr);
1794 local_irq_restore_hw(flags);
1795}
1796
1797#endif /* _CDEF_BF534_H */ 1753#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
new file mode 100644
index 000000000000..169c106d0edb
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 66aa722cf6c8..085b06b8c0a5 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -2027,54 +2027,4 @@
2027/* These need to be last due to the cdef/linux inter-dependencies */ 2027/* These need to be last due to the cdef/linux inter-dependencies */
2028#include <asm/irq.h> 2028#include <asm/irq.h>
2029 2029
2030/* Writing to PLL_CTL initiates a PLL relock sequence. */
2031static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2032{
2033 unsigned long flags, iwr0, iwr1;
2034
2035 if (val == bfin_read_PLL_CTL())
2036 return;
2037
2038 local_irq_save_hw(flags);
2039 /* Enable the PLL Wakeup bit in SIC IWR */
2040 iwr0 = bfin_read32(SIC_IWR0);
2041 iwr1 = bfin_read32(SIC_IWR1);
2042 /* Only allow PPL Wakeup) */
2043 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2044 bfin_write32(SIC_IWR1, 0);
2045
2046 bfin_write16(PLL_CTL, val);
2047 SSYNC();
2048 asm("IDLE;");
2049
2050 bfin_write32(SIC_IWR0, iwr0);
2051 bfin_write32(SIC_IWR1, iwr1);
2052 local_irq_restore_hw(flags);
2053}
2054
2055/* Writing to VR_CTL initiates a PLL relock sequence. */
2056static __inline__ void bfin_write_VR_CTL(unsigned int val)
2057{
2058 unsigned long flags, iwr0, iwr1;
2059
2060 if (val == bfin_read_VR_CTL())
2061 return;
2062
2063 local_irq_save_hw(flags);
2064 /* Enable the PLL Wakeup bit in SIC IWR */
2065 iwr0 = bfin_read32(SIC_IWR0);
2066 iwr1 = bfin_read32(SIC_IWR1);
2067 /* Only allow PPL Wakeup) */
2068 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2069 bfin_write32(SIC_IWR1, 0);
2070
2071 bfin_write16(VR_CTL, val);
2072 SSYNC();
2073 asm("IDLE;");
2074
2075 bfin_write32(SIC_IWR0, iwr0);
2076 bfin_write32(SIC_IWR1, iwr1);
2077 local_irq_restore_hw(flags);
2078}
2079
2080#endif 2030#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
new file mode 100644
index 000000000000..b30bbcd412a7
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2008-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index ea3ec4ea9e2b..0c16067df4f3 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2648,61 +2648,5 @@
2648/* These need to be last due to the cdef/linux inter-dependencies */ 2648/* These need to be last due to the cdef/linux inter-dependencies */
2649#include <asm/irq.h> 2649#include <asm/irq.h>
2650 2650
2651/* Writing to PLL_CTL initiates a PLL relock sequence. */
2652static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2653{
2654 unsigned long flags, iwr0, iwr1, iwr2;
2655
2656 if (val == bfin_read_PLL_CTL())
2657 return;
2658
2659 local_irq_save_hw(flags);
2660 /* Enable the PLL Wakeup bit in SIC IWR */
2661 iwr0 = bfin_read32(SIC_IWR0);
2662 iwr1 = bfin_read32(SIC_IWR1);
2663 iwr2 = bfin_read32(SIC_IWR2);
2664 /* Only allow PPL Wakeup) */
2665 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2666 bfin_write32(SIC_IWR1, 0);
2667 bfin_write32(SIC_IWR2, 0);
2668
2669 bfin_write16(PLL_CTL, val);
2670 SSYNC();
2671 asm("IDLE;");
2672
2673 bfin_write32(SIC_IWR0, iwr0);
2674 bfin_write32(SIC_IWR1, iwr1);
2675 bfin_write32(SIC_IWR2, iwr2);
2676 local_irq_restore_hw(flags);
2677}
2678
2679/* Writing to VR_CTL initiates a PLL relock sequence. */
2680static __inline__ void bfin_write_VR_CTL(unsigned int val)
2681{
2682 unsigned long flags, iwr0, iwr1, iwr2;
2683
2684 if (val == bfin_read_VR_CTL())
2685 return;
2686
2687 local_irq_save_hw(flags);
2688 /* Enable the PLL Wakeup bit in SIC IWR */
2689 iwr0 = bfin_read32(SIC_IWR0);
2690 iwr1 = bfin_read32(SIC_IWR1);
2691 iwr2 = bfin_read32(SIC_IWR2);
2692 /* Only allow PPL Wakeup) */
2693 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2694 bfin_write32(SIC_IWR1, 0);
2695 bfin_write32(SIC_IWR2, 0);
2696
2697 bfin_write16(VR_CTL, val);
2698 SSYNC();
2699 asm("IDLE;");
2700
2701 bfin_write32(SIC_IWR0, iwr0);
2702 bfin_write32(SIC_IWR1, iwr1);
2703 bfin_write32(SIC_IWR2, iwr2);
2704 local_irq_restore_hw(flags);
2705}
2706
2707#endif /* _CDEF_BF54X_H */ 2651#endif /* _CDEF_BF54X_H */
2708 2652
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
new file mode 100644
index 000000000000..7865a090d333
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
67}
68
69#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 81ecdb71c6af..cc0416a5fa02 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1534,54 +1534,4 @@
1534/* These need to be last due to the cdef/linux inter-dependencies */ 1534/* These need to be last due to the cdef/linux inter-dependencies */
1535#include <asm/irq.h> 1535#include <asm/irq.h>
1536 1536
1537/* Writing to PLL_CTL initiates a PLL relock sequence. */
1538static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1539{
1540 unsigned long flags, iwr0, iwr1;
1541
1542 if (val == bfin_read_PLL_CTL())
1543 return;
1544
1545 local_irq_save_hw(flags);
1546 /* Enable the PLL Wakeup bit in SIC IWR */
1547 iwr0 = bfin_read32(SICA_IWR0);
1548 iwr1 = bfin_read32(SICA_IWR1);
1549 /* Only allow PPL Wakeup) */
1550 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1551 bfin_write32(SICA_IWR1, 0);
1552
1553 bfin_write16(PLL_CTL, val);
1554 SSYNC();
1555 asm("IDLE;");
1556
1557 bfin_write32(SICA_IWR0, iwr0);
1558 bfin_write32(SICA_IWR1, iwr1);
1559 local_irq_restore_hw(flags);
1560}
1561
1562/* Writing to VR_CTL initiates a PLL relock sequence. */
1563static __inline__ void bfin_write_VR_CTL(unsigned int val)
1564{
1565 unsigned long flags, iwr0, iwr1;
1566
1567 if (val == bfin_read_VR_CTL())
1568 return;
1569
1570 local_irq_save_hw(flags);
1571 /* Enable the PLL Wakeup bit in SIC IWR */
1572 iwr0 = bfin_read32(SICA_IWR0);
1573 iwr1 = bfin_read32(SICA_IWR1);
1574 /* Only allow PPL Wakeup) */
1575 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1576 bfin_write32(SICA_IWR1, 0);
1577
1578 bfin_write16(VR_CTL, val);
1579 SSYNC();
1580 asm("IDLE;");
1581
1582 bfin_write32(SICA_IWR0, iwr0);
1583 bfin_write32(SICA_IWR1, iwr1);
1584 local_irq_restore_hw(flags);
1585}
1586
1587#endif /* _CDEF_BF561_H */ 1537#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
new file mode 100644
index 000000000000..f2b1fbdb8e72
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2005-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SICA_IWR0);
24 iwr1 = bfin_read32(SICA_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
27 bfin_write32(SICA_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SICA_IWR0, iwr0);
34 bfin_write32(SICA_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SICA_IWR0);
49 iwr1 = bfin_read32(SICA_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
52 bfin_write32(SICA_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SICA_IWR0, iwr0);
59 bfin_write32(SICA_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 4391d03dc845..f4cf11d362e1 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -134,7 +134,7 @@ static int bfin_target(struct cpufreq_policy *poli,
134 134
135 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 135 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
136 if (cpu == CPUFREQ_CPU) { 136 if (cpu == CPUFREQ_CPU) {
137 local_irq_save_hw(flags); 137 flags = hard_local_irq_save();
138 plldiv = (bfin_read_PLL_DIV() & SSEL) | 138 plldiv = (bfin_read_PLL_DIV() & SSEL) |
139 dpm_state_table[index].csel; 139 dpm_state_table[index].csel;
140 bfin_write_PLL_DIV(plldiv); 140 bfin_write_PLL_DIV(plldiv);
@@ -155,7 +155,7 @@ static int bfin_target(struct cpufreq_policy *poli,
155 loops_per_jiffy = cpufreq_scale(lpj_ref, 155 loops_per_jiffy = cpufreq_scale(lpj_ref,
156 lpj_ref_freq, freqs.new); 156 lpj_ref_freq, freqs.new);
157 } 157 }
158 local_irq_restore_hw(flags); 158 hard_local_irq_restore(flags);
159 } 159 }
160 /* TODO: just test case for cycles clock source, remove later */ 160 /* TODO: just test case for cycles clock source, remove later */
161 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 161 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1c8c4c7245c3..eaece5f84e42 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -132,8 +132,8 @@ static void bfin_ack_noop(unsigned int irq)
132static void bfin_core_mask_irq(unsigned int irq) 132static void bfin_core_mask_irq(unsigned int irq)
133{ 133{
134 bfin_irq_flags &= ~(1 << irq); 134 bfin_irq_flags &= ~(1 << irq);
135 if (!irqs_disabled_hw()) 135 if (!hard_irqs_disabled())
136 local_irq_enable_hw(); 136 hard_local_irq_enable();
137} 137}
138 138
139static void bfin_core_unmask_irq(unsigned int irq) 139static void bfin_core_unmask_irq(unsigned int irq)
@@ -148,8 +148,8 @@ static void bfin_core_unmask_irq(unsigned int irq)
148 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly 148 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
149 * what we need. 149 * what we need.
150 */ 150 */
151 if (!irqs_disabled_hw()) 151 if (!hard_irqs_disabled())
152 local_irq_enable_hw(); 152 hard_local_irq_enable();
153 return; 153 return;
154} 154}
155 155
@@ -158,12 +158,12 @@ static void bfin_internal_mask_irq(unsigned int irq)
158 unsigned long flags; 158 unsigned long flags;
159 159
160#ifdef CONFIG_BF53x 160#ifdef CONFIG_BF53x
161 local_irq_save_hw(flags); 161 flags = hard_local_irq_save();
162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
163 ~(1 << SIC_SYSIRQ(irq))); 163 ~(1 << SIC_SYSIRQ(irq)));
164#else 164#else
165 unsigned mask_bank, mask_bit; 165 unsigned mask_bank, mask_bit;
166 local_irq_save_hw(flags); 166 flags = hard_local_irq_save();
167 mask_bank = SIC_SYSIRQ(irq) / 32; 167 mask_bank = SIC_SYSIRQ(irq) / 32;
168 mask_bit = SIC_SYSIRQ(irq) % 32; 168 mask_bit = SIC_SYSIRQ(irq) % 32;
169 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 169 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
@@ -173,7 +173,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
173 ~(1 << mask_bit)); 173 ~(1 << mask_bit));
174#endif 174#endif
175#endif 175#endif
176 local_irq_restore_hw(flags); 176 hard_local_irq_restore(flags);
177} 177}
178 178
179#ifdef CONFIG_SMP 179#ifdef CONFIG_SMP
@@ -186,12 +186,12 @@ static void bfin_internal_unmask_irq(unsigned int irq)
186 unsigned long flags; 186 unsigned long flags;
187 187
188#ifdef CONFIG_BF53x 188#ifdef CONFIG_BF53x
189 local_irq_save_hw(flags); 189 flags = hard_local_irq_save();
190 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 190 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
191 (1 << SIC_SYSIRQ(irq))); 191 (1 << SIC_SYSIRQ(irq)));
192#else 192#else
193 unsigned mask_bank, mask_bit; 193 unsigned mask_bank, mask_bit;
194 local_irq_save_hw(flags); 194 flags = hard_local_irq_save();
195 mask_bank = SIC_SYSIRQ(irq) / 32; 195 mask_bank = SIC_SYSIRQ(irq) / 32;
196 mask_bit = SIC_SYSIRQ(irq) % 32; 196 mask_bit = SIC_SYSIRQ(irq) % 32;
197#ifdef CONFIG_SMP 197#ifdef CONFIG_SMP
@@ -207,7 +207,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
207 (1 << mask_bit)); 207 (1 << mask_bit));
208#endif 208#endif
209#endif 209#endif
210 local_irq_restore_hw(flags); 210 hard_local_irq_restore(flags);
211} 211}
212 212
213#ifdef CONFIG_SMP 213#ifdef CONFIG_SMP
@@ -264,7 +264,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
264 break; 264 break;
265 } 265 }
266 266
267 local_irq_save_hw(flags); 267 flags = hard_local_irq_save();
268 268
269 if (state) { 269 if (state) {
270 bfin_sic_iwr[bank] |= (1 << bit); 270 bfin_sic_iwr[bank] |= (1 << bit);
@@ -275,7 +275,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
275 vr_wakeup &= ~wakeup; 275 vr_wakeup &= ~wakeup;
276 } 276 }
277 277
278 local_irq_restore_hw(flags); 278 hard_local_irq_restore(flags);
279 279
280 return 0; 280 return 0;
281} 281}
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 09c1fb410748..80884b136a0c 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -25,7 +25,7 @@ void bfin_pm_suspend_standby_enter(void)
25{ 25{
26 unsigned long flags; 26 unsigned long flags;
27 27
28 local_irq_save_hw(flags); 28 flags = hard_local_irq_save();
29 bfin_pm_standby_setup(); 29 bfin_pm_standby_setup();
30 30
31#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER 31#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -56,7 +56,7 @@ void bfin_pm_suspend_standby_enter(void)
56 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 56 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
57#endif 57#endif
58 58
59 local_irq_restore_hw(flags); 59 hard_local_irq_restore(flags);
60} 60}
61 61
62int bf53x_suspend_l1_mem(unsigned char *memptr) 62int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -149,12 +149,12 @@ int bfin_pm_suspend_mem_enter(void)
149 wakeup |= GPWE; 149 wakeup |= GPWE;
150#endif 150#endif
151 151
152 local_irq_save_hw(flags); 152 flags = hard_local_irq_save();
153 153
154 ret = blackfin_dma_suspend(); 154 ret = blackfin_dma_suspend();
155 155
156 if (ret) { 156 if (ret) {
157 local_irq_restore_hw(flags); 157 hard_local_irq_restore(flags);
158 kfree(memptr); 158 kfree(memptr);
159 return ret; 159 return ret;
160 } 160 }
@@ -178,7 +178,7 @@ int bfin_pm_suspend_mem_enter(void)
178 bfin_gpio_pm_hibernate_restore(); 178 bfin_gpio_pm_hibernate_restore();
179 blackfin_dma_resume(); 179 blackfin_dma_resume();
180 180
181 local_irq_restore_hw(flags); 181 hard_local_irq_restore(flags);
182 kfree(memptr); 182 kfree(memptr);
183 183
184 return 0; 184 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 22:31:18 -0500