diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-11-18 04:48:22 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 04:48:22 -0500 |
commit | 9b78442fadc1d0319f77437c811fe53398822602 (patch) | |
tree | e38d6ecd18f1941fc2746bce3e45bd8e35c0ce00 /arch/blackfin | |
parent | a3765e0cd5fb76d7d62bc2d74be4627279d44005 (diff) |
Blackfin arch: rename cache_lock() to bfin_cache_lock()
rename cache_lock() to bfin_cache_lock() to avoid namespace collision
with common code
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r-- | arch/blackfin/include/asm/bfin-global.h | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-common/lock.S | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 1dd08058bc90..daffc0684e75 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
@@ -111,7 +111,7 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; | |||
111 | 111 | ||
112 | #ifdef CONFIG_BFIN_ICACHE_LOCK | 112 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
113 | extern void cache_grab_lock(int way); | 113 | extern void cache_grab_lock(int way); |
114 | extern void cache_lock(int way); | 114 | extern void bfin_cache_lock(int way); |
115 | #endif | 115 | #endif |
116 | 116 | ||
117 | #endif | 117 | #endif |
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 9daf01201e9f..6c5f5f0ea7fe 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S | |||
@@ -160,7 +160,7 @@ ENDPROC(_cache_grab_lock) | |||
160 | * R0 - Which way to be locked | 160 | * R0 - Which way to be locked |
161 | */ | 161 | */ |
162 | 162 | ||
163 | ENTRY(_cache_lock) | 163 | ENTRY(_bfin_cache_lock) |
164 | 164 | ||
165 | [--SP]=( R7:0,P5:0 ); | 165 | [--SP]=( R7:0,P5:0 ); |
166 | 166 | ||
@@ -184,7 +184,7 @@ ENTRY(_cache_lock) | |||
184 | 184 | ||
185 | ( R7:0,P5:0 ) = [SP++]; | 185 | ( R7:0,P5:0 ) = [SP++]; |
186 | RTS; | 186 | RTS; |
187 | ENDPROC(_cache_lock) | 187 | ENDPROC(_bfin_cache_lock) |
188 | 188 | ||
189 | /* Invalidate the Entire Instruction cache by | 189 | /* Invalidate the Entire Instruction cache by |
190 | * disabling IMC bit | 190 | * disabling IMC bit |