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authorMike Frysinger <vapier@gentoo.org>2011-06-26 14:07:17 -0400
committerMike Frysinger <vapier@gentoo.org>2011-07-23 01:18:27 -0400
commit4705a25c06c99081c1ec2f48561e37738e566ebd (patch)
treef96ac62119930059306f82345c26e5350e84f42f /arch/blackfin
parent01f8e34c9855e5aa4f56a73b8d5ea8f7613dbb7e (diff)
Blackfin: dpmc: optimize SIC_IWR programming a little
For parts with more than one SIC_IWR, we can optimize the writing a little bit using better Blackfin insns. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S15
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 6ecc64e5a06a..3fba05c99098 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -239,21 +239,18 @@ ENDPROC(_unset_dram_srfs)
239 239
240ENTRY(_set_sic_iwr) 240ENTRY(_set_sic_iwr)
241#ifdef SIC_IWR0 241#ifdef SIC_IWR0
242 P0.H = hi(SIC_IWR0); 242 P0.H = hi(SYSMMR_BASE);
243 P0.L = lo(SIC_IWR0); 243 P0.L = lo(SYSMMR_BASE);
244 P1.H = hi(SIC_IWR1); 244 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
245 P1.L = lo(SIC_IWR1); 245 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
246 [P1] = R1;
247# ifdef SIC_IWR2 246# ifdef SIC_IWR2
248 P1.H = hi(SIC_IWR2); 247 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
249 P1.L = lo(SIC_IWR2);
250 [P1] = R2;
251# endif 248# endif
252#else 249#else
253 P0.H = hi(SIC_IWR); 250 P0.H = hi(SIC_IWR);
254 P0.L = lo(SIC_IWR); 251 P0.L = lo(SIC_IWR);
255#endif
256 [P0] = R0; 252 [P0] = R0;
253#endif
257 254
258 SSYNC; 255 SSYNC;
259 RTS; 256 RTS;