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authorMichael Hennerich <michael.hennerich@analog.com>2010-08-02 04:51:07 -0400
committerMike Frysinger <vapier@gentoo.org>2010-08-06 12:55:57 -0400
commitf619ddd4fe5e6da3c3e97fe21043a4233aa54aee (patch)
tree066f624fb958d70e48a223140c1b569d215e4dc3 /arch/blackfin/mach-common
parent39750324053c2aa4314e460b5ce1767f4dfbeff1 (diff)
Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing
The RTC ISTAT bits do not affect wakeups, and the RTC driver already takes care of clearing this MMR when necessary. So drop the useless clearing in the core Blackfin power code. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S24
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index b03716896051..5969d86836a5 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -17,9 +17,6 @@ ENTRY(_sleep_mode)
17 17
18 call _set_sic_iwr; 18 call _set_sic_iwr;
19 19
20 R0 = 0xFFFF (Z);
21 call _set_rtc_istat;
22
23 P0.H = hi(PLL_CTL); 20 P0.H = hi(PLL_CTL);
24 P0.L = lo(PLL_CTL); 21 P0.L = lo(PLL_CTL);
25 R1 = W[P0](z); 22 R1 = W[P0](z);
@@ -65,9 +62,6 @@ ENTRY(_hibernate_mode)
65 call _set_dram_srfs; 62 call _set_dram_srfs;
66 SSYNC; 63 SSYNC;
67 64
68 R0 = 0xFFFF (Z);
69 call _set_rtc_istat;
70
71 P0.H = hi(VR_CTL); 65 P0.H = hi(VR_CTL);
72 P0.L = lo(VR_CTL); 66 P0.L = lo(VR_CTL);
73 67
@@ -95,9 +89,6 @@ ENTRY(_sleep_deeper)
95 call _set_sic_iwr; 89 call _set_sic_iwr;
96 call _set_dram_srfs; /* Set SDRAM Self Refresh */ 90 call _set_dram_srfs; /* Set SDRAM Self Refresh */
97 91
98 /* Clear all the interrupts,bits sticky */
99 R0 = 0xFFFF (Z);
100 call _set_rtc_istat;
101 P0.H = hi(PLL_DIV); 92 P0.H = hi(PLL_DIV);
102 P0.L = lo(PLL_DIV); 93 P0.L = lo(PLL_DIV);
103 R6 = W[P0](z); 94 R6 = W[P0](z);
@@ -269,21 +260,6 @@ ENTRY(_set_sic_iwr)
269 RTS; 260 RTS;
270ENDPROC(_set_sic_iwr) 261ENDPROC(_set_sic_iwr)
271 262
272ENTRY(_set_rtc_istat)
273#ifndef CONFIG_BF561
274 P0.H = hi(RTC_ISTAT);
275 P0.L = lo(RTC_ISTAT);
276 w[P0] = R0.L;
277 SSYNC;
278#elif (ANOMALY_05000371)
279 nop;
280 nop;
281 nop;
282 nop;
283#endif
284 RTS;
285ENDPROC(_set_rtc_istat)
286
287ENTRY(_test_pll_locked) 263ENTRY(_test_pll_locked)
288 P0.H = hi(PLL_STAT); 264 P0.H = hi(PLL_STAT);
289 P0.L = lo(PLL_STAT); 265 P0.L = lo(PLL_STAT);