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authorMike Frysinger <michael.frysinger@analog.com>2007-11-15 08:12:32 -0500
committerBryan Wu <bryan.wu@analog.com>2007-11-15 08:12:32 -0500
commita055b2b4de214d7c3c5382ba7e7c65d1476826b3 (patch)
tree430ce2d03fc665e01da2d1092290a1f3996bae77 /arch/blackfin/mach-common
parent0feea17f9401efe4a214db6f43e7208ae8331081 (diff)
Blackfin arch: remove useless CONFIG_IRQCHIP_DEMUX_GPIO
since we have this always turned on now and dont want it off (and hasnt been an option in a while) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c21
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c28
2 files changed, 18 insertions, 31 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index c2f05fabedc1..4882f0e801a9 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -181,7 +181,6 @@ static struct irq_chip bf561_internal_irqchip = {
181 .unmask = bf561_internal_unmask_irq, 181 .unmask = bf561_internal_unmask_irq,
182}; 182};
183 183
184#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
185static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 184static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
186static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; 185static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
187 186
@@ -362,8 +361,6 @@ static void bf561_demux_gpio_irq(unsigned int inta_irq,
362 361
363} 362}
364 363
365#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
366
367void __init init_exception_vectors(void) 364void __init init_exception_vectors(void)
368{ 365{
369 SSYNC(); 366 SSYNC();
@@ -413,26 +410,21 @@ int __init init_arch_irq(void)
413 set_irq_chip(irq, &bf561_core_irqchip); 410 set_irq_chip(irq, &bf561_core_irqchip);
414 else 411 else
415 set_irq_chip(irq, &bf561_internal_irqchip); 412 set_irq_chip(irq, &bf561_internal_irqchip);
416#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 413
417 if ((irq != IRQ_PROG0_INTA) && 414 if ((irq != IRQ_PROG0_INTA) &&
418 (irq != IRQ_PROG1_INTA) && (irq != IRQ_PROG2_INTA)) { 415 (irq != IRQ_PROG1_INTA) &&
419#endif 416 (irq != IRQ_PROG2_INTA))
420 set_irq_handler(irq, handle_simple_irq); 417 set_irq_handler(irq, handle_simple_irq);
421#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 418 else
422 } else {
423 set_irq_chained_handler(irq, bf561_demux_gpio_irq); 419 set_irq_chained_handler(irq, bf561_demux_gpio_irq);
424 }
425#endif
426
427 } 420 }
428 421
429#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
430 for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) { 422 for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
431 set_irq_chip(irq, &bf561_gpio_irqchip); 423 set_irq_chip(irq, &bf561_gpio_irqchip);
432 /* if configured as edge, then will be changed to do_edge_IRQ */ 424 /* if configured as edge, then will be changed to do_edge_IRQ */
433 set_irq_handler(irq, handle_level_irq); 425 set_irq_handler(irq, handle_level_irq);
434 } 426 }
435#endif 427
436 bfin_write_IMASK(0); 428 bfin_write_IMASK(0);
437 CSYNC(); 429 CSYNC();
438 ilat = bfin_read_ILAT(); 430 ilat = bfin_read_ILAT();
@@ -457,9 +449,8 @@ int __init init_arch_irq(void)
457} 449}
458 450
459#ifdef CONFIG_DO_IRQ_L1 451#ifdef CONFIG_DO_IRQ_L1
460void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); 452__attribute__((l1_text))
461#endif 453#endif
462
463void do_irq(int vec, struct pt_regs *fp) 454void do_irq(int vec, struct pt_regs *fp)
464{ 455{
465 if (vec == EVT_IVTMR_P) { 456 if (vec == EVT_IVTMR_P) {
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 2d2b63567b30..147f0731087a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -308,7 +308,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
308} 308}
309#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ 309#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
310 310
311#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) 311#if !defined(CONFIG_BF54x)
312 312
313static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 313static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
314static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; 314static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -464,7 +464,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
464 } 464 }
465} 465}
466 466
467#else /* CONFIG_IRQCHIP_DEMUX_GPIO */ 467#else /* CONFIG_BF54x */
468 468
469#define NR_PINT_SYS_IRQS 4 469#define NR_PINT_SYS_IRQS 4
470#define NR_PINT_BITS 32 470#define NR_PINT_BITS 32
@@ -726,7 +726,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
726 } 726 }
727 727
728} 728}
729#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ 729#endif
730 730
731void __init init_exception_vectors(void) 731void __init init_exception_vectors(void)
732{ 732{
@@ -766,10 +766,10 @@ int __init init_arch_irq(void)
766 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 766 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
767 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 767 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
768 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 768 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
769#ifdef CONFIG_BF54x 769# ifdef CONFIG_BF54x
770 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 770 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
771 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 771 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
772#endif 772# endif
773#else 773#else
774 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 774 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
775 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 775 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@@ -778,13 +778,13 @@ int __init init_arch_irq(void)
778 778
779 local_irq_disable(); 779 local_irq_disable();
780 780
781#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) 781#ifdef CONFIG_BF54x
782#ifdef CONFIG_PINTx_REASSIGN 782# ifdef CONFIG_PINTx_REASSIGN
783 pint[0]->assign = CONFIG_PINT0_ASSIGN; 783 pint[0]->assign = CONFIG_PINT0_ASSIGN;
784 pint[1]->assign = CONFIG_PINT1_ASSIGN; 784 pint[1]->assign = CONFIG_PINT1_ASSIGN;
785 pint[2]->assign = CONFIG_PINT2_ASSIGN; 785 pint[2]->assign = CONFIG_PINT2_ASSIGN;
786 pint[3]->assign = CONFIG_PINT3_ASSIGN; 786 pint[3]->assign = CONFIG_PINT3_ASSIGN;
787#endif 787# endif
788 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ 788 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
789 init_pint_lut(); 789 init_pint_lut();
790#endif 790#endif
@@ -799,18 +799,17 @@ int __init init_arch_irq(void)
799#endif 799#endif
800 800
801 switch (irq) { 801 switch (irq) {
802#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
803#if defined(CONFIG_BF53x) 802#if defined(CONFIG_BF53x)
804 case IRQ_PROG_INTA: 803 case IRQ_PROG_INTA:
805 set_irq_chained_handler(irq, 804 set_irq_chained_handler(irq,
806 bfin_demux_gpio_irq); 805 bfin_demux_gpio_irq);
807 break; 806 break;
808#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 807# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
809 case IRQ_MAC_RX: 808 case IRQ_MAC_RX:
810 set_irq_chained_handler(irq, 809 set_irq_chained_handler(irq,
811 bfin_demux_gpio_irq); 810 bfin_demux_gpio_irq);
812 break; 811 break;
813#endif 812# endif
814#elif defined(CONFIG_BF54x) 813#elif defined(CONFIG_BF54x)
815 case IRQ_PINT0: 814 case IRQ_PINT0:
816 set_irq_chained_handler(irq, 815 set_irq_chained_handler(irq,
@@ -842,7 +841,6 @@ int __init init_arch_irq(void)
842 bfin_demux_gpio_irq); 841 bfin_demux_gpio_irq);
843 break; 842 break;
844#endif 843#endif
845#endif
846 default: 844 default:
847 set_irq_handler(irq, handle_simple_irq); 845 set_irq_handler(irq, handle_simple_irq);
848 break; 846 break;
@@ -861,7 +859,6 @@ int __init init_arch_irq(void)
861 } 859 }
862#endif 860#endif
863 861
864#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
865#ifndef CONFIG_BF54x 862#ifndef CONFIG_BF54x
866 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { 863 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
867#else 864#else
@@ -871,7 +868,7 @@ int __init init_arch_irq(void)
871 /* if configured as edge, then will be changed to do_edge_IRQ */ 868 /* if configured as edge, then will be changed to do_edge_IRQ */
872 set_irq_handler(irq, handle_level_irq); 869 set_irq_handler(irq, handle_level_irq);
873 } 870 }
874#endif 871
875 bfin_write_IMASK(0); 872 bfin_write_IMASK(0);
876 CSYNC(); 873 CSYNC();
877 ilat = bfin_read_ILAT(); 874 ilat = bfin_read_ILAT();
@@ -896,9 +893,8 @@ int __init init_arch_irq(void)
896} 893}
897 894
898#ifdef CONFIG_DO_IRQ_L1 895#ifdef CONFIG_DO_IRQ_L1
899void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); 896__attribute__((l1_text))
900#endif 897#endif
901
902void do_irq(int vec, struct pt_regs *fp) 898void do_irq(int vec, struct pt_regs *fp)
903{ 899{
904 if (vec == EVT_IVTMR_P) { 900 if (vec == EVT_IVTMR_P) {