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authorGraf Yang <graf.yang@analog.com>2009-05-15 07:01:59 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:11:37 -0400
commit1fa9be72b558c39459f98835eb86dbb4ef4da30b (patch)
treef0b71c7b7a3639285c64e3f3cbc449c3ff9eee3b /arch/blackfin/mach-common
parent555487bbb63f527e63fecbff48c86e2c07ce5024 (diff)
Blackfin: add support for gptimer0 as a tick source
For systems where the core cycles are not a usable tick source (like SMP or cycles gets updated), enable gptimer0 as an alternative. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/ints-priority.c23
-rw-r--r--arch/blackfin/mach-common/smp.c5
2 files changed, 9 insertions, 19 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 389c5e8aa456..6e808612d170 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1052,7 +1052,7 @@ int __init init_arch_irq(void)
1052 set_irq_chained_handler(irq, bfin_demux_error_irq); 1052 set_irq_chained_handler(irq, bfin_demux_error_irq);
1053 break; 1053 break;
1054#endif 1054#endif
1055#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 1055#if defined(CONFIG_TICKSOURCE_GPTMR0)
1056 case IRQ_TIMER0: 1056 case IRQ_TIMER0:
1057 set_irq_handler(irq, handle_percpu_irq); 1057 set_irq_handler(irq, handle_percpu_irq);
1058 break; 1058 break;
@@ -1232,13 +1232,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1232 1232
1233 if (likely(vec == EVT_IVTMR_P)) { 1233 if (likely(vec == EVT_IVTMR_P)) {
1234 irq = IRQ_CORETMR; 1234 irq = IRQ_CORETMR;
1235 goto core_tick;
1236 }
1237
1238 SSYNC();
1239 1235
1236 } else {
1240#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1237#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1241 {
1242 unsigned long sic_status[3]; 1238 unsigned long sic_status[3];
1243 1239
1244 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1240 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
@@ -1254,9 +1250,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1254 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) 1250 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1255 break; 1251 break;
1256 } 1252 }
1257 }
1258#else 1253#else
1259 {
1260 unsigned long sic_status; 1254 unsigned long sic_status;
1261 1255
1262 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 1256 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
@@ -1268,15 +1262,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1268 } else if (sic_status & ivg->isrflag) 1262 } else if (sic_status & ivg->isrflag)
1269 break; 1263 break;
1270 } 1264 }
1271 }
1272#endif 1265#endif
1273 1266
1274 irq = ivg->irqno; 1267 irq = ivg->irqno;
1268 }
1275 1269
1276 if (irq == IRQ_SYSTMR) { 1270 if (irq == IRQ_SYSTMR) {
1277#ifdef CONFIG_GENERIC_CLOCKEVENTS 1271#ifndef CONFIG_GENERIC_CLOCKEVENTS
1278core_tick:
1279#else
1280 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1272 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1281#endif 1273#endif
1282 /* This is basically what we need from the register frame. */ 1274 /* This is basically what we need from the register frame. */
@@ -1288,9 +1280,6 @@ core_tick:
1288 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; 1280 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1289 } 1281 }
1290 1282
1291#ifndef CONFIG_GENERIC_CLOCKEVENTS
1292core_tick:
1293#endif
1294 if (this_domain == ipipe_root_domain) { 1283 if (this_domain == ipipe_root_domain) {
1295 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); 1284 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1296 barrier(); 1285 barrier();
@@ -1308,7 +1297,7 @@ core_tick:
1308 } 1297 }
1309 } 1298 }
1310 1299
1311 return 0; 1300 return 0;
1312} 1301}
1313 1302
1314#endif /* CONFIG_IPIPE */ 1303#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 187c79e585a1..b6695957b065 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -43,6 +43,7 @@
43#include <asm/processor.h> 43#include <asm/processor.h>
44#include <asm/ptrace.h> 44#include <asm/ptrace.h>
45#include <asm/cpu.h> 45#include <asm/cpu.h>
46#include <asm/time.h>
46#include <linux/err.h> 47#include <linux/err.h>
47 48
48/* 49/*
@@ -356,7 +357,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
356 357
357static void __cpuinit setup_secondary(unsigned int cpu) 358static void __cpuinit setup_secondary(unsigned int cpu)
358{ 359{
359#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)) 360#if !defined(CONFIG_TICKSOURCE_GPTMR0)
360 struct irq_desc *timer_desc; 361 struct irq_desc *timer_desc;
361#endif 362#endif
362 unsigned long ilat; 363 unsigned long ilat;
@@ -377,7 +378,7 @@ static void __cpuinit setup_secondary(unsigned int cpu)
377 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 378 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
378 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 379 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
379 380
380#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) 381#if defined(CONFIG_TICKSOURCE_GPTMR0)
381 /* Power down the core timer, just to play safe. */ 382 /* Power down the core timer, just to play safe. */
382 bfin_write_TCNTL(0); 383 bfin_write_TCNTL(0);
383 384