blackfin architecture

This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix!  Tinyboards.

The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000.  Since then ADI has put this core into its Blackfin
processor family of devices.  The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.

The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf

The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc

This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/

We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel

[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 418 insertions, 0 deletions

diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
new file mode 100644
index 000000000000..97cdcd6a00d4
--- /dev/null
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -0,0 +1,418 @@
+/*
+ * File:         arch/blackfin/mach-common/dpmc.S
+ * Based on:
+ * Author:       LG Soft India
+ *
+ * Created:      ?
+ * Description:  Watchdog Timer APIs
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/mach/irq.h>
+
+.text
+
+ENTRY(_unmask_wdog_wakeup_evt)
+        [--SP] = ( R7:0, P5:0 );
+#if defined(CONFIG_BF561)
+        P0.H = hi(SICA_IWR1);
+        P0.L = lo(SICA_IWR1);
+#else
+        P0.h = (SIC_IWR >> 16);
+        P0.l = (SIC_IWR & 0xFFFF);
+#endif
+        R7 = [P0];
+#if defined(CONFIG_BF561)
+        BITSET(R7, 27);
+#else
+        BITSET(R7,(IRQ_WATCH - IVG7));
+#endif
+        [P0] = R7;
+        SSYNC;
+
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+.LWRITE_TO_STAT:
+        /* When watch dog timer is enabled, a write to STAT will load the
+         * contents of CNT to STAT
+         */
+        R7 = 0x0000(z);
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_STAT >> 16);
+        P0.l = (WDOGA_STAT & 0xFFFF);
+#else
+        P0.h = (WDOG_STAT >> 16);
+        P0.l = (WDOG_STAT & 0xFFFF);
+#endif
+        [P0] = R7;
+        SSYNC;
+        JUMP .LSKIP_WRITE_TO_STAT;
+
+ENTRY(_program_wdog_timer)
+        [--SP] = ( R7:0, P5:0 );
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_CNT >> 16);
+        P0.l = (WDOGA_CNT & 0xFFFF);
+#else
+        P0.h = (WDOG_CNT >> 16);
+        P0.l = (WDOG_CNT & 0xFFFF);
+#endif
+        [P0] = R0;
+        SSYNC;
+
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_CTL >> 16);
+        P0.l = (WDOGA_CTL & 0xFFFF);
+#else
+        P0.h = (WDOG_CTL >> 16);
+        P0.l = (WDOG_CTL & 0xFFFF);
+#endif
+        R7 = W[P0](Z);
+        CC = BITTST(R7,1);
+        if !CC JUMP .LWRITE_TO_STAT;
+        CC = BITTST(R7,2);
+        if !CC JUMP .LWRITE_TO_STAT;
+
+.LSKIP_WRITE_TO_STAT:
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_CTL >> 16);
+            P0.l = (WDOGA_CTL & 0xFFFF);
+#else
+        P0.h = (WDOG_CTL >> 16);
+            P0.l = (WDOG_CTL & 0xFFFF);
+#endif
+        R7 = W[P0](Z);
+        BITCLR(R7,1);   /* Enable GP event */
+        BITSET(R7,2);
+        W[P0] = R7.L;
+        SSYNC;
+        NOP;
+
+        R7 = W[P0](Z);
+        BITCLR(R7,4);   /* Enable the wdog counter */
+        W[P0] = R7.L;
+        SSYNC;
+
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+ENTRY(_clear_wdog_wakeup_evt)
+        [--SP] = ( R7:0, P5:0 );
+
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_CTL >> 16);
+        P0.l = (WDOGA_CTL & 0xFFFF);
+#else
+        P0.h = (WDOG_CTL >> 16);
+        P0.l = (WDOG_CTL & 0xFFFF);
+#endif
+        R7 = 0x0AD6(Z);
+        W[P0] = R7.L;
+        SSYNC;
+
+        R7 = W[P0](Z);
+        BITSET(R7,15);
+        W[P0] = R7.L;
+        SSYNC;
+
+        R7 = W[P0](Z);
+        BITSET(R7,1);
+        BITSET(R7,2);
+        W[P0] = R7.L;
+        SSYNC;
+
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+ENTRY(_disable_wdog_timer)
+        [--SP] = ( R7:0, P5:0 );
+#if defined(CONFIG_BF561)
+        P0.h = (WDOGA_CTL >> 16);
+        P0.l = (WDOGA_CTL & 0xFFFF);
+#else
+        P0.h = (WDOG_CTL >> 16);
+        P0.l = (WDOG_CTL & 0xFFFF);
+#endif
+        R7 = 0xAD6(Z);
+        W[P0] = R7.L;
+        SSYNC;
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+#if !defined(CONFIG_BF561)
+
+.section .l1.text
+
+ENTRY(_sleep_mode)
+        [--SP] = ( R7:0, P5:0 );
+        [--SP] =  RETS;
+
+        call _set_sic_iwr;
+
+        R0 = 0xFFFF (Z);
+        call _set_rtc_istat
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R1 = W[P0](z);
+        BITSET (R1, 3);
+        W[P0] = R1.L;
+
+        CLI R2;
+        SSYNC;
+        IDLE;
+        STI R2;
+
+        call _test_pll_locked;
+
+        R0 = IWR_ENABLE(0);
+        call _set_sic_iwr;
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R7 = w[p0](z);
+        BITCLR (R7, 3);
+        BITCLR (R7, 5);
+        w[p0] = R7.L;
+        IDLE;
+        call _test_pll_locked;
+
+        RETS = [SP++];
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+ENTRY(_hibernate_mode)
+        [--SP] = ( R7:0, P5:0 );
+        [--SP] =  RETS;
+
+        call _set_sic_iwr;
+
+        R0 = 0xFFFF (Z);
+        call _set_rtc_istat
+
+        P0.H = hi(VR_CTL);
+        P0.L = lo(VR_CTL);
+        R1 = W[P0](z);
+        BITSET (R1, 8);
+        BITCLR (R1, 0);
+        BITCLR (R1, 1);
+        W[P0] = R1.L;
+        SSYNC;
+
+        CLI R2;
+        IDLE;
+
+        /* Actually, adding anything may not be necessary...SDRAM contents
+         * are lost
+         */
+
+ENTRY(_deep_sleep)
+        [--SP] = ( R7:0, P5:0 );
+        [--SP] =  RETS;
+
+        CLI R4;
+
+        call _set_sic_iwr;
+
+        call _set_sdram_srfs;
+
+        /* Clear all the interrupts,bits sticky */
+        R0 = 0xFFFF (Z);
+        call _set_rtc_istat
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R0 = W[P0](z);
+        BITSET (R0, 5);
+        W[P0] = R0.L;
+
+        call _test_pll_locked;
+
+        SSYNC;
+        IDLE;
+
+        call _unset_sdram_srfs;
+
+        call _test_pll_locked;
+
+        R0 = IWR_ENABLE(0);
+        call _set_sic_iwr;
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R0 = w[p0](z);
+        BITCLR (R0, 3);
+        BITCLR (R0, 5);
+        BITCLR (R0, 8);
+        w[p0] = R0;
+        IDLE;
+        call _test_pll_locked;
+
+        STI R4;
+
+        RETS = [SP++];
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+ENTRY(_sleep_deeper)
+        [--SP] = ( R7:0, P5:0 );
+        [--SP] =  RETS;
+
+        CLI R4;
+
+        P3 = R0;
+        R0 = IWR_ENABLE(0);
+        call _set_sic_iwr;
+        call _set_sdram_srfs;
+
+        /* Clear all the interrupts,bits sticky */
+        R0 = 0xFFFF (Z);
+        call _set_rtc_istat
+
+        P0.H = hi(PLL_DIV);
+        P0.L = lo(PLL_DIV);
+        R6 = W[P0](z);
+        R0.L = 0xF;
+        W[P0] = R0.l;
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R5 = W[P0](z);
+        R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
+        W[P0] = R0.l;
+
+        SSYNC;
+        IDLE;
+
+        call _test_pll_locked;
+
+        P0.H = hi(VR_CTL);
+        P0.L = lo(VR_CTL);
+        R7 = W[P0](z);
+        R1 = 0x6;
+        R1 <<= 16;
+        R2 = 0x0404(Z);
+        R1 = R1|R2;
+
+        R2 = DEPOSIT(R7, R1);
+        W[P0] = R2;
+
+        SSYNC;
+        IDLE;
+
+        call _test_pll_locked;
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        R0 = W[P0](z);
+        BITSET (R0, 3);
+        W[P0] = R0.L;
+
+        R0 = P3;
+        call _set_sic_iwr;
+
+        SSYNC;
+        IDLE;
+
+        call _test_pll_locked;
+
+        R0 = IWR_ENABLE(0);
+        call _set_sic_iwr;
+
+        P0.H = hi(VR_CTL);
+        P0.L = lo(VR_CTL);
+        W[P0]= R7;
+
+        SSYNC;
+        IDLE;
+
+        call _test_pll_locked;
+
+        P0.H = hi(PLL_DIV);
+        P0.L = lo(PLL_DIV);
+        W[P0]= R6;
+
+        P0.H = hi(PLL_CTL);
+        P0.L = lo(PLL_CTL);
+        w[p0] = R5;
+        IDLE;
+        call _test_pll_locked;
+
+        call _unset_sdram_srfs;
+
+        STI R4;
+
+        RETS = [SP++];
+        ( R7:0, P5:0 ) = [SP++];
+        RTS;
+
+ENTRY(_set_sdram_srfs)
+        /*  set the sdram to self refresh mode */
+        P0.H = hi(EBIU_SDGCTL);
+        P0.L = lo(EBIU_SDGCTL);
+        R2 = [P0];
+        R3.H = hi(SRFS);
+        R3.L = lo(SRFS);
+        R2 = R2|R3;
+        [P0] = R2;
+        ssync;
+        RTS;
+
+ENTRY(_unset_sdram_srfs)
+        /*  set the sdram out of self refresh mode */
+        P0.H = hi(EBIU_SDGCTL);
+        P0.L = lo(EBIU_SDGCTL);
+        R2 = [P0];
+        R3.H = hi(SRFS);
+        R3.L = lo(SRFS);
+        R3 = ~R3;
+        R2 = R2&R3;
+        [P0] = R2;
+        ssync;
+        RTS;
+
+ENTRY(_set_sic_iwr)
+        P0.H = hi(SIC_IWR);
+        P0.L = lo(SIC_IWR);
+        [P0] = R0;
+        SSYNC;
+        RTS;
+
+ENTRY(_set_rtc_istat)
+        P0.H = hi(RTC_ISTAT);
+        P0.L = lo(RTC_ISTAT);
+        w[P0] = R0.L;
+        SSYNC;
+        RTS;
+
+ENTRY(_test_pll_locked)
+        P0.H = hi(PLL_STAT);
+        P0.L = lo(PLL_STAT);
+1:
+        R0 = W[P0] (Z);
+        CC = BITTST(R0,5);
+        IF !CC JUMP 1b;
+        RTS;
+#endif