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authorSonic Zhang <sonic.zhang@analog.com>2010-08-05 03:49:26 -0400
committerMike Frysinger <vapier@gentoo.org>2011-03-18 04:01:04 -0400
commitc6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa (patch)
tree8f3980f69cba2e3269aa9688426fca95be56d7a6 /arch/blackfin/mach-common/cache.S
parent6f546bc3ac9eedbf770bf3bcbc45ce2ea32c94ad (diff)
Blackfin: SMP: work around anomaly 05000491
In order to safely work around anomaly 05000491, we have to execute IFLUSH from L1 instruction sram. The trouble with multi-core systems is that all L1 sram is visible only to the active core. So we can't just place the functions into L1 and call it directly. We need to setup a jump table and place the entry point in external memory. This will call the right func based on the active core. In the process, convert from the manual relocation of a small bit of code into Core B's L1 to the more general framework we already have in place for loading arbitrary pieces of code into L1. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r--arch/blackfin/mach-common/cache.S20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 85aadeb76658..9f4dd35bfd74 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -69,10 +69,30 @@
69#endif 69#endif
70 70
71/* Invalidate all instruction cache lines assocoiated with this memory area */ 71/* Invalidate all instruction cache lines assocoiated with this memory area */
72#ifdef CONFIG_SMP
73# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
74#endif
72ENTRY(_blackfin_icache_flush_range) 75ENTRY(_blackfin_icache_flush_range)
73 do_flush IFLUSH 76 do_flush IFLUSH
74ENDPROC(_blackfin_icache_flush_range) 77ENDPROC(_blackfin_icache_flush_range)
75 78
79#ifdef CONFIG_SMP
80.text
81# undef _blackfin_icache_flush_range
82ENTRY(_blackfin_icache_flush_range)
83 p0.L = LO(DSPID);
84 p0.H = HI(DSPID);
85 r3 = [p0];
86 r3 = r3.b (z);
87 p2 = r3;
88 p0.L = _blackfin_iflush_l1_entry;
89 p0.H = _blackfin_iflush_l1_entry;
90 p0 = p0 + (p2 << 2);
91 p1 = [p0];
92 jump (p1);
93ENDPROC(_blackfin_icache_flush_range)
94#endif
95
76#ifdef CONFIG_DCACHE_FLUSH_L1 96#ifdef CONFIG_DCACHE_FLUSH_L1
77.section .l1.text 97.section .l1.text
78#else 98#else