Blackfin: SMP: implement cpu_freq support

Re-use some of the existing cpu hotplugging code in the process.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2 files changed, 18 insertions, 29 deletions

diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index 4cd3b28cd046..42fc085629c7 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -5,30 +5,27 @@
  * Licensed under the GPL-2 or later.
  */
 
+#include <linux/smp.h>
 #include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/smp.h>
-
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
+#include <mach/pll.h>
 
 int hotplug_coreb;
 
 void platform_cpu_die(void)
 {
-        unsigned long iwr[2] = {0, 0};
-        unsigned long bank = SIC_SYSIRQ(IRQ_SUPPLE_0) / 32;
-        unsigned long bit = 1 << (SIC_SYSIRQ(IRQ_SUPPLE_0) % 32);
-
+        unsigned long iwr;
         hotplug_coreb = 1;
 
-        iwr[bank] = bit;
-
         /* disable core timer */
         bfin_write_TCNTL(0);
 
-        /* clear ipi interrupt IRQ_SUPPLE_0 */
+        /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
         SSYNC();
 
-        coreb_sleep(iwr[0], iwr[1], 0);
+        /* set CoreB wakeup by ipi0, iwr will be discarded */
+        bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
+        SSYNC();
+
+        coreb_die();
 }
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index ef9acf21eb8e..148e50764555 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -162,39 +162,31 @@ ENTRY(_coreb_trampoline_start)
 ENDPROC(_coreb_trampoline_start)
 ENTRY(_coreb_trampoline_end)
 
+#ifdef CONFIG_HOTPLUG_CPU
 .section ".text"
-ENTRY(_set_sicb_iwr)
-        P0.H = hi(SICB_IWR0);
-        P0.L = lo(SICB_IWR0);
-        P1.H = hi(SICB_IWR1);
-        P1.L = lo(SICB_IWR1);
-        [P0] = R0;
-        [P1] = R1;
-        SSYNC;
-        RTS;
-ENDPROC(_set_sicb_iwr)
-
-ENTRY(_coreb_sleep)
+ENTRY(_coreb_die)
         sp.l = lo(INITIAL_STACK);
         sp.h = hi(INITIAL_STACK);
         fp = sp;
         usp = sp;
 
-        call _set_sicb_iwr;
-
         CLI R2;
         SSYNC;
         IDLE;
         STI R2;
 
         R0 = IWR_DISABLE_ALL;
-        R1 = IWR_DISABLE_ALL;
-        call _set_sicb_iwr;
+        P0.H = hi(SYSMMR_BASE);
+        P0.L = lo(SYSMMR_BASE);
+        [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
+        [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
+        SSYNC;
 
         p0.h = hi(COREB_L1_CODE_START);
         p0.l = lo(COREB_L1_CODE_START);
         jump (p0);
-ENDPROC(_coreb_sleep)
+ENDPROC(_coreb_die)
+#endif
 
 __INIT
 ENTRY(_coreb_start)