diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-30 02:54:33 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 08:13:42 -0400 |
| commit | 6adc521e7127732512ebd7fcfd3926d7970a82e1 (patch) | |
| tree | 1de12c99fde995c82a8cd7487f45c6f6ea0b4ef4 /arch/blackfin/mach-bf561 | |
| parent | 6b108049d67090988fbb0b9d9905ffca114b6ff1 (diff) | |
Blackfin: unify core IRQ definitions
Start a new common IRQ header and move all of the CEC pieces there. This
lets the individual part headers worry just about its SIC defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/irq.h | 117 |
1 files changed, 1 insertions, 116 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h index c95566ade51b..aa8f5953a1ac 100644 --- a/arch/blackfin/mach-bf561/include/mach/irq.h +++ b/arch/blackfin/mach-bf561/include/mach/irq.h | |||
| @@ -7,115 +7,11 @@ | |||
| 7 | #ifndef _BF561_IRQ_H_ | 7 | #ifndef _BF561_IRQ_H_ |
| 8 | #define _BF561_IRQ_H_ | 8 | #define _BF561_IRQ_H_ |
| 9 | 9 | ||
| 10 | /*********************************************************************** | 10 | #include <mach-common/irq.h> |
| 11 | * Interrupt source definitions: | ||
| 12 | Event Source Core Event Name IRQ No | ||
| 13 | (highest priority) | ||
| 14 | Emulation Events EMU 0 | ||
| 15 | Reset RST 1 | ||
| 16 | NMI NMI 2 | ||
| 17 | Exception EVX 3 | ||
| 18 | Reserved -- 4 | ||
| 19 | Hardware Error IVHW 5 | ||
| 20 | Core Timer IVTMR 6 * | ||
| 21 | |||
| 22 | PLL Wakeup Interrupt IVG7 7 | ||
| 23 | DMA1 Error (generic) IVG7 8 | ||
| 24 | DMA2 Error (generic) IVG7 9 | ||
| 25 | IMDMA Error (generic) IVG7 10 | ||
| 26 | PPI1 Error Interrupt IVG7 11 | ||
| 27 | PPI2 Error Interrupt IVG7 12 | ||
| 28 | SPORT0 Error Interrupt IVG7 13 | ||
| 29 | SPORT1 Error Interrupt IVG7 14 | ||
| 30 | SPI Error Interrupt IVG7 15 | ||
| 31 | UART Error Interrupt IVG7 16 | ||
| 32 | Reserved Interrupt IVG7 17 | ||
| 33 | |||
| 34 | DMA1 0 Interrupt(PPI1) IVG8 18 | ||
| 35 | DMA1 1 Interrupt(PPI2) IVG8 19 | ||
| 36 | DMA1 2 Interrupt IVG8 20 | ||
| 37 | DMA1 3 Interrupt IVG8 21 | ||
| 38 | DMA1 4 Interrupt IVG8 22 | ||
| 39 | DMA1 5 Interrupt IVG8 23 | ||
| 40 | DMA1 6 Interrupt IVG8 24 | ||
| 41 | DMA1 7 Interrupt IVG8 25 | ||
| 42 | DMA1 8 Interrupt IVG8 26 | ||
| 43 | DMA1 9 Interrupt IVG8 27 | ||
| 44 | DMA1 10 Interrupt IVG8 28 | ||
| 45 | DMA1 11 Interrupt IVG8 29 | ||
| 46 | |||
| 47 | DMA2 0 (SPORT0 RX) IVG9 30 | ||
| 48 | DMA2 1 (SPORT0 TX) IVG9 31 | ||
| 49 | DMA2 2 (SPORT1 RX) IVG9 32 | ||
| 50 | DMA2 3 (SPORT2 TX) IVG9 33 | ||
| 51 | DMA2 4 (SPI) IVG9 34 | ||
| 52 | DMA2 5 (UART RX) IVG9 35 | ||
| 53 | DMA2 6 (UART TX) IVG9 36 | ||
| 54 | DMA2 7 Interrupt IVG9 37 | ||
| 55 | DMA2 8 Interrupt IVG9 38 | ||
| 56 | DMA2 9 Interrupt IVG9 39 | ||
| 57 | DMA2 10 Interrupt IVG9 40 | ||
| 58 | DMA2 11 Interrupt IVG9 41 | ||
| 59 | |||
| 60 | TIMER 0 Interrupt IVG10 42 | ||
| 61 | TIMER 1 Interrupt IVG10 43 | ||
| 62 | TIMER 2 Interrupt IVG10 44 | ||
| 63 | TIMER 3 Interrupt IVG10 45 | ||
| 64 | TIMER 4 Interrupt IVG10 46 | ||
| 65 | TIMER 5 Interrupt IVG10 47 | ||
| 66 | TIMER 6 Interrupt IVG10 48 | ||
| 67 | TIMER 7 Interrupt IVG10 49 | ||
| 68 | TIMER 8 Interrupt IVG10 50 | ||
| 69 | TIMER 9 Interrupt IVG10 51 | ||
| 70 | TIMER 10 Interrupt IVG10 52 | ||
| 71 | TIMER 11 Interrupt IVG10 53 | ||
| 72 | |||
| 73 | Programmable Flags0 A (8) IVG11 54 | ||
| 74 | Programmable Flags0 B (8) IVG11 55 | ||
| 75 | Programmable Flags1 A (8) IVG11 56 | ||
| 76 | Programmable Flags1 B (8) IVG11 57 | ||
| 77 | Programmable Flags2 A (8) IVG11 58 | ||
| 78 | Programmable Flags2 B (8) IVG11 59 | ||
| 79 | |||
| 80 | MDMA1 0 write/read INT IVG8 60 | ||
| 81 | MDMA1 1 write/read INT IVG8 61 | ||
| 82 | |||
| 83 | MDMA2 0 write/read INT IVG9 62 | ||
| 84 | MDMA2 1 write/read INT IVG9 63 | ||
| 85 | |||
| 86 | IMDMA 0 write/read INT IVG12 64 | ||
| 87 | IMDMA 1 write/read INT IVG12 65 | ||
| 88 | |||
| 89 | Watch Dog Timer IVG13 66 | ||
| 90 | |||
| 91 | Reserved interrupt IVG7 67 | ||
| 92 | Reserved interrupt IVG7 68 | ||
| 93 | Supplemental interrupt 0 IVG7 69 | ||
| 94 | supplemental interrupt 1 IVG7 70 | ||
| 95 | |||
| 96 | Softirq IVG14 | ||
| 97 | System Call -- | ||
| 98 | (lowest priority) IVG15 | ||
| 99 | |||
| 100 | **********************************************************************/ | ||
| 101 | 11 | ||
| 102 | #define SYS_IRQS 71 | 12 | #define SYS_IRQS 71 |
| 103 | #define NR_PERI_INTS 64 | 13 | #define NR_PERI_INTS 64 |
| 104 | 14 | ||
| 105 | /* | ||
| 106 | * The ABSTRACT IRQ definitions | ||
| 107 | * the first seven of the following are fixed, | ||
| 108 | * the rest you change if you need to. | ||
| 109 | */ | ||
| 110 | /* IVG 0-6*/ | ||
| 111 | #define IRQ_EMU 0 /* Emulation */ | ||
| 112 | #define IRQ_RST 1 /* Reset */ | ||
| 113 | #define IRQ_NMI 2 /* Non Maskable Interrupt */ | ||
| 114 | #define IRQ_EVX 3 /* Exception */ | ||
| 115 | #define IRQ_UNUSED 4 /* Reserved interrupt */ | ||
| 116 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
| 117 | #define IRQ_CORETMR 6 /* Core timer */ | ||
| 118 | |||
| 119 | #define IVG_BASE 7 | 15 | #define IVG_BASE 7 |
| 120 | /* IVG 7 */ | 16 | /* IVG 7 */ |
| 121 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ | 17 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ |
| @@ -266,17 +162,6 @@ | |||
| 266 | #define GPIO_IRQ_BASE IRQ_PF0 | 162 | #define GPIO_IRQ_BASE IRQ_PF0 |
| 267 | 163 | ||
| 268 | #define NR_MACH_IRQS (IRQ_PF47 + 1) | 164 | #define NR_MACH_IRQS (IRQ_PF47 + 1) |
| 269 | #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) | ||
| 270 | |||
| 271 | #define IVG7 7 | ||
| 272 | #define IVG8 8 | ||
| 273 | #define IVG9 9 | ||
| 274 | #define IVG10 10 | ||
| 275 | #define IVG11 11 | ||
| 276 | #define IVG12 12 | ||
| 277 | #define IVG13 13 | ||
| 278 | #define IVG14 14 | ||
| 279 | #define IVG15 15 | ||
| 280 | 165 | ||
| 281 | /* | 166 | /* |
| 282 | * DEFAULT PRIORITIES: | 167 | * DEFAULT PRIORITIES: |