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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /arch/blackfin/mach-bf561
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/Kconfig222
-rw-r--r--arch/blackfin/mach-bf561/Makefile9
-rw-r--r--arch/blackfin/mach-bf561/boards/Makefile7
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c289
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c147
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c82
-rw-r--r--arch/blackfin/mach-bf561/coreb.c402
-rw-r--r--arch/blackfin/mach-bf561/head.S512
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c108
9 files changed, 1778 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
new file mode 100644
index 000000000000..0a17c4cf0059
--- /dev/null
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -0,0 +1,222 @@
1if BF561
2
3menu "BF561 Specific Configuration"
4
5comment "Core B Support"
6
7menu "Core B Support"
8
9config BF561_COREB
10 bool "Enable Core B support"
11 default y
12
13config BF561_COREB_RESET
14 bool "Enable Core B reset support"
15 default n
16 help
17 This requires code in the application that is loaded
18 into Core B. In order to reset, the application needs
19 to install an interrupt handler for Supplemental
20 Interrupt 0, that sets RETI to 0xff600000 and writes
21 bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
22 This causes Core B to stall when Supplemental Interrupt
23 0 is set, and will reset PC to 0xff600000 when
24 COREB_SRAM_INIT is cleared.
25
26endmenu
27
28comment "Interrupt Priority Assignment"
29
30menu "Priority"
31
32config IRQ_PLL_WAKEUP
33 int "PLL Wakeup Interrupt"
34 default 7
35config IRQ_DMA1_ERROR
36 int "DMA1 Error (generic)"
37 default 7
38config IRQ_DMA2_ERROR
39 int "DMA2 Error (generic)"
40 default 7
41config IRQ_IMDMA_ERROR
42 int "IMDMA Error (generic)"
43 default 7
44config IRQ_PPI0_ERROR
45 int "PPI0 Error Interrupt"
46 default 7
47config IRQ_PPI1_ERROR
48 int "PPI1 Error Interrupt"
49 default 7
50config IRQ_SPORT0_ERROR
51 int "SPORT0 Error Interrupt"
52 default 7
53config IRQ_SPORT1_ERROR
54 int "SPORT1 Error Interrupt"
55 default 7
56config IRQ_SPI_ERROR
57 int "SPI Error Interrupt"
58 default 7
59config IRQ_UART_ERROR
60 int "UART Error Interrupt"
61 default 7
62config IRQ_RESERVED_ERROR
63 int "Reserved Interrupt"
64 default 7
65config IRQ_DMA1_0
66 int "DMA1 0 Interrupt(PPI1)"
67 default 8
68config IRQ_DMA1_1
69 int "DMA1 1 Interrupt(PPI2)"
70 default 8
71config IRQ_DMA1_2
72 int "DMA1 2 Interrupt"
73 default 8
74config IRQ_DMA1_3
75 int "DMA1 3 Interrupt"
76 default 8
77config IRQ_DMA1_4
78 int "DMA1 4 Interrupt"
79 default 8
80config IRQ_DMA1_5
81 int "DMA1 5 Interrupt"
82 default 8
83config IRQ_DMA1_6
84 int "DMA1 6 Interrupt"
85 default 8
86config IRQ_DMA1_7
87 int "DMA1 7 Interrupt"
88 default 8
89config IRQ_DMA1_8
90 int "DMA1 8 Interrupt"
91 default 8
92config IRQ_DMA1_9
93 int "DMA1 9 Interrupt"
94 default 8
95config IRQ_DMA1_10
96 int "DMA1 10 Interrupt"
97 default 8
98config IRQ_DMA1_11
99 int "DMA1 11 Interrupt"
100 default 8
101config IRQ_DMA2_0
102 int "DMA2 0 (SPORT0 RX)"
103 default 9
104config IRQ_DMA2_1
105 int "DMA2 1 (SPORT0 TX)"
106 default 9
107config IRQ_DMA2_2
108 int "DMA2 2 (SPORT1 RX)"
109 default 9
110config IRQ_DMA2_3
111 int "DMA2 3 (SPORT2 TX)"
112 default 9
113config IRQ_DMA2_4
114 int "DMA2 4 (SPI)"
115 default 9
116config IRQ_DMA2_5
117 int "DMA2 5 (UART RX)"
118 default 9
119config IRQ_DMA2_6
120 int "DMA2 6 (UART TX)"
121 default 9
122config IRQ_DMA2_7
123 int "DMA2 7 Interrupt"
124 default 9
125config IRQ_DMA2_8
126 int "DMA2 8 Interrupt"
127 default 9
128config IRQ_DMA2_9
129 int "DMA2 9 Interrupt"
130 default 9
131config IRQ_DMA2_10
132 int "DMA2 10 Interrupt"
133 default 9
134config IRQ_DMA2_11
135 int "DMA2 11 Interrupt"
136 default 9
137config IRQ_TIMER0
138 int "TIMER 0 Interrupt"
139 default 10
140config IRQ_TIMER1
141 int "TIMER 1 Interrupt"
142 default 10
143config IRQ_TIMER2
144 int "TIMER 2 Interrupt"
145 default 10
146config IRQ_TIMER3
147 int "TIMER 3 Interrupt"
148 default 10
149config IRQ_TIMER4
150 int "TIMER 4 Interrupt"
151 default 10
152config IRQ_TIMER5
153 int "TIMER 5 Interrupt"
154 default 10
155config IRQ_TIMER6
156 int "TIMER 6 Interrupt"
157 default 10
158config IRQ_TIMER7
159 int "TIMER 7 Interrupt"
160 default 10
161config IRQ_TIMER8
162 int "TIMER 8 Interrupt"
163 default 10
164config IRQ_TIMER9
165 int "TIMER 9 Interrupt"
166 default 10
167config IRQ_TIMER10
168 int "TIMER 10 Interrupt"
169 default 10
170config IRQ_TIMER11
171 int "TIMER 11 Interrupt"
172 default 10
173config IRQ_PROG0_INTA
174 int "Programmable Flags0 A (8)"
175 default 11
176config IRQ_PROG0_INTB
177 int "Programmable Flags0 B (8)"
178 default 11
179config IRQ_PROG1_INTA
180 int "Programmable Flags1 A (8)"
181 default 11
182config IRQ_PROG1_INTB
183 int "Programmable Flags1 B (8)"
184 default 11
185config IRQ_PROG2_INTA
186 int "Programmable Flags2 A (8)"
187 default 11
188config IRQ_PROG2_INTB
189 int "Programmable Flags2 B (8)"
190 default 11
191config IRQ_DMA1_WRRD0
192 int "MDMA1 0 write/read INT"
193 default 8
194config IRQ_DMA1_WRRD1
195 int "MDMA1 1 write/read INT"
196 default 8
197config IRQ_DMA2_WRRD0
198 int "MDMA2 0 write/read INT"
199 default 9
200config IRQ_DMA2_WRRD1
201 int "MDMA2 1 write/read INT"
202 default 9
203config IRQ_IMDMA_WRRD0
204 int "IMDMA 0 write/read INT"
205 default 12
206config IRQ_IMDMA_WRRD1
207 int "IMDMA 1 write/read INT"
208 default 12
209config IRQ_WDTIMER
210 int "Watch Dog Timer"
211 default 13
212
213 help
214 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
215 This applies to all the above. It is not recommended to assign the
216 highest priority number 7 to UART or any other device.
217
218endmenu
219
220endmenu
221
222endif
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
new file mode 100644
index 000000000000..57f475a55161
--- /dev/null
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf561/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o
8
9obj-$(CONFIG_BF561_COREB) += coreb.o
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
new file mode 100644
index 000000000000..886edc739ab4
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -0,0 +1,7 @@
1#
2# arch/blackfin/mach-bf561/boards/Makefile
3#
4
5obj-$(CONFIG_GENERIC_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
7obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
new file mode 100644
index 000000000000..6824e956d153
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -0,0 +1,289 @@
1/*
2 * File: arch/blackfin/mach-bf533/boards/cm_bf561.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au> Copright 2005
5 *
6 * Created: 2006
7 * Description: Board description file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/device.h>
31#include <linux/platform_device.h>
32#include <linux/mtd/mtd.h>
33#include <linux/mtd/partitions.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h>
37#include <asm/irq.h>
38#include <asm/bfin5xx_spi.h>
39
40/*
41 * Name the Board for the /proc/cpuinfo
42 */
43char *bfin_board_name = "Bluetechnix CM BF561";
44
45#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
46/* all SPI perpherals info goes here */
47
48#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
49static struct mtd_partition bfin_spi_flash_partitions[] = {
50 {
51 .name = "bootloader",
52 .size = 0x00020000,
53 .offset = 0,
54 .mask_flags = MTD_CAP_ROM
55 },{
56 .name = "kernel",
57 .size = 0xe0000,
58 .offset = 0x20000
59 },{
60 .name = "file system",
61 .size = 0x700000,
62 .offset = 0x00100000,
63 }
64};
65
66static struct flash_platform_data bfin_spi_flash_data = {
67 .name = "m25p80",
68 .parts = bfin_spi_flash_partitions,
69 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
70 .type = "m25p64",
71};
72
73/* SPI flash chip (m25p64) */
74static struct bfin5xx_spi_chip spi_flash_chip_info = {
75 .enable_dma = 0, /* use dma transfer with this chip*/
76 .bits_per_word = 8,
77};
78#endif
79
80#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
81/* SPI ADC chip */
82static struct bfin5xx_spi_chip spi_adc_chip_info = {
83 .enable_dma = 1, /* use dma transfer with this chip*/
84 .bits_per_word = 16,
85};
86#endif
87
88#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
89static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
90 .enable_dma = 0,
91 .bits_per_word = 16,
92};
93#endif
94
95#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
96static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
97 .enable_dma = 0,
98 .bits_per_word = 16,
99};
100#endif
101
102#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
103static struct bfin5xx_spi_chip spi_mmc_chip_info = {
104 .enable_dma = 1,
105 .bits_per_word = 8,
106};
107#endif
108
109static struct spi_board_info bfin_spi_board_info[] __initdata = {
110#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
111 {
112 /* the modalias must be the same as spi device driver name */
113 .modalias = "m25p80", /* Name of spi_driver for this device */
114 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
115 .bus_num = 1, /* Framework bus number */
116 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
117 .platform_data = &bfin_spi_flash_data,
118 .controller_data = &spi_flash_chip_info,
119 .mode = SPI_MODE_3,
120 },
121#endif
122
123#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
124 {
125 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
126 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
127 .bus_num = 1, /* Framework bus number */
128 .chip_select = 1, /* Framework chip select. */
129 .platform_data = NULL, /* No spi_driver specific config */
130 .controller_data = &spi_adc_chip_info,
131 },
132#endif
133
134#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
135 {
136 .modalias = "ad1836-spi",
137 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
138 .bus_num = 1,
139 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
140 .controller_data = &ad1836_spi_chip_info,
141 },
142#endif
143#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
144 {
145 .modalias = "ad9960-spi",
146 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
147 .bus_num = 1,
148 .chip_select = 1,
149 .controller_data = &ad9960_spi_chip_info,
150 },
151#endif
152#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
153 {
154 .modalias = "spi_mmc",
155 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
156 .bus_num = 1,
157 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
158 .platform_data = NULL,
159 .controller_data = &spi_mmc_chip_info,
160 .mode = SPI_MODE_3,
161 },
162#endif
163};
164
165/* SPI controller data */
166static struct bfin5xx_spi_master spi_bfin_master_info = {
167 .num_chipselect = 8,
168 .enable_dma = 1, /* master has the ability to do dma transfer */
169};
170
171static struct platform_device spi_bfin_master_device = {
172 .name = "bfin-spi-master",
173 .id = 1, /* Bus number */
174 .dev = {
175 .platform_data = &spi_bfin_master_info, /* Passed to driver */
176 },
177};
178#endif /* spi master and devices */
179
180
181#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
182
183static struct resource smc91x_resources[] = {
184 {
185 .name = "smc91x-regs",
186 .start = 0x28000300,
187 .end = 0x28000300 + 16,
188 .flags = IORESOURCE_MEM,
189 },{
190 .start = IRQ_PF0,
191 .end = IRQ_PF0,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
193 },
194};
195static struct platform_device smc91x_device = {
196 .name = "smc91x",
197 .id = 0,
198 .num_resources = ARRAY_SIZE(smc91x_resources),
199 .resource = smc91x_resources,
200};
201#endif
202
203#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
204static struct resource isp1362_hcd_resources[] = {
205 {
206 .start = 0x24008000,
207 .end = 0x24008000,
208 .flags = IORESOURCE_MEM,
209 },{
210 .start = 0x24008004,
211 .end = 0x24008004,
212 .flags = IORESOURCE_MEM,
213 },{
214 .start = IRQ_PF47,
215 .end = IRQ_PF47,
216 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
217 },
218};
219
220static struct isp1362_platform_data isp1362_priv = {
221 .sel15Kres = 1,
222 .clknotstop = 0,
223 .oc_enable = 0,
224 .int_act_high = 0,
225 .int_edge_triggered = 0,
226 .remote_wakeup_connected = 0,
227 .no_power_switching = 1,
228 .power_switching_mode = 0,
229};
230
231static struct platform_device isp1362_hcd_device = {
232 .name = "isp1362-hcd",
233 .id = 0,
234 .dev = {
235 .platform_data = &isp1362_priv,
236 },
237 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
238 .resource = isp1362_hcd_resources,
239};
240#endif
241
242#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
243static struct resource bfin_uart_resources[] = {
244 {
245 .start = 0xFFC00400,
246 .end = 0xFFC004FF,
247 .flags = IORESOURCE_MEM,
248 },
249};
250
251static struct platform_device bfin_uart_device = {
252 .name = "bfin-uart",
253 .id = 1,
254 .num_resources = ARRAY_SIZE(bfin_uart_resources),
255 .resource = bfin_uart_resources,
256};
257#endif
258
259static struct platform_device *cm_bf561_devices[] __initdata = {
260
261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
262 &bfin_uart_device,
263#endif
264
265#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
266 &isp1362_hcd_device,
267#endif
268
269#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
270 &smc91x_device,
271#endif
272
273#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
274 &spi_bfin_master_device,
275#endif
276
277};
278
279static int __init cm_bf561_init(void)
280{
281 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
282 platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
283#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
284 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
285#endif
286 return 0;
287}
288
289arch_initcall(cm_bf561_init);
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
new file mode 100644
index 000000000000..14eb4f9a68ea
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -0,0 +1,147 @@
1/*
2 * File: arch/blackfin/mach-bf561/ezkit.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/device.h>
31#include <linux/platform_device.h>
32#include <linux/spi/spi.h>
33#include <asm/irq.h>
34#include <asm/bfin5xx_spi.h>
35
36/*
37 * Name the Board for the /proc/cpuinfo
38 */
39char *bfin_board_name = "ADDS-BF561-EZKIT";
40
41/*
42 * USB-LAN EzExtender board
43 * Driver needs to know address, irq and flag pin.
44 */
45#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
46static struct resource smc91x_resources[] = {
47 {
48 .name = "smc91x-regs",
49 .start = 0x2C010300,
50 .end = 0x2C010300 + 16,
51 .flags = IORESOURCE_MEM,
52 },{
53
54 .start = IRQ_PF9,
55 .end = IRQ_PF9,
56 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
57 },
58};
59
60static struct platform_device smc91x_device = {
61 .name = "smc91x",
62 .id = 0,
63 .num_resources = ARRAY_SIZE(smc91x_resources),
64 .resource = smc91x_resources,
65};
66#endif
67
68#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
69static struct resource bfin_uart_resources[] = {
70 {
71 .start = 0xFFC00400,
72 .end = 0xFFC004FF,
73 .flags = IORESOURCE_MEM,
74 },
75};
76
77static struct platform_device bfin_uart_device = {
78 .name = "bfin-uart",
79 .id = 1,
80 .num_resources = ARRAY_SIZE(bfin_uart_resources),
81 .resource = bfin_uart_resources,
82};
83#endif
84
85#ifdef CONFIG_SPI_BFIN
86#if defined(CONFIG_SND_BLACKFIN_AD1836) \
87 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
88static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
89 .enable_dma = 0,
90 .bits_per_word = 16,
91};
92#endif
93#endif
94
95/* SPI controller data */
96static struct bfin5xx_spi_master spi_bfin_master_info = {
97 .num_chipselect = 8,
98 .enable_dma = 1, /* master has the ability to do dma transfer */
99};
100
101static struct platform_device spi_bfin_master_device = {
102 .name = "bfin-spi-master",
103 .id = 1, /* Bus number */
104 .dev = {
105 .platform_data = &spi_bfin_master_info, /* Passed to driver */
106 },
107};
108
109static struct spi_board_info bfin_spi_board_info[] __initdata = {
110#if defined(CONFIG_SND_BLACKFIN_AD1836) \
111 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
112 {
113 .modalias = "ad1836-spi",
114 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
115 .bus_num = 1,
116 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
117 .controller_data = &ad1836_spi_chip_info,
118 },
119#endif
120};
121
122static struct platform_device *ezkit_devices[] __initdata = {
123#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
124 &smc91x_device,
125#endif
126#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
127 &spi_bfin_master_device,
128#endif
129#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
130 &bfin_uart_device,
131#endif
132};
133
134static int __init ezkit_init(void)
135{
136 int ret;
137
138 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
139 ret = platform_add_devices(ezkit_devices,
140 ARRAY_SIZE(ezkit_devices));
141 if (ret < 0)
142 return ret;
143 return spi_register_board_info(bfin_spi_board_info,
144 ARRAY_SIZE(bfin_spi_board_info));
145}
146
147arch_initcall(ezkit_init);
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
new file mode 100644
index 000000000000..585ecdd2f6a5
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -0,0 +1,82 @@
1/*
2 * File: arch/blackfin/mach-bf561/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <asm/irq.h>
34
35char *bfin_board_name = "UNKNOWN BOARD";
36
37/*
38 * Driver needs to know address, irq and flag pin.
39 */
40#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
41static struct resource smc91x_resources[] = {
42 {
43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM,
46 },{
47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },{
51 /*
52 * denotes the flag pin and is used directly if
53 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
54 */
55 .start = IRQ_PF9,
56 .end = IRQ_PF9,
57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
58 },
59};
60
61static struct platform_device smc91x_device = {
62 .name = "smc91x",
63 .id = 0,
64 .num_resources = ARRAY_SIZE(smc91x_resources),
65 .resource = smc91x_resources,
66};
67#endif
68
69static struct platform_device *generic_board_devices[] __initdata = {
70#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
71 &smc91x_device,
72#endif
73};
74
75static int __init generic_board_init(void)
76{
77 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
78 return platform_add_devices(generic_board_devices,
79 ARRAY_SIZE(generic_board_devices));
80}
81
82arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
new file mode 100644
index 000000000000..b28582fe083c
--- /dev/null
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -0,0 +1,402 @@
1/*
2 * File: arch/blackfin/mach-bf561/coreb.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: Handle CoreB on a BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/mm.h>
31#include <linux/miscdevice.h>
32#include <linux/device.h>
33#include <linux/ioport.h>
34#include <linux/module.h>
35#include <asm/dma.h>
36#include <asm/uaccess.h>
37
38#define MODULE_VER "v0.1"
39
40static spinlock_t coreb_lock;
41static wait_queue_head_t coreb_dma_wait;
42
43#define COREB_IS_OPEN 0x00000001
44#define COREB_IS_RUNNING 0x00000010
45
46#define CMD_COREB_INDEX 1
47#define CMD_COREB_START 2
48#define CMD_COREB_STOP 3
49#define CMD_COREB_RESET 4
50
51#define COREB_MINOR 229
52
53static unsigned long coreb_status = 0;
54static unsigned long coreb_base = 0xff600000;
55static unsigned long coreb_size = 0x4000;
56int coreb_dma_done;
57
58static loff_t coreb_lseek(struct file *file, loff_t offset, int origin);
59static ssize_t coreb_read(struct file *file, char *buf, size_t count,
60 loff_t * ppos);
61static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
62 loff_t * ppos);
63static int coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
64 unsigned long arg);
65static int coreb_open(struct inode *inode, struct file *file);
66static int coreb_release(struct inode *inode, struct file *file);
67
68static irqreturn_t coreb_dma_interrupt(int irq, void *dev_id)
69{
70 clear_dma_irqstat(CH_MEM_STREAM2_DEST);
71 coreb_dma_done = 1;
72 wake_up_interruptible(&coreb_dma_wait);
73 return IRQ_HANDLED;
74}
75
76static ssize_t coreb_write(struct file *file, const char *buf, size_t count,
77 loff_t * ppos)
78{
79 unsigned long p = *ppos;
80 ssize_t wrote = 0;
81
82 if (p + count > coreb_size)
83 return -EFAULT;
84
85 while (count > 0) {
86 int len = count;
87
88 if (len > PAGE_SIZE)
89 len = PAGE_SIZE;
90
91 coreb_dma_done = 0;
92
93 /* Source Channel */
94 set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
95 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
96 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
97 set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
98 /* Destination Channel */
99 set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
100 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
101 set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
102 set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
103
104 enable_dma(CH_MEM_STREAM2_SRC);
105 enable_dma(CH_MEM_STREAM2_DEST);
106
107 wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
108
109 disable_dma(CH_MEM_STREAM2_SRC);
110 disable_dma(CH_MEM_STREAM2_DEST);
111
112 count -= len;
113 wrote += len;
114 buf += len;
115 p += len;
116 }
117 *ppos = p;
118 return wrote;
119}
120
121static ssize_t coreb_read(struct file *file, char *buf, size_t count,
122 loff_t * ppos)
123{
124 unsigned long p = *ppos;
125 ssize_t read = 0;
126
127 if ((p + count) > coreb_size)
128 return -EFAULT;
129
130 while (count > 0) {
131 int len = count;
132
133 if (len > PAGE_SIZE)
134 len = PAGE_SIZE;
135
136 coreb_dma_done = 0;
137
138 /* Source Channel */
139 set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
140 set_dma_x_count(CH_MEM_STREAM2_SRC, len);
141 set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
142 set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
143 /* Destination Channel */
144 set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
145 set_dma_x_count(CH_MEM_STREAM2_DEST, len);
146 set_dma_x_modify(CH_MEM_STREAM2_DEST, sizeof(char));
147 set_dma_config(CH_MEM_STREAM2_DEST, WNR | RESTART | DI_EN);
148
149 enable_dma(CH_MEM_STREAM2_SRC);
150 enable_dma(CH_MEM_STREAM2_DEST);
151
152 wait_event_interruptible(coreb_dma_wait, coreb_dma_done);
153
154 disable_dma(CH_MEM_STREAM2_SRC);
155 disable_dma(CH_MEM_STREAM2_DEST);
156
157 count -= len;
158 read += len;
159 buf += len;
160 p += len;
161 }
162
163 return read;
164}
165
166static loff_t coreb_lseek(struct file *file, loff_t offset, int origin)
167{
168 loff_t ret;
169
170 mutex_lock(&file->f_dentry->d_inode->i_mutex);
171
172 switch (origin) {
173 case 0 /* SEEK_SET */ :
174 if (offset < coreb_size) {
175 file->f_pos = offset;
176 ret = file->f_pos;
177 } else
178 ret = -EINVAL;
179 break;
180 case 1 /* SEEK_CUR */ :
181 if ((offset + file->f_pos) < coreb_size) {
182 file->f_pos += offset;
183 ret = file->f_pos;
184 } else
185 ret = -EINVAL;
186 default:
187 ret = -EINVAL;
188 }
189 mutex_unlock(&file->f_dentry->d_inode->i_mutex);
190 return ret;
191}
192
193static int coreb_open(struct inode *inode, struct file *file)
194{
195 spin_lock_irq(&coreb_lock);
196
197 if (coreb_status & COREB_IS_OPEN)
198 goto out_busy;
199
200 coreb_status |= COREB_IS_OPEN;
201
202 spin_unlock_irq(&coreb_lock);
203 return 0;
204
205 out_busy:
206 spin_unlock_irq(&coreb_lock);
207 return -EBUSY;
208}
209
210static int coreb_release(struct inode *inode, struct file *file)
211{
212 spin_lock_irq(&coreb_lock);
213 coreb_status &= ~COREB_IS_OPEN;
214 spin_unlock_irq(&coreb_lock);
215 return 0;
216}
217
218static int coreb_ioctl(struct inode *inode, struct file *file,
219 unsigned int cmd, unsigned long arg)
220{
221 int retval = 0;
222 int coreb_index = 0;
223
224 switch (cmd) {
225 case CMD_COREB_INDEX:
226 if (copy_from_user(&coreb_index, (int *)arg, sizeof(int))) {
227 retval = -EFAULT;
228 break;
229 }
230
231 spin_lock_irq(&coreb_lock);
232 switch (coreb_index) {
233 case 0:
234 coreb_base = 0xff600000;
235 coreb_size = 0x4000;
236 break;
237 case 1:
238 coreb_base = 0xff610000;
239 coreb_size = 0x4000;
240 break;
241 case 2:
242 coreb_base = 0xff500000;
243 coreb_size = 0x8000;
244 break;
245 case 3:
246 coreb_base = 0xff400000;
247 coreb_size = 0x8000;
248 break;
249 default:
250 retval = -EINVAL;
251 break;
252 }
253 spin_unlock_irq(&coreb_lock);
254
255 mutex_lock(&file->f_dentry->d_inode->i_mutex);
256 file->f_pos = 0;
257 mutex_unlock(&file->f_dentry->d_inode->i_mutex);
258 break;
259 case CMD_COREB_START:
260 spin_lock_irq(&coreb_lock);
261 if (coreb_status & COREB_IS_RUNNING) {
262 retval = -EBUSY;
263 break;
264 }
265 printk(KERN_INFO "Starting Core B\n");
266 coreb_status |= COREB_IS_RUNNING;
267 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
268 SSYNC();
269 spin_lock_irq(&coreb_lock);
270 break;
271#if defined(CONFIG_BF561_COREB_RESET)
272 case CMD_COREB_STOP:
273 spin_lock_irq(&coreb_lock);
274 printk(KERN_INFO "Stopping Core B\n");
275 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
276 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
277 coreb_status &= ~COREB_IS_RUNNING;
278 spin_lock_irq(&coreb_lock);
279 break;
280 case CMD_COREB_RESET:
281 printk(KERN_INFO "Resetting Core B\n");
282 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
283 break;
284#endif
285 }
286
287 return retval;
288}
289
290static struct file_operations coreb_fops = {
291 .owner = THIS_MODULE,
292 .llseek = coreb_lseek,
293 .read = coreb_read,
294 .write = coreb_write,
295 .ioctl = coreb_ioctl,
296 .open = coreb_open,
297 .release = coreb_release
298};
299
300static struct miscdevice coreb_dev = {
301 COREB_MINOR,
302 "coreb",
303 &coreb_fops
304};
305
306static ssize_t coreb_show_status(struct device *dev, struct device_attribute *attr, char *buf)
307{
308 return sprintf(buf,
309 "Base Address:\t0x%08lx\n"
310 "Core B is %s\n"
311 "SICA_SYSCR:\t%04x\n"
312 "SICB_SYSCR:\t%04x\n"
313 "\n"
314 "IRQ Status:\tCore A\t\tCore B\n"
315 "ISR0:\t\t%08x\t\t%08x\n"
316 "ISR1:\t\t%08x\t\t%08x\n"
317 "IMASK0:\t\t%08x\t\t%08x\n"
318 "IMASK1:\t\t%08x\t\t%08x\n",
319 coreb_base,
320 coreb_status & COREB_IS_RUNNING ? "running" : "stalled",
321 bfin_read_SICA_SYSCR(), bfin_read_SICB_SYSCR(),
322 bfin_read_SICA_ISR0(), bfin_read_SICB_ISR0(),
323 bfin_read_SICA_ISR1(), bfin_read_SICB_ISR0(),
324 bfin_read_SICA_IMASK0(), bfin_read_SICB_IMASK0(),
325 bfin_read_SICA_IMASK1(), bfin_read_SICB_IMASK1());
326}
327
328static DEVICE_ATTR(coreb_status, S_IRUGO, coreb_show_status, NULL);
329
330int __init bf561_coreb_init(void)
331{
332 init_waitqueue_head(&coreb_dma_wait);
333
334 spin_lock_init(&coreb_lock);
335 /* Request the core memory regions for Core B */
336 if (request_mem_region(0xff600000, 0x4000,
337 "Core B - Instruction SRAM") == NULL)
338 goto exit;
339
340 if (request_mem_region(0xFF610000, 0x4000,
341 "Core B - Instruction SRAM") == NULL)
342 goto release_instruction_a_sram;
343
344 if (request_mem_region(0xFF500000, 0x8000,
345 "Core B - Data Bank B SRAM") == NULL)
346 goto release_instruction_b_sram;
347
348 if (request_mem_region(0xff400000, 0x8000,
349 "Core B - Data Bank A SRAM") == NULL)
350 goto release_data_b_sram;
351
352 if (request_dma(CH_MEM_STREAM2_DEST, "Core B - DMA Destination") < 0)
353 goto release_data_a_sram;
354
355 if (request_dma(CH_MEM_STREAM2_SRC, "Core B - DMA Source") < 0)
356 goto release_dma_dest;
357
358 set_dma_callback(CH_MEM_STREAM2_DEST, coreb_dma_interrupt, NULL);
359
360 misc_register(&coreb_dev);
361
362 if (device_create_file(coreb_dev.this_device, &dev_attr_coreb_status))
363 goto release_dma_src;
364
365 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
366 return 0;
367
368 release_dma_src:
369 free_dma(CH_MEM_STREAM2_SRC);
370 release_dma_dest:
371 free_dma(CH_MEM_STREAM2_DEST);
372 release_data_a_sram:
373 release_mem_region(0xff400000, 0x8000);
374 release_data_b_sram:
375 release_mem_region(0xff500000, 0x8000);
376 release_instruction_b_sram:
377 release_mem_region(0xff610000, 0x4000);
378 release_instruction_a_sram:
379 release_mem_region(0xff600000, 0x4000);
380 exit:
381 return -ENOMEM;
382}
383
384void __exit bf561_coreb_exit(void)
385{
386 device_remove_file(coreb_dev.this_device, &dev_attr_coreb_status);
387 misc_deregister(&coreb_dev);
388
389 release_mem_region(0xff610000, 0x4000);
390 release_mem_region(0xff600000, 0x4000);
391 release_mem_region(0xff500000, 0x8000);
392 release_mem_region(0xff400000, 0x8000);
393
394 free_dma(CH_MEM_STREAM2_DEST);
395 free_dma(CH_MEM_STREAM2_SRC);
396}
397
398module_init(bf561_coreb_init);
399module_exit(bf561_coreb_exit);
400
401MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
402MODULE_DESCRIPTION("BF561 Core B Support");
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
new file mode 100644
index 000000000000..7bca478526b9
--- /dev/null
+++ b/arch/blackfin/mach-bf561/head.S
@@ -0,0 +1,512 @@
1/*
2 * File: arch/blackfin/mach-bf561/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author:
5 *
6 * Created:
7 * Description: BF561 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#if CONFIG_BFIN_KERNEL_CLOCK
33#include <asm/mach/mem_init.h>
34#endif
35
36.global __rambase
37.global __ramstart
38.global __ramend
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem
42
43#define INITIAL_STACK 0xFFB01000
44
45.text
46
47ENTRY(__start)
48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Set the SYSCFG register */
52 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
54 R0 = 0;
55
56 /*Clear Out All the data and pointer Registers*/
57 R1 = R0;
58 R2 = R0;
59 R3 = R0;
60 R4 = R0;
61 R5 = R0;
62 R6 = R0;
63
64 P0 = R0;
65 P1 = R0;
66 P2 = R0;
67 P3 = R0;
68 P4 = R0;
69 P5 = R0;
70
71 LC0 = r0;
72 LC1 = r0;
73 L0 = r0;
74 L1 = r0;
75 L2 = r0;
76 L3 = r0;
77
78 /* Clear Out All the DAG Registers*/
79 B0 = r0;
80 B1 = r0;
81 B2 = r0;
82 B3 = r0;
83
84 I0 = r0;
85 I1 = r0;
86 I2 = r0;
87 I3 = r0;
88
89 M0 = r0;
90 M1 = r0;
91 M2 = r0;
92 M3 = r0;
93
94 /* Turn off the icache */
95 p0.l = (IMEM_CONTROL & 0xFFFF);
96 p0.h = (IMEM_CONTROL >> 16);
97 R1 = [p0];
98 R0 = ~ENICPLB;
99 R0 = R0 & R1;
100
101 /* Anomaly 05000125 */
102#ifdef ANOMALY_05000125
103 CLI R2;
104 SSYNC;
105#endif
106 [p0] = R0;
107 SSYNC;
108#ifdef ANOMALY_05000125
109 STI R2;
110#endif
111
112 /* Turn off the dcache */
113 p0.l = (DMEM_CONTROL & 0xFFFF);
114 p0.h = (DMEM_CONTROL >> 16);
115 R1 = [p0];
116 R0 = ~ENDCPLB;
117 R0 = R0 & R1;
118
119 /* Anomaly 05000125 */
120#ifdef ANOMALY_05000125
121 CLI R2;
122 SSYNC;
123#endif
124 [p0] = R0;
125 SSYNC;
126#ifdef ANOMALY_05000125
127 STI R2;
128#endif
129
130 /* Initialise UART*/
131 p0.h = hi(UART_LCR);
132 p0.l = lo(UART_LCR);
133 r0 = 0x0(Z);
134 w[p0] = r0.L; /* To enable DLL writes */
135 ssync;
136
137 p0.h = hi(UART_DLL);
138 p0.l = lo(UART_DLL);
139 r0 = 0x0(Z);
140 w[p0] = r0.L;
141 ssync;
142
143 p0.h = hi(UART_DLH);
144 p0.l = lo(UART_DLH);
145 r0 = 0x00(Z);
146 w[p0] = r0.L;
147 ssync;
148
149 p0.h = hi(UART_GCTL);
150 p0.l = lo(UART_GCTL);
151 r0 = 0x0(Z);
152 w[p0] = r0.L; /* To enable UART clock */
153 ssync;
154
155 /* Initialize stack pointer */
156 sp.l = lo(INITIAL_STACK);
157 sp.h = hi(INITIAL_STACK);
158 fp = sp;
159 usp = sp;
160
161 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
162 call _bf53x_relocate_l1_mem;
163#if CONFIG_BFIN_KERNEL_CLOCK
164 call _start_dma_code;
165#endif
166
167 /* Code for initializing Async memory banks */
168
169 p2.h = hi(EBIU_AMBCTL1);
170 p2.l = lo(EBIU_AMBCTL1);
171 r0.h = hi(AMBCTL1VAL);
172 r0.l = lo(AMBCTL1VAL);
173 [p2] = r0;
174 ssync;
175
176 p2.h = hi(EBIU_AMBCTL0);
177 p2.l = lo(EBIU_AMBCTL0);
178 r0.h = hi(AMBCTL0VAL);
179 r0.l = lo(AMBCTL0VAL);
180 [p2] = r0;
181 ssync;
182
183 p2.h = hi(EBIU_AMGCTL);
184 p2.l = lo(EBIU_AMGCTL);
185 r0 = AMGCTLVAL;
186 w[p2] = r0;
187 ssync;
188
189 /* This section keeps the processor in supervisor mode
190 * during kernel boot. Switches to user mode at end of boot.
191 * See page 3-9 of Hardware Reference manual for documentation.
192 */
193
194 /* EVT15 = _real_start */
195
196 p0.l = lo(EVT15);
197 p0.h = hi(EVT15);
198 p1.l = _real_start;
199 p1.h = _real_start;
200 [p0] = p1;
201 csync;
202
203 p0.l = lo(IMASK);
204 p0.h = hi(IMASK);
205 p1.l = IMASK_IVG15;
206 p1.h = 0x0;
207 [p0] = p1;
208 csync;
209
210 raise 15;
211 p0.l = .LWAIT_HERE;
212 p0.h = .LWAIT_HERE;
213 reti = p0;
214#if defined(ANOMALY_05000281)
215 nop; nop; nop;
216#endif
217 rti;
218
219.LWAIT_HERE:
220 jump .LWAIT_HERE;
221
222ENTRY(_real_start)
223 [ -- sp ] = reti;
224 p0.l = lo(WDOGA_CTL);
225 p0.h = hi(WDOGA_CTL);
226 r0 = 0xAD6(z);
227 w[p0] = r0; /* watchdog off for now */
228 ssync;
229
230 /* Code update for BSS size == 0
231 * Zero out the bss region.
232 */
233
234 p1.l = ___bss_start;
235 p1.h = ___bss_start;
236 p2.l = ___bss_stop;
237 p2.h = ___bss_stop;
238 r0 = 0;
239 p2 -= p1;
240 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
241.L_clear_bss:
242 B[p1++] = r0;
243
244 /* In case there is a NULL pointer reference
245 * Zero out region before stext
246 */
247
248 p1.l = 0x0;
249 p1.h = 0x0;
250 r0.l = __stext;
251 r0.h = __stext;
252 r0 = r0 >> 1;
253 p2 = r0;
254 r0 = 0;
255 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
256.L_clear_zero:
257 W[p1++] = r0;
258
259/* pass the uboot arguments to the global value command line */
260 R0 = R7;
261 call _cmdline_init;
262
263 p1.l = __rambase;
264 p1.h = __rambase;
265 r0.l = __sdata;
266 r0.h = __sdata;
267 [p1] = r0;
268
269 p1.l = __ramstart;
270 p1.h = __ramstart;
271 p3.l = ___bss_stop;
272 p3.h = ___bss_stop;
273
274 r1 = p3;
275 [p1] = r1;
276
277 /*
278 * load the current thread pointer and stack
279 */
280 r1.l = _init_thread_union;
281 r1.h = _init_thread_union;
282
283 r2.l = 0x2000;
284 r2.h = 0x0000;
285 r1 = r1 + r2;
286 sp = r1;
287 usp = sp;
288 fp = sp;
289 call _start_kernel;
290.L_exit:
291 jump.s .L_exit;
292
293.section .l1.text
294#if CONFIG_BFIN_KERNEL_CLOCK
295ENTRY(_start_dma_code)
296 p0.h = hi(SICA_IWR0);
297 p0.l = lo(SICA_IWR0);
298 r0.l = 0x1;
299 [p0] = r0;
300 SSYNC;
301
302 /*
303 * Set PLL_CTL
304 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
305 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
306 * - [7] = output delay (add 200ps of delay to mem signals)
307 * - [6] = input delay (add 200ps of input delay to mem signals)
308 * - [5] = PDWN : 1=All Clocks off
309 * - [3] = STOPCK : 1=Core Clock off
310 * - [1] = PLL_OFF : 1=Disable Power to PLL
311 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
312 * all other bits set to zero
313 */
314
315 p0.h = hi(PLL_LOCKCNT);
316 p0.l = lo(PLL_LOCKCNT);
317 r0 = 0x300(Z);
318 w[p0] = r0.l;
319 ssync;
320
321 P2.H = hi(EBIU_SDGCTL);
322 P2.L = lo(EBIU_SDGCTL);
323 R0 = [P2];
324 BITSET (R0, 24);
325 [P2] = R0;
326 SSYNC;
327
328 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
329 r0 = r0 << 9; /* Shift it over, */
330 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
331 r0 = r1 | r0;
332 r1 = PLL_BYPASS; /* Bypass the PLL? */
333 r1 = r1 << 8; /* Shift it over */
334 r0 = r1 | r0; /* add them all together */
335
336 p0.h = hi(PLL_CTL);
337 p0.l = lo(PLL_CTL); /* Load the address */
338 cli r2; /* Disable interrupts */
339 ssync;
340 w[p0] = r0.l; /* Set the value */
341 idle; /* Wait for the PLL to stablize */
342 sti r2; /* Enable interrupts */
343
344.Lcheck_again:
345 p0.h = hi(PLL_STAT);
346 p0.l = lo(PLL_STAT);
347 R0 = W[P0](Z);
348 CC = BITTST(R0,5);
349 if ! CC jump .Lcheck_again;
350
351 /* Configure SCLK & CCLK Dividers */
352 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
353 p0.h = hi(PLL_DIV);
354 p0.l = lo(PLL_DIV);
355 w[p0] = r0.l;
356 ssync;
357
358 p0.l = lo(EBIU_SDRRC);
359 p0.h = hi(EBIU_SDRRC);
360 r0 = mem_SDRRC;
361 w[p0] = r0.l;
362 ssync;
363
364 p0.l = (EBIU_SDBCTL & 0xFFFF);
365 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
366 r0 = mem_SDBCTL;
367 w[p0] = r0.l;
368 ssync;
369
370 P2.H = hi(EBIU_SDGCTL);
371 P2.L = lo(EBIU_SDGCTL);
372 R0 = [P2];
373 BITCLR (R0, 24);
374 p0.h = hi(EBIU_SDSTAT);
375 p0.l = lo(EBIU_SDSTAT);
376 r2.l = w[p0];
377 cc = bittst(r2,3);
378 if !cc jump .Lskip;
379 NOP;
380 BITSET (R0, 23);
381.Lskip:
382 [P2] = R0;
383 SSYNC;
384
385 R0.L = lo(mem_SDGCTL);
386 R0.H = hi(mem_SDGCTL);
387 R1 = [p2];
388 R1 = R1 | R0;
389 [P2] = R1;
390 SSYNC;
391
392 RTS;
393#endif /* CONFIG_BFIN_KERNEL_CLOCK */
394
395ENTRY(_bfin_reset)
396 /* No more interrupts to be handled*/
397 CLI R6;
398 SSYNC;
399
400#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
401 p0.h = hi(FIO_INEN);
402 p0.l = lo(FIO_INEN);
403 r0.l = ~(PF1 | PF0);
404 w[p0] = r0.l;
405
406 p0.h = hi(FIO_DIR);
407 p0.l = lo(FIO_DIR);
408 r0.l = (PF1 | PF0);
409 w[p0] = r0.l;
410
411 p0.h = hi(FIO_FLAG_C);
412 p0.l = lo(FIO_FLAG_C);
413 r0.l = (PF1 | PF0);
414 w[p0] = r0.l;
415#endif
416
417 /* Clear the bits 13-15 in SWRST if they werent cleared */
418 p0.h = hi(SICA_SWRST);
419 p0.l = lo(SICA_SWRST);
420 csync;
421 r0.l = w[p0];
422
423 /* Clear the IMASK register */
424 p0.h = hi(IMASK);
425 p0.l = lo(IMASK);
426 r0 = 0x0;
427 [p0] = r0;
428
429 /* Clear the ILAT register */
430 p0.h = hi(ILAT);
431 p0.l = lo(ILAT);
432 r0 = [p0];
433 [p0] = r0;
434 SSYNC;
435
436 /* Disable the WDOG TIMER */
437 p0.h = hi(WDOGA_CTL);
438 p0.l = lo(WDOGA_CTL);
439 r0.l = 0xAD6;
440 w[p0] = r0.l;
441 SSYNC;
442
443 /* Clear the sticky bit incase it is already set */
444 p0.h = hi(WDOGA_CTL);
445 p0.l = lo(WDOGA_CTL);
446 r0.l = 0x8AD6;
447 w[p0] = r0.l;
448 SSYNC;
449
450 /* Program the count value */
451 R0.l = 0x100;
452 R0.h = 0x0;
453 P0.h = hi(WDOGA_CNT);
454 P0.l = lo(WDOGA_CNT);
455 [P0] = R0;
456 SSYNC;
457
458 /* Program WDOG_STAT if necessary */
459 P0.h = hi(WDOGA_CTL);
460 P0.l = lo(WDOGA_CTL);
461 R0 = W[P0](Z);
462 CC = BITTST(R0,1);
463 if !CC JUMP .LWRITESTAT;
464 CC = BITTST(R0,2);
465 if !CC JUMP .LWRITESTAT;
466 JUMP .LSKIP_WRITE;
467
468.LWRITESTAT:
469 /* When watch dog timer is enabled,
470 * a write to STAT will load the contents of CNT to STAT
471 */
472 R0 = 0x0000(z);
473 P0.h = hi(WDOGA_STAT);
474 P0.l = lo(WDOGA_STAT)
475 [P0] = R0;
476 SSYNC;
477
478.LSKIP_WRITE:
479 /* Enable the reset event */
480 P0.h = hi(WDOGA_CTL);
481 P0.l = lo(WDOGA_CTL);
482 R0 = W[P0](Z);
483 BITCLR(R0,1);
484 BITCLR(R0,2);
485 W[P0] = R0.L;
486 SSYNC;
487 NOP;
488
489 /* Enable the wdog counter */
490 R0 = W[P0](Z);
491 BITCLR(R0,4);
492 W[P0] = R0.L;
493 SSYNC;
494
495 IDLE;
496
497 RTS;
498
499.data
500
501/*
502 * Set up the usable of RAM stuff. Size of RAM is determined then
503 * an initial stack set up at the end.
504 */
505
506.align 4
507__rambase:
508.long 0
509__ramstart:
510.long 0
511__ramend:
512.long 0
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
new file mode 100644
index 000000000000..89c52ff95b27
--- /dev/null
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -0,0 +1,108 @@
1/*
2 * File: arch/blackfin/mach-bf561/ints-priority.c
3 * Based on: arch/blackfin/mach-bf537/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <asm/blackfin.h>
32#include <asm/irq.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
39 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
40 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
41 ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
42 ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
43 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
44 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
45
46 bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
47 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
48 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
49 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
50 ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
51 ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
52 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
53 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
54
55 bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
56 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
57 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
58 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
59 ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
60 ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
61 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
62 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
63
64 bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
65 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
66 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
67 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
68 ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
69 ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
70 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
71 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
72
73 bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
74 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
75 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
76 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
77 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
78 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
79 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
80 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
81
82 bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
83 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
84 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
85 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
86 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
87 ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
88 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
89 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
90
91 bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
92 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
93 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
94 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
95 ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
96 ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
97 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
98 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
99
100 bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
101 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
102 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
103 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
104 (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
105 (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
106
107 SSYNC();
108}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 09:40:22 -0500