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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/blackfin/mach-bf561
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/atomic.S5
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c8
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c14
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c80
-rw-r--r--arch/blackfin/mach-bf561/boards/tepla.c2
-rw-r--r--arch/blackfin/mach-bf561/coreb.c12
-rw-r--r--arch/blackfin/mach-bf561/dma.c18
-rw-r--r--arch/blackfin/mach-bf561/hotplug.c24
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h21
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h122
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h59
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h629
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h502
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/irq.h505
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h54
-rw-r--r--arch/blackfin/mach-bf561/include/mach/smp.h10
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf561/secondary.S35
-rw-r--r--arch/blackfin/mach-bf561/smp.c79
22 files changed, 842 insertions, 1385 deletions
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
index f99f174b129f..52d6f73fcced 100644
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -49,6 +49,7 @@ ENTRY(_get_core_lock)
49 jump .Lretry_corelock 49 jump .Lretry_corelock
50.Ldone_corelock: 50.Ldone_corelock:
51 p0 = r1; 51 p0 = r1;
52 /* flush core internal write buffer before invalidate dcache */
52 CSYNC(r2); 53 CSYNC(r2);
53 flushinv[p0]; 54 flushinv[p0];
54 SSYNC(r2); 55 SSYNC(r2);
@@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm)
685 r1 = -L1_CACHE_BYTES; 686 r1 = -L1_CACHE_BYTES;
686 r1 = r0 & r1; 687 r1 = r0 & r1;
687 p0 = r1; 688 p0 = r1;
689 /* flush core internal write buffer before invalidate dcache */
690 CSYNC(r2);
688 flushinv[p0]; 691 flushinv[p0];
689 SSYNC(r2); 692 SSYNC(r2);
690 r0 = [p1]; 693 r0 = [p1];
@@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm)
907 r1 = -L1_CACHE_BYTES; 910 r1 = -L1_CACHE_BYTES;
908 r1 = r0 & r1; 911 r1 = r0 & r1;
909 p0 = r1; 912 p0 = r1;
913 /* flush core internal write buffer before invalidate dcache */
914 CSYNC(r2);
910 flushinv[p0]; 915 flushinv[p0];
911 SSYNC(r2); 916 SSYNC(r2);
912 r0 = [p1]; 917 r0 = [p1];
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 35b6d124c1e3..9231a942892b 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -224,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
224 }, 224 },
225}; 225};
226 226
227unsigned short bfin_uart0_peripherals[] = { 227static unsigned short bfin_uart0_peripherals[] = {
228 P_UART0_TX, P_UART0_RX, 0 228 P_UART0_TX, P_UART0_RX, 0
229}; 229};
230 230
@@ -243,7 +243,6 @@ static struct platform_device bfin_uart0_device = {
243 243
244#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 244#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
245 245
246#ifdef CONFIG_MTD_PARTITIONS
247const char *part_probes[] = { "cmdlinepart", NULL }; 246const char *part_probes[] = { "cmdlinepart", NULL };
248 247
249static struct mtd_partition bfin_plat_nand_partitions[] = { 248static struct mtd_partition bfin_plat_nand_partitions[] = {
@@ -257,7 +256,6 @@ static struct mtd_partition bfin_plat_nand_partitions[] = {
257 .offset = MTDPART_OFS_APPEND, 256 .offset = MTDPART_OFS_APPEND,
258 }, 257 },
259}; 258};
260#endif
261 259
262#define BFIN_NAND_PLAT_CLE 2 260#define BFIN_NAND_PLAT_CLE 2
263#define BFIN_NAND_PLAT_ALE 3 261#define BFIN_NAND_PLAT_ALE 3
@@ -286,11 +284,9 @@ static struct platform_nand_data bfin_plat_nand_data = {
286 .chip = { 284 .chip = {
287 .nr_chips = 1, 285 .nr_chips = 1,
288 .chip_delay = 30, 286 .chip_delay = 30,
289#ifdef CONFIG_MTD_PARTITIONS
290 .part_probe_types = part_probes, 287 .part_probe_types = part_probes,
291 .partitions = bfin_plat_nand_partitions, 288 .partitions = bfin_plat_nand_partitions,
292 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), 289 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
293#endif
294 }, 290 },
295 .ctrl = { 291 .ctrl = {
296 .cmd_ctrl = bfin_plat_nand_cmd_ctrl, 292 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
@@ -302,7 +298,7 @@ static struct platform_nand_data bfin_plat_nand_data = {
302static struct resource bfin_plat_nand_resources = { 298static struct resource bfin_plat_nand_resources = {
303 .start = 0x24000000, 299 .start = 0x24000000,
304 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), 300 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
305 .flags = IORESOURCE_IO, 301 .flags = IORESOURCE_MEM,
306}; 302};
307 303
308static struct platform_device bfin_async_nand_device = { 304static struct platform_device bfin_async_nand_device = {
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index e127aedc1d7f..87595cd38afe 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
72}; 72};
73#endif 73#endif
74 74
75#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 75#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
76static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 76static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
77 .enable_dma = 0, 77 .enable_dma = 0,
78 .bits_per_word = 16, 78 .bits_per_word = 16,
@@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
111 }, 111 },
112#endif 112#endif
113 113
114#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 114#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
115 { 115 {
116 .modalias = "ad1836", 116 .modalias = "ad183x",
117 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 117 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
118 .bus_num = 0, 118 .bus_num = 0,
119 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 119 .chip_select = 4,
120 .controller_data = &ad1836_spi_chip_info, 120 .controller_data = &ad1836_spi_chip_info,
121 }, 121 },
122#endif 122#endif
@@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = {
278 }, { 278 }, {
279 .start = IRQ_PF47, 279 .start = IRQ_PF47,
280 .end = IRQ_PF47, 280 .end = IRQ_PF47,
281 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 281 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
282 }, 282 },
283}; 283};
284 284
@@ -334,7 +334,7 @@ static struct resource bfin_uart0_resources[] = {
334 }, 334 },
335}; 335};
336 336
337unsigned short bfin_uart0_peripherals[] = { 337static unsigned short bfin_uart0_peripherals[] = {
338 P_UART0_TX, P_UART0_RX, 0 338 P_UART0_TX, P_UART0_RX, 0
339}; 339};
340 340
@@ -541,7 +541,7 @@ static int __init cm_bf561_init(void)
541#endif 541#endif
542 542
543#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 543#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
544 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 544 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
545#endif 545#endif
546 return 0; 546 return 0;
547} 547}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9b93e2f95791..5067984a62e7 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -14,6 +14,7 @@
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/delay.h>
17#include <asm/dma.h> 18#include <asm/dma.h>
18#include <asm/bfin5xx_spi.h> 19#include <asm/bfin5xx_spi.h>
19#include <asm/portmux.h> 20#include <asm/portmux.h>
@@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = {
74 }, { 75 }, {
75 .start = IRQ_PF8, 76 .start = IRQ_PF8,
76 .end = IRQ_PF8, 77 .end = IRQ_PF8,
77 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
78 }, 79 },
79}; 80};
80 81
@@ -189,7 +190,7 @@ static struct resource bfin_uart0_resources[] = {
189 }, 190 },
190}; 191};
191 192
192unsigned short bfin_uart0_peripherals[] = { 193static unsigned short bfin_uart0_peripherals[] = {
193 P_UART0_TX, P_UART0_RX, 0 194 P_UART0_TX, P_UART0_RX, 0
194}; 195};
195 196
@@ -246,7 +247,15 @@ static struct mtd_partition ezkit_partitions[] = {
246 .offset = MTDPART_OFS_APPEND, 247 .offset = MTDPART_OFS_APPEND,
247 }, { 248 }, {
248 .name = "file system(nor)", 249 .name = "file system(nor)",
249 .size = MTDPART_SIZ_FULL, 250 .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
251 .offset = MTDPART_OFS_APPEND,
252 }, {
253 .name = "config(nor)",
254 .size = 0x2000 * 7,
255 .offset = MTDPART_OFS_APPEND,
256 }, {
257 .name = "u-boot env(nor)",
258 .size = 0x2000,
250 .offset = MTDPART_OFS_APPEND, 259 .offset = MTDPART_OFS_APPEND,
251 } 260 }
252}; 261};
@@ -274,8 +283,8 @@ static struct platform_device ezkit_flash_device = {
274}; 283};
275#endif 284#endif
276 285
277#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 286#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
278 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 287 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
279static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 288static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
280 .enable_dma = 0, 289 .enable_dma = 0,
281 .bits_per_word = 16, 290 .bits_per_word = 16,
@@ -328,14 +337,16 @@ static struct platform_device bfin_spi0_device = {
328#endif 337#endif
329 338
330static struct spi_board_info bfin_spi_board_info[] __initdata = { 339static struct spi_board_info bfin_spi_board_info[] __initdata = {
331#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 340#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
332 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 341 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
333 { 342 {
334 .modalias = "ad1836", 343 .modalias = "ad183x",
335 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 344 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
336 .bus_num = 0, 345 .bus_num = 0,
337 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 346 .chip_select = 4,
347 .platform_data = "ad1836", /* only includes chip name for the moment */
338 .controller_data = &ad1836_spi_chip_info, 348 .controller_data = &ad1836_spi_chip_info,
349 .mode = SPI_MODE_3,
339 }, 350 },
340#endif 351#endif
341#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 352#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -377,8 +388,8 @@ static struct platform_device bfin_device_gpiokeys = {
377#include <linux/i2c-gpio.h> 388#include <linux/i2c-gpio.h>
378 389
379static struct i2c_gpio_platform_data i2c_gpio_data = { 390static struct i2c_gpio_platform_data i2c_gpio_data = {
380 .sda_pin = 1, 391 .sda_pin = GPIO_PF1,
381 .scl_pin = 0, 392 .scl_pin = GPIO_PF0,
382 .sda_is_open_drain = 0, 393 .sda_is_open_drain = 0,
383 .scl_is_open_drain = 0, 394 .scl_is_open_drain = 0,
384 .udelay = 40, 395 .udelay = 40,
@@ -420,6 +431,30 @@ static struct platform_device bfin_dpmc = {
420 }, 431 },
421}; 432};
422 433
434#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
435static struct platform_device bfin_i2s = {
436 .name = "bfin-i2s",
437 .id = CONFIG_SND_BF5XX_SPORT_NUM,
438 /* TODO: add platform data here */
439};
440#endif
441
442#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
443static struct platform_device bfin_tdm = {
444 .name = "bfin-tdm",
445 .id = CONFIG_SND_BF5XX_SPORT_NUM,
446 /* TODO: add platform data here */
447};
448#endif
449
450#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
451static struct platform_device bfin_ac97 = {
452 .name = "bfin-ac97",
453 .id = CONFIG_SND_BF5XX_SPORT_NUM,
454 /* TODO: add platform data here */
455};
456#endif
457
423static struct platform_device *ezkit_devices[] __initdata = { 458static struct platform_device *ezkit_devices[] __initdata = {
424 459
425 &bfin_dpmc, 460 &bfin_dpmc,
@@ -467,6 +502,18 @@ static struct platform_device *ezkit_devices[] __initdata = {
467#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 502#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
468 &ezkit_flash_device, 503 &ezkit_flash_device,
469#endif 504#endif
505
506#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
507 &bfin_i2s,
508#endif
509
510#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
511 &bfin_tdm,
512#endif
513
514#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
515 &bfin_ac97,
516#endif
470}; 517};
471 518
472static int __init ezkit_init(void) 519static int __init ezkit_init(void)
@@ -484,6 +531,17 @@ static int __init ezkit_init(void)
484 SSYNC(); 531 SSYNC();
485#endif 532#endif
486 533
534#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
535 bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
536 bfin_write_FIO0_FLAG_S(1 << 15);
537 SSYNC();
538 /*
539 * This initialization lasts for approximately 4500 MCLKs.
540 * MCLK = 12.288MHz
541 */
542 udelay(400);
543#endif
544
487 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 545 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
488 return 0; 546 return 0;
489} 547}
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index d3017e53686b..bb056e60f6ed 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -72,7 +72,7 @@ static struct resource bfin_uart0_resources[] = {
72 }, 72 },
73}; 73};
74 74
75unsigned short bfin_uart0_peripherals[] = { 75static unsigned short bfin_uart0_peripherals[] = {
76 P_UART0_TX, P_UART0_RX, 0 76 P_UART0_TX, P_UART0_RX, 0
77}; 77};
78 78
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index deb2271d09a3..78ecb50bafc8 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -18,9 +18,9 @@
18#include <linux/miscdevice.h> 18#include <linux/miscdevice.h>
19#include <linux/module.h> 19#include <linux/module.h>
20 20
21#define CMD_COREB_START 2 21#define CMD_COREB_START _IO('b', 0)
22#define CMD_COREB_STOP 3 22#define CMD_COREB_STOP _IO('b', 1)
23#define CMD_COREB_RESET 4 23#define CMD_COREB_RESET _IO('b', 2)
24 24
25static long 25static long
26coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 26coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
@@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
29 29
30 switch (cmd) { 30 switch (cmd) {
31 case CMD_COREB_START: 31 case CMD_COREB_START:
32 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); 32 bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
33 break; 33 break;
34 case CMD_COREB_STOP: 34 case CMD_COREB_STOP:
35 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); 35 bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); 36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
37 break; 37 break;
38 case CMD_COREB_RESET: 38 case CMD_COREB_RESET:
@@ -51,6 +51,7 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
51static const struct file_operations coreb_fops = { 51static const struct file_operations coreb_fops = {
52 .owner = THIS_MODULE, 52 .owner = THIS_MODULE,
53 .unlocked_ioctl = coreb_ioctl, 53 .unlocked_ioctl = coreb_ioctl,
54 .llseek = noop_llseek,
54}; 55};
55 56
56static struct miscdevice coreb_dev = { 57static struct miscdevice coreb_dev = {
@@ -73,3 +74,4 @@ module_exit(bf561_coreb_exit);
73 74
74MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); 75MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
75MODULE_DESCRIPTION("BF561 Core B Support"); 76MODULE_DESCRIPTION("BF561 Core B Support");
77MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index c938c3c7355d..8ffdd6b4a242 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR, 36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR, 37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR, 38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, 43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, 44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, 45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, 46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, 47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, 48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, 49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index c95169b612dc..0123117b8ff2 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -5,28 +5,36 @@
5 * Licensed under the GPL-2 or later. 5 * Licensed under the GPL-2 or later.
6 */ 6 */
7 7
8#include <linux/smp.h>
8#include <asm/blackfin.h> 9#include <asm/blackfin.h>
9#include <asm/smp.h> 10#include <asm/cacheflush.h>
10#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 11#include <mach/pll.h>
11 12
12int hotplug_coreb; 13int hotplug_coreb;
13 14
14void platform_cpu_die(void) 15void platform_cpu_die(void)
15{ 16{
16 unsigned long iwr[2] = {0, 0}; 17 unsigned long iwr;
17 unsigned long bank = SIC_SYSIRQ(IRQ_SUPPLE_0) / 32;
18 unsigned long bit = 1 << (SIC_SYSIRQ(IRQ_SUPPLE_0) % 32);
19 18
20 hotplug_coreb = 1; 19 hotplug_coreb = 1;
21 20
22 iwr[bank] = bit; 21 /*
22 * When CoreB wakes up, the code in _coreb_trampoline_start cannot
23 * turn off the data cache. This causes the CoreB failed to boot.
24 * As a workaround, we invalidate all the data cache before sleep.
25 */
26 blackfin_invalidate_entire_dcache();
23 27
24 /* disable core timer */ 28 /* disable core timer */
25 bfin_write_TCNTL(0); 29 bfin_write_TCNTL(0);
26 30
27 /* clear ipi interrupt IRQ_SUPPLE_0 */ 31 /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
28 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1))); 32 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
29 SSYNC(); 33 SSYNC();
30 34
31 coreb_sleep(iwr[0], iwr[1], 0); 35 /* set CoreB wakeup by ipi0, iwr will be discarded */
36 bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
37 SSYNC();
38
39 coreb_die();
32} 40}
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 4c108c99cb6e..22b5ab773027 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List 14 * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -181,7 +181,11 @@
181/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 181/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
182#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) 182#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
183/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 183/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
184#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) 184/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
185 * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
186 * after the behavior and the root cause are confirmed with hardware team.
187 */
188#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
185/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 189/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
186#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) 190#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
187/* ICPLB_STATUS MMR Register May Be Corrupted */ 191/* ICPLB_STATUS MMR Register May Be Corrupted */
@@ -286,12 +290,18 @@
286#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) 290#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
287/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 291/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
288#define ANOMALY_05000443 (1) 292#define ANOMALY_05000443 (1)
293/* SCKELOW Feature Is Not Functional */
294#define ANOMALY_05000458 (1)
289/* False Hardware Error when RETI Points to Invalid Memory */ 295/* False Hardware Error when RETI Points to Invalid Memory */
290#define ANOMALY_05000461 (1) 296#define ANOMALY_05000461 (1)
297/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
298#define ANOMALY_05000462 (1)
299/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
300#define ANOMALY_05000471 (1)
291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 301/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
292#define ANOMALY_05000473 (1) 302#define ANOMALY_05000473 (1)
293/* Possible Lockup Condition whem Modifying PLL from External Memory */ 303/* Possible Lockup Condition whem Modifying PLL from External Memory */
294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 304#define ANOMALY_05000475 (1)
295/* TESTSET Instruction Cannot Be Interrupted */ 305/* TESTSET Instruction Cannot Be Interrupted */
296#define ANOMALY_05000477 (1) 306#define ANOMALY_05000477 (1)
297/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 307/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -310,12 +320,14 @@
310#define ANOMALY_05000353 (1) 320#define ANOMALY_05000353 (1)
311#define ANOMALY_05000364 (0) 321#define ANOMALY_05000364 (0)
312#define ANOMALY_05000380 (0) 322#define ANOMALY_05000380 (0)
323#define ANOMALY_05000383 (0)
313#define ANOMALY_05000386 (1) 324#define ANOMALY_05000386 (1)
314#define ANOMALY_05000389 (0) 325#define ANOMALY_05000389 (0)
315#define ANOMALY_05000400 (0) 326#define ANOMALY_05000400 (0)
316#define ANOMALY_05000430 (0) 327#define ANOMALY_05000430 (0)
317#define ANOMALY_05000432 (0) 328#define ANOMALY_05000432 (0)
318#define ANOMALY_05000435 (0) 329#define ANOMALY_05000435 (0)
330#define ANOMALY_05000440 (0)
319#define ANOMALY_05000447 (0) 331#define ANOMALY_05000447 (0)
320#define ANOMALY_05000448 (0) 332#define ANOMALY_05000448 (0)
321#define ANOMALY_05000456 (0) 333#define ANOMALY_05000456 (0)
@@ -323,6 +335,7 @@
323#define ANOMALY_05000465 (0) 335#define ANOMALY_05000465 (0)
324#define ANOMALY_05000467 (0) 336#define ANOMALY_05000467 (0)
325#define ANOMALY_05000474 (0) 337#define ANOMALY_05000474 (0)
338#define ANOMALY_05000480 (0)
326#define ANOMALY_05000485 (0) 339#define ANOMALY_05000485 (0)
327 340
328#endif 341#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index e33e158bc16d..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Copyright 2006-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#include <linux/serial.h>
8#include <asm/dma.h>
9#include <asm/portmux.h>
10
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN
40# define CONFIG_UART0_CTS_PIN -1
41# endif
42# ifndef CONFIG_UART0_RTS_PIN
43# define CONFIG_UART0_RTS_PIN -1
44# endif
45#endif
46
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res {
93 unsigned long uart_base_addr;
94 int uart_irq;
95 int uart_status_irq;
96#ifdef CONFIG_SERIAL_BFIN_DMA
97 unsigned int uart_tx_dma_channel;
98 unsigned int uart_rx_dma_channel;
99#endif
100#ifdef CONFIG_SERIAL_BFIN_CTSRTS
101 int uart_cts_pin;
102 int uart_rts_pin;
103#endif
104};
105
106struct bfin_serial_res bfin_serial_resource[] = {
107 {
108 0xFFC00400,
109 IRQ_UART_RX,
110 IRQ_UART_ERROR,
111#ifdef CONFIG_SERIAL_BFIN_DMA
112 CH_UART_TX,
113 CH_UART_RX,
114#endif
115#ifdef CONFIG_SERIAL_BFIN_CTSRTS
116 CONFIG_UART0_CTS_PIN,
117 CONFIG_UART0_RTS_PIN,
118#endif
119 }
120};
121
122#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 67d6bdcd3fa8..dc470534c085 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -10,11 +10,14 @@
10#define BF561_FAMILY 10#define BF561_FAMILY
11 11
12#include "bf561.h" 12#include "bf561.h"
13#include "defBF561.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
16#if !defined(__ASSEMBLY__) 15#include <asm/def_LPBlackfin.h>
17#include "cdefBF561.h" 16#include "defBF561.h"
17
18#ifndef __ASSEMBLY__
19# include <asm/cdef_LPBlackfin.h>
20# include "cdefBF561.h"
18#endif 21#endif
19 22
20#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() 23#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
@@ -24,43 +27,15 @@
24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 27#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 28#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
26 29
27#define SIC_IWR0 SICA_IWR0 30/* Weird muxer funcs which pick SIC regs from IMASK base */
28#define SIC_IWR1 SICA_IWR1 31#define __SIC_MUX(base, x) ((base) + ((x) << 2))
29#define SIC_IAR0 SICA_IAR0 32#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
30#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 33#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
31#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 34#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
32#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 35#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
33#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 36#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
34 37#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
35#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 38#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 39#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
38#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
39#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
40#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
41
42#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
44#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
46#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
47#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
48#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
49#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
50
51#define BFIN_UART_NR_PORTS 1
52
53#define OFFSET_THR 0x00 /* Transmit Holding register */
54#define OFFSET_RBR 0x00 /* Receive Buffer register */
55#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
56#define OFFSET_IER 0x04 /* Interrupt Enable Register */
57#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
58#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
59#define OFFSET_LCR 0x0C /* Line Control Register */
60#define OFFSET_MCR 0x10 /* Modem Control Register */
61#define OFFSET_LSR 0x14 /* Line Status Register */
62#define OFFSET_MSR 0x18 /* Modem Status Register */
63#define OFFSET_SCR 0x1C /* SCR Scratch Register */
64#define OFFSET_GCTL 0x24 /* Global Control Register */
65 40
66#endif /* _MACH_BLACKFIN_H_ */ 41#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 81ecdb71c6af..753331597207 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF561_H 7#ifndef _CDEF_BF561_H
8#define _CDEF_BF561_H 8#define _CDEF_BF561_H
9 9
10#include <asm/blackfin.h>
11
12/* include all Core registers and bit definitions */
13#include "defBF561.h"
14
15/*include core specific register pointer definitions*/
16#include <asm/cdef_LPBlackfin.h>
17
18/*********************************************************************************** */ 10/*********************************************************************************** */
19/* System MMR Register Map */ 11/* System MMR Register Map */
20/*********************************************************************************** */ 12/*********************************************************************************** */
@@ -30,49 +22,41 @@
30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 22#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
31#define bfin_read_CHIPID() bfin_read32(CHIPID) 23#define bfin_read_CHIPID() bfin_read32(CHIPID)
32 24
33/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
34#define bfin_read_SWRST() bfin_read_SICA_SWRST()
35#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
36#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
37#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
38
39/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 25/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
40#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 26#define bfin_read_SWRST() bfin_read16(SWRST)
41#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 27#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
42#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) 28#define bfin_read_SYSCR() bfin_read16(SYSCR)
43#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) 29#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
44#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) 30#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
45#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) 31#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
46#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) 32#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
47#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) 33#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
48#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) 34#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
49#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) 35#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
50#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) 36#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
51#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) 37#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
52#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) 38#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
53#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) 39#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
54#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) 40#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
55#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) 41#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
56#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) 42#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
57#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) 43#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
58#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) 44#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
59#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) 45#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
60#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) 46#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
61#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) 47#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
62#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) 48#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
63#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) 49#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
64#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) 50#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
65#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) 51#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
66#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) 52#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
67#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) 53#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
68#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) 54#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
69#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) 55#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
70#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) 56#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
71#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) 57#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
72#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) 58#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
73#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) 59#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
74#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
75#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
76 60
77/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 61/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
78#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) 62#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
@@ -531,14 +515,14 @@
531#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) 515#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
532#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) 516#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
533/*DMA traffic control registers */ 517/*DMA traffic control registers */
534#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) 518#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
535#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) 519#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
536#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) 520#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
537#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) 521#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
538#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) 522#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
539#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) 523#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
540#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) 524#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
541#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) 525#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
542/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 526/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
543#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) 527#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
544#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) 528#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
@@ -853,110 +837,110 @@
853#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) 837#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
854#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) 838#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
855/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 839/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
856#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) 840#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
857#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) 841#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
858#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) 842#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
859#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) 843#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
860#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) 844#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
861#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) 845#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
862#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) 846#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
863#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) 847#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
864#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) 848#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
865#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) 849#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
866#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) 850#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
867#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) 851#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
868#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) 852#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
869#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) 853#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
870#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) 854#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
871#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) 855#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
872#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) 856#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
873#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) 857#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
874#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) 858#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
875#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) 859#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
876#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) 860#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
877#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) 861#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
878#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) 862#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
879#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) 863#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
880#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) 864#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
881#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) 865#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
882#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) 866#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
883#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) 867#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
884#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) 868#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
885#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) 869#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
886#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) 870#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
887#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) 871#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
888#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) 872#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
889#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) 873#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
890#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) 874#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
891#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) 875#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
892#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) 876#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
893#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) 877#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
894#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) 878#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
895#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) 879#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
896#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) 880#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
897#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) 881#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
898#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) 882#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
899#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) 883#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
900#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) 884#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
901#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) 885#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
902#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) 886#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
903#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) 887#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
904#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) 888#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
905#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) 889#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
906#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) 890#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
907#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) 891#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
908#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) 892#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
909#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) 893#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
910#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) 894#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
911#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) 895#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
912#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) 896#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
913#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) 897#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
914#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) 898#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
915#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) 899#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
916#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) 900#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
917#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) 901#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
918#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) 902#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
919#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) 903#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
920#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) 904#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
921#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) 905#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
922#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) 906#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
923#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) 907#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
924#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) 908#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
925#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) 909#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
926#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) 910#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
927#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) 911#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
928#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) 912#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
929#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) 913#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
930#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) 914#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
931#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) 915#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
932#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) 916#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
933#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) 917#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
934#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) 918#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
935#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) 919#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
936#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) 920#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
937#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) 921#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
938#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) 922#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
939#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) 923#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
940#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) 924#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
941#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) 925#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
942#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) 926#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
943#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) 927#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
944#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) 928#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
945#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) 929#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
946#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) 930#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
947#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) 931#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
948#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) 932#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
949#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) 933#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
950#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) 934#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
951#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) 935#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
952#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) 936#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
953#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) 937#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
954#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 938#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
955#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) 939#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
956#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) 940#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
957#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) 941#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
958#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) 942#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
959#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) 943#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
960/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 944/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
961#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) 945#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
962#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) 946#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
@@ -1271,110 +1255,110 @@
1271#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) 1255#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1272#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) 1256#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1273/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 1257/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1274#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) 1258#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
1275#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) 1259#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
1276#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) 1260#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
1277#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) 1261#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
1278#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) 1262#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
1279#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) 1263#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
1280#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) 1264#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
1281#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) 1265#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
1282#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) 1266#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
1283#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) 1267#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
1284#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) 1268#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
1285#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) 1269#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
1286#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) 1270#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
1287#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) 1271#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
1288#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) 1272#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
1289#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) 1273#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
1290#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) 1274#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
1291#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) 1275#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
1292#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) 1276#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
1293#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) 1277#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
1294#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) 1278#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
1295#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) 1279#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
1296#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) 1280#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
1297#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) 1281#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
1298#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) 1282#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
1299#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) 1283#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
1300#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) 1284#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
1301#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) 1285#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
1302#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) 1286#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
1303#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) 1287#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
1304#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) 1288#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
1305#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) 1289#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
1306#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) 1290#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
1307#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) 1291#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
1308#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) 1292#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
1309#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) 1293#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
1310#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) 1294#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
1311#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) 1295#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
1312#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) 1296#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
1313#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) 1297#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
1314#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) 1298#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
1315#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) 1299#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
1316#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) 1300#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
1317#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) 1301#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
1318#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) 1302#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
1319#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) 1303#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
1320#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) 1304#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
1321#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) 1305#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
1322#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) 1306#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
1323#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) 1307#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
1324#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) 1308#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
1325#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) 1309#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
1326#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) 1310#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
1327#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) 1311#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
1328#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) 1312#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
1329#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) 1313#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
1330#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) 1314#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
1331#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) 1315#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
1332#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) 1316#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
1333#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) 1317#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
1334#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) 1318#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
1335#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) 1319#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
1336#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) 1320#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
1337#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) 1321#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
1338#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) 1322#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
1339#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) 1323#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
1340#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) 1324#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
1341#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) 1325#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
1342#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) 1326#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
1343#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) 1327#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
1344#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) 1328#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
1345#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) 1329#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
1346#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) 1330#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
1347#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) 1331#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
1348#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) 1332#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
1349#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) 1333#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
1350#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) 1334#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
1351#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) 1335#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
1352#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) 1336#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
1353#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) 1337#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
1354#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) 1338#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
1355#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) 1339#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
1356#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) 1340#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
1357#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) 1341#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
1358#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) 1342#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
1359#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) 1343#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
1360#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) 1344#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
1361#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) 1345#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
1362#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) 1346#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
1363#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) 1347#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
1364#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) 1348#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
1365#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) 1349#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
1366#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) 1350#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
1367#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) 1351#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
1368#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) 1352#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
1369#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) 1353#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
1370#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) 1354#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
1371#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) 1355#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
1372#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) 1356#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
1373#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) 1357#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
1374#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) 1358#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
1375#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) 1359#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
1376#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) 1360#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
1377#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) 1361#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
1378/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 1362/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1379#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) 1363#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1380#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) 1364#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
@@ -1473,115 +1457,4 @@
1473#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) 1457#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1474#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) 1458#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1475 1459
1476#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1477#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1478#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1479#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1480#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1481#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1482#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1483#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1484#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1485#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1486#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1487#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1488#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1489#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1490#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1491#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1492#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1493#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1494#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1495#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1496#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1497#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1498#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1499#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1500#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1501#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1502#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1503#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1504
1505#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG()
1506#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
1507#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS()
1508#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
1509#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY()
1510#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
1511#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY()
1512#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
1513#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT()
1514#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
1515#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT()
1516#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
1517#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR()
1518#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
1519#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG()
1520#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
1521#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS()
1522#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
1523#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY()
1524#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
1525#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY()
1526#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
1527#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT()
1528#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
1529#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT()
1530#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
1531#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR()
1532#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
1533
1534/* These need to be last due to the cdef/linux inter-dependencies */
1535#include <asm/irq.h>
1536
1537/* Writing to PLL_CTL initiates a PLL relock sequence. */
1538static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1539{
1540 unsigned long flags, iwr0, iwr1;
1541
1542 if (val == bfin_read_PLL_CTL())
1543 return;
1544
1545 local_irq_save_hw(flags);
1546 /* Enable the PLL Wakeup bit in SIC IWR */
1547 iwr0 = bfin_read32(SICA_IWR0);
1548 iwr1 = bfin_read32(SICA_IWR1);
1549 /* Only allow PPL Wakeup) */
1550 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1551 bfin_write32(SICA_IWR1, 0);
1552
1553 bfin_write16(PLL_CTL, val);
1554 SSYNC();
1555 asm("IDLE;");
1556
1557 bfin_write32(SICA_IWR0, iwr0);
1558 bfin_write32(SICA_IWR1, iwr1);
1559 local_irq_restore_hw(flags);
1560}
1561
1562/* Writing to VR_CTL initiates a PLL relock sequence. */
1563static __inline__ void bfin_write_VR_CTL(unsigned int val)
1564{
1565 unsigned long flags, iwr0, iwr1;
1566
1567 if (val == bfin_read_VR_CTL())
1568 return;
1569
1570 local_irq_save_hw(flags);
1571 /* Enable the PLL Wakeup bit in SIC IWR */
1572 iwr0 = bfin_read32(SICA_IWR0);
1573 iwr1 = bfin_read32(SICA_IWR1);
1574 /* Only allow PPL Wakeup) */
1575 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1576 bfin_write32(SICA_IWR1, 0);
1577
1578 bfin_write16(VR_CTL, val);
1579 SSYNC();
1580 asm("IDLE;");
1581
1582 bfin_write32(SICA_IWR0, iwr0);
1583 bfin_write32(SICA_IWR1, iwr1);
1584 local_irq_restore_hw(flags);
1585}
1586
1587#endif /* _CDEF_BF561_H */ 1460#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 2674f0097576..71e805ea74e5 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,18 +1,11 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF561_H 7#ifndef _DEF_BF561_H
8#define _DEF_BF561_H 8#define _DEF_BF561_H
9/*
10#if !defined(__ADSPBF561__)
11#warning defBF561.h should only be included for BF561 chip.
12#endif
13*/
14/* include all Core registers and bit definitions */
15#include <asm/def_LPBlackfin.h>
16 9
17/*********************************************************************************** */ 10/*********************************************************************************** */
18/* System MMR Register Map */ 11/* System MMR Register Map */
@@ -28,32 +21,29 @@
28#define CHIPID 0xFFC00014 /* Chip ID Register */ 21#define CHIPID 0xFFC00014 /* Chip ID Register */
29 22
30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 23/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
31#define SWRST SICA_SWRST
32#define SYSCR SICA_SYSCR
33#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) 24#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
34#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) 25#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
35#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) 26#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
36#define RESET_SOFTWARE (SWRST_OCCURRED) 27#define RESET_SOFTWARE (SWRST_OCCURRED)
37 28
38/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 29/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
39#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 30#define SWRST 0xFFC00100 /* Software Reset register */
40#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 31#define SYSCR 0xFFC00104 /* System Reset Configuration register */
41#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ 32#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
42#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ 33#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
43#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ 34#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
44#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ 35#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
45#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ 36#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
46#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ 37#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
47#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ 38#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
48#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ 39#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
49#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ 40#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
50#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ 41#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
51#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ 42#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
52#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ 43#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
53#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ 44#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
54#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ 45#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
55#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ 46#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
56#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
57 47
58/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 48/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
59#define SICB_SWRST 0xFFC01100 /* reserved */ 49#define SICB_SWRST 0xFFC01100 /* reserved */
@@ -314,10 +304,10 @@
314#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ 304#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
315 305
316/*DMA traffic control registers */ 306/*DMA traffic control registers */
317#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ 307#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
318#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ 308#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
319#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ 309#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
320#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ 310#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
321 311
322/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 312/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
323#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ 313#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
@@ -489,61 +479,61 @@
489#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ 479#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
490 480
491/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 481/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
492#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ 482#define MDMA_D2_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
493#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ 483#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
494#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ 484#define MDMA_D2_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
495#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ 485#define MDMA_D2_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
496#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ 486#define MDMA_D2_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
497#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ 487#define MDMA_D2_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
498#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ 488#define MDMA_D2_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
499#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ 489#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
500#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ 490#define MDMA_D2_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
501#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ 491#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
502#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ 492#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
503#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ 493#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
504#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ 494#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
505 495
506#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ 496#define MDMA_S2_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
507#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ 497#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
508#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ 498#define MDMA_S2_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
509#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ 499#define MDMA_S2_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
510#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ 500#define MDMA_S2_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
511#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ 501#define MDMA_S2_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
512#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ 502#define MDMA_S2_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
513#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ 503#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
514#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ 504#define MDMA_S2_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
515#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ 505#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
516#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ 506#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
517#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ 507#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
518#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ 508#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
519 509
520#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ 510#define MDMA_D3_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
521#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ 511#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
522#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ 512#define MDMA_D3_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
523#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ 513#define MDMA_D3_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
524#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ 514#define MDMA_D3_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
525#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ 515#define MDMA_D3_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
526#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ 516#define MDMA_D3_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
527#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ 517#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
528#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ 518#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
529#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ 519#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
530#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ 520#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
531#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ 521#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
532#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ 522#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
533 523
534#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ 524#define MDMA_S3_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
535#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ 525#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
536#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ 526#define MDMA_S3_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
537#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ 527#define MDMA_S3_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
538#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ 528#define MDMA_S3_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
539#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ 529#define MDMA_S3_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
540#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ 530#define MDMA_S3_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
541#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ 531#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
542#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ 532#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
543#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ 533#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
544#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ 534#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
545#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ 535#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
546#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ 536#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
547 537
548/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 538/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
549#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ 539#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
@@ -715,117 +705,61 @@
715#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ 705#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
716 706
717/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 707/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
718#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ 708#define MDMA_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
719#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ 709#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
720#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ 710#define MDMA_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
721#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ 711#define MDMA_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
722#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ 712#define MDMA_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
723#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ 713#define MDMA_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
724#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ 714#define MDMA_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
725#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ 715#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
726#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ 716#define MDMA_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
727#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ 717#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
728#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ 718#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
729#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ 719#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
730#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ 720#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
731 721
732#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ 722#define MDMA_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
733#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ 723#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
734#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ 724#define MDMA_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
735#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ 725#define MDMA_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
736#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ 726#define MDMA_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
737#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ 727#define MDMA_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
738#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ 728#define MDMA_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
739#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ 729#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
740#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ 730#define MDMA_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
741#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ 731#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
742#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ 732#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
743#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ 733#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
744#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ 734#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
745 735
746#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ 736#define MDMA_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
747#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ 737#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
748#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ 738#define MDMA_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
749#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ 739#define MDMA_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
750#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ 740#define MDMA_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
751#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ 741#define MDMA_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
752#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ 742#define MDMA_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
753#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ 743#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
754#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ 744#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
755#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ 745#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
756#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ 746#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
757#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ 747#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
758#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ 748#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
759 749
760#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ 750#define MDMA_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
761#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ 751#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
762#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ 752#define MDMA_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
763#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ 753#define MDMA_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
764#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ 754#define MDMA_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
765#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ 755#define MDMA_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
766#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ 756#define MDMA_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
767#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ 757#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
768#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ 758#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
769#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ 759#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
770#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ 760#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
771#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ 761#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
772#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ 762#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
773
774#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
775#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
776#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
777#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
778#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
779#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
780#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
781#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
782#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
783#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
784#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
785#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
786#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
787
788#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
789#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
790#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
791#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
792#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
793#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
794#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
795#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
796#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
797#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
798#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
799#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
800#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
801
802#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
803#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
804#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
805#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
806#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
807#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
808#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
809#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
810#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
811#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
812#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
813#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
814#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
815
816#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
817#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
818#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
819#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
820#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
821#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
822#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
823#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
824#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
825#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
826#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
827#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
828#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
829 763
830/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 764/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
831#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ 765#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
@@ -930,83 +864,6 @@
930#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 864#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
931#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 865#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
932 866
933/* ***************************** UART CONTROLLER MASKS ********************** */
934
935/* UART_LCR Register */
936
937#define DLAB 0x80
938#define SB 0x40
939#define STP 0x20
940#define EPS 0x10
941#define PEN 0x08
942#define STB 0x04
943#define WLS(x) ((x-5) & 0x03)
944
945#define DLAB_P 0x07
946#define SB_P 0x06
947#define STP_P 0x05
948#define EPS_P 0x04
949#define PEN_P 0x03
950#define STB_P 0x02
951#define WLS_P1 0x01
952#define WLS_P0 0x00
953
954/* UART_MCR Register */
955#define LOOP_ENA 0x10
956#define LOOP_ENA_P 0x04
957
958/* UART_LSR Register */
959#define TEMT 0x40
960#define THRE 0x20
961#define BI 0x10
962#define FE 0x08
963#define PE 0x04
964#define OE 0x02
965#define DR 0x01
966
967#define TEMP_P 0x06
968#define THRE_P 0x05
969#define BI_P 0x04
970#define FE_P 0x03
971#define PE_P 0x02
972#define OE_P 0x01
973#define DR_P 0x00
974
975/* UART_IER Register */
976#define ELSI 0x04
977#define ETBEI 0x02
978#define ERBFI 0x01
979
980#define ELSI_P 0x02
981#define ETBEI_P 0x01
982#define ERBFI_P 0x00
983
984/* UART_IIR Register */
985#define STATUS(x) ((x << 1) & 0x06)
986#define NINT 0x01
987#define STATUS_P1 0x02
988#define STATUS_P0 0x01
989#define NINT_P 0x00
990#define IIR_TX_READY 0x02 /* UART_THR empty */
991#define IIR_RX_READY 0x04 /* Receive data ready */
992#define IIR_LINE_CHANGE 0x06 /* Receive line status */
993#define IIR_STATUS 0x06
994
995/* UART_GCTL Register */
996#define FFE 0x20
997#define FPE 0x10
998#define RPOLC 0x08
999#define TPOLC 0x04
1000#define IREN 0x02
1001#define UCEN 0x01
1002
1003#define FFE_P 0x05
1004#define FPE_P 0x04
1005#define RPOLC_P 0x03
1006#define TPOLC_P 0x02
1007#define IREN_P 0x01
1008#define UCEN_P 0x00
1009
1010/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 867/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1011 868
1012/* PPI_CONTROL Masks */ 869/* PPI_CONTROL Masks */
@@ -1233,101 +1090,6 @@
1233#define ERR_TYP_P0 0x0E 1090#define ERR_TYP_P0 0x0E
1234#define ERR_TYP_P1 0x0F 1091#define ERR_TYP_P1 0x0F
1235 1092
1236/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
1237
1238/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1239#define PF0 0x0001
1240#define PF1 0x0002
1241#define PF2 0x0004
1242#define PF3 0x0008
1243#define PF4 0x0010
1244#define PF5 0x0020
1245#define PF6 0x0040
1246#define PF7 0x0080
1247#define PF8 0x0100
1248#define PF9 0x0200
1249#define PF10 0x0400
1250#define PF11 0x0800
1251#define PF12 0x1000
1252#define PF13 0x2000
1253#define PF14 0x4000
1254#define PF15 0x8000
1255
1256/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
1257#define PF0_P 0
1258#define PF1_P 1
1259#define PF2_P 2
1260#define PF3_P 3
1261#define PF4_P 4
1262#define PF5_P 5
1263#define PF6_P 6
1264#define PF7_P 7
1265#define PF8_P 8
1266#define PF9_P 9
1267#define PF10_P 10
1268#define PF11_P 11
1269#define PF12_P 12
1270#define PF13_P 13
1271#define PF14_P 14
1272#define PF15_P 15
1273
1274/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1275
1276/* SPI_CTL Masks */
1277#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1278#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1279#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1280#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1281#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1282#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1283#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1284#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1285#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1286#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1287#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1288#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1289
1290/* SPI_FLG Masks */
1291#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1292#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1293#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1294#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1295#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1296#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1297#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1298#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1299#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1300#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1301#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1302#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1303#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1304#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1305
1306/* SPI_FLG Bit Positions */
1307#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1308#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1309#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1310#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1311#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1312#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1313#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1314#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1315#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1316#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1317#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1318#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1319#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1320#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1321
1322/* SPI_STAT Masks */
1323#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1324#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1325#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1326#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1327#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1328#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1329#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1330
1331/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1093/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1332 1094
1333/* AMGCTL Masks */ 1095/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 4f8aa5d08802..57d5eab59faf 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -62,4 +62,6 @@
62#define PORT_FIO1 GPIO_16 62#define PORT_FIO1 GPIO_16
63#define PORT_FIO2 GPIO_32 63#define PORT_FIO2 GPIO_32
64 64
65#include <mach-common/ports-f.h>
66
65#endif /* _MACH_GPIO_H_ */ 67#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index c95566ade51b..d6998520f70f 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -7,212 +7,98 @@
7#ifndef _BF561_IRQ_H_ 7#ifndef _BF561_IRQ_H_
8#define _BF561_IRQ_H_ 8#define _BF561_IRQ_H_
9 9
10/*********************************************************************** 10#include <mach-common/irq.h>
11 * Interrupt source definitions: 11
12 Event Source Core Event Name IRQ No 12#define NR_PERI_INTS (2 * 32)
13 (highest priority) 13
14 Emulation Events EMU 0 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 Reset RST 1 15#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
16 NMI NMI 2 16#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
17 Exception EVX 3 17#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
18 Reserved -- 4 18#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
19 Hardware Error IVHW 5 19#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
20 Core Timer IVTMR 6 * 20#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
21 21#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
22 PLL Wakeup Interrupt IVG7 7 22#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
23 DMA1 Error (generic) IVG7 8 23#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
24 DMA2 Error (generic) IVG7 9 24#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
25 IMDMA Error (generic) IVG7 10 25#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
26 PPI1 Error Interrupt IVG7 11 26#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
27 PPI2 Error Interrupt IVG7 12 27#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
28 SPORT0 Error Interrupt IVG7 13 28#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
29 SPORT1 Error Interrupt IVG7 14 29#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
30 SPI Error Interrupt IVG7 15 30#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
31 UART Error Interrupt IVG7 16 31#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
32 Reserved Interrupt IVG7 17 32#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
33 33#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
34 DMA1 0 Interrupt(PPI1) IVG8 18 34#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
35 DMA1 1 Interrupt(PPI2) IVG8 19 35#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
36 DMA1 2 Interrupt IVG8 20 36#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
37 DMA1 3 Interrupt IVG8 21 37#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
38 DMA1 4 Interrupt IVG8 22 38#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
39 DMA1 5 Interrupt IVG8 23 39#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
40 DMA1 6 Interrupt IVG8 24 40#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
41 DMA1 7 Interrupt IVG8 25 41#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
42 DMA1 8 Interrupt IVG8 26 42#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
43 DMA1 9 Interrupt IVG8 27 43#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
44 DMA1 10 Interrupt IVG8 28 44#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
45 DMA1 11 Interrupt IVG8 29 45#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
46 46#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
47 DMA2 0 (SPORT0 RX) IVG9 30 47#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
48 DMA2 1 (SPORT0 TX) IVG9 31 48#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
49 DMA2 2 (SPORT1 RX) IVG9 32 49#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
50 DMA2 3 (SPORT2 TX) IVG9 33 50#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
51 DMA2 4 (SPI) IVG9 34 51#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
52 DMA2 5 (UART RX) IVG9 35 52#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
53 DMA2 6 (UART TX) IVG9 36 53#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
54 DMA2 7 Interrupt IVG9 37 54#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
55 DMA2 8 Interrupt IVG9 38 55#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
56 DMA2 9 Interrupt IVG9 39 56#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
57 DMA2 10 Interrupt IVG9 40 57#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
58 DMA2 11 Interrupt IVG9 41 58#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
59 59#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
60 TIMER 0 Interrupt IVG10 42 60#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
61 TIMER 1 Interrupt IVG10 43 61#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
62 TIMER 2 Interrupt IVG10 44 62#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
63 TIMER 3 Interrupt IVG10 45 63#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
64 TIMER 4 Interrupt IVG10 46 64#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
65 TIMER 5 Interrupt IVG10 47 65#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
66 TIMER 6 Interrupt IVG10 48 66#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
67 TIMER 7 Interrupt IVG10 49 67#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
68 TIMER 8 Interrupt IVG10 50 68#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
69 TIMER 9 Interrupt IVG10 51 69#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
70 TIMER 10 Interrupt IVG10 52 70#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
71 TIMER 11 Interrupt IVG10 53 71#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
72 72#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
73 Programmable Flags0 A (8) IVG11 54 73#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
74 Programmable Flags0 B (8) IVG11 55 74#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
75 Programmable Flags1 A (8) IVG11 56 75#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
76 Programmable Flags1 B (8) IVG11 57 76#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
77 Programmable Flags2 A (8) IVG11 58 77#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
78 Programmable Flags2 B (8) IVG11 59 78#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
79 79#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
80 MDMA1 0 write/read INT IVG8 60 80#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
81 MDMA1 1 write/read INT IVG8 61 81#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
82 82#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
83 MDMA2 0 write/read INT IVG9 62
84 MDMA2 1 write/read INT IVG9 63
85
86 IMDMA 0 write/read INT IVG12 64
87 IMDMA 1 write/read INT IVG12 65
88
89 Watch Dog Timer IVG13 66
90
91 Reserved interrupt IVG7 67
92 Reserved interrupt IVG7 68
93 Supplemental interrupt 0 IVG7 69
94 supplemental interrupt 1 IVG7 70
95
96 Softirq IVG14
97 System Call --
98 (lowest priority) IVG15
99
100 **********************************************************************/
101
102#define SYS_IRQS 71
103#define NR_PERI_INTS 64
104
105/*
106 * The ABSTRACT IRQ definitions
107 * the first seven of the following are fixed,
108 * the rest you change if you need to.
109 */
110/* IVG 0-6*/
111#define IRQ_EMU 0 /* Emulation */
112#define IRQ_RST 1 /* Reset */
113#define IRQ_NMI 2 /* Non Maskable Interrupt */
114#define IRQ_EVX 3 /* Exception */
115#define IRQ_UNUSED 4 /* Reserved interrupt */
116#define IRQ_HWERR 5 /* Hardware Error */
117#define IRQ_CORETMR 6 /* Core timer */
118
119#define IVG_BASE 7
120/* IVG 7 */
121#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
122#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
123#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
124#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
125#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
126#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
127#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
128#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
129#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
130#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
131#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
132#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
133#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
134/* IVG 8 */
135#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
136#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
137#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
138#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
139#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
140#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
141#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
142#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
143#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
144#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
145#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
146#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
147#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
148#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
149#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
150/* IVG 9 */
151#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
152#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
153#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
154#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
155#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
156#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
157#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
158#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
159#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
160#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
161#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
162#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
163#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
164#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
165#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
166#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
167#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
168#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
169#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
170/* IVG 10 */
171#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
172#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
173#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
174#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
175#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
176#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
177#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
178#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
179#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
180#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
181#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
182#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
183/* IVG 11 */
184#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
185#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
186#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
187#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
188#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
189#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
190#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
191#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
192/* IVG 8 */
193#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
194#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
195#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 83#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
196#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ 84#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
197#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ 85#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
198#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 86#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
199/* IVG 9 */ 87#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
200#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
201#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 88#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
202#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ 89#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
203#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 90#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
204/* IVG 12 */ 91#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
205#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
206#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 92#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
207#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ 93#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
208#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 94#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
209/* IVG 13 */ 95#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
210#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ 96#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
211/* IVG 7 */ 97#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
212#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ 98#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
213#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ 99#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
214#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 100
215#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 101#define SYS_IRQS 71
216 102
217#define IRQ_PF0 73 103#define IRQ_PF0 73
218#define IRQ_PF1 74 104#define IRQ_PF1 74
@@ -266,158 +152,85 @@
266#define GPIO_IRQ_BASE IRQ_PF0 152#define GPIO_IRQ_BASE IRQ_PF0
267 153
268#define NR_MACH_IRQS (IRQ_PF47 + 1) 154#define NR_MACH_IRQS (IRQ_PF47 + 1)
269#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
270
271#define IVG7 7
272#define IVG8 8
273#define IVG9 9
274#define IVG10 10
275#define IVG11 11
276#define IVG12 12
277#define IVG13 13
278#define IVG14 14
279#define IVG15 15
280
281/*
282 * DEFAULT PRIORITIES:
283 */
284
285#define CONFIG_DEF_PLL_WAKEUP 7
286#define CONFIG_DEF_DMA1_ERROR 7
287#define CONFIG_DEF_DMA2_ERROR 7
288#define CONFIG_DEF_IMDMA_ERROR 7
289#define CONFIG_DEF_PPI1_ERROR 7
290#define CONFIG_DEF_PPI2_ERROR 7
291#define CONFIG_DEF_SPORT0_ERROR 7
292#define CONFIG_DEF_SPORT1_ERROR 7
293#define CONFIG_DEF_SPI_ERROR 7
294#define CONFIG_DEF_UART_ERROR 7
295#define CONFIG_DEF_RESERVED_ERROR 7
296#define CONFIG_DEF_DMA1_0 8
297#define CONFIG_DEF_DMA1_1 8
298#define CONFIG_DEF_DMA1_2 8
299#define CONFIG_DEF_DMA1_3 8
300#define CONFIG_DEF_DMA1_4 8
301#define CONFIG_DEF_DMA1_5 8
302#define CONFIG_DEF_DMA1_6 8
303#define CONFIG_DEF_DMA1_7 8
304#define CONFIG_DEF_DMA1_8 8
305#define CONFIG_DEF_DMA1_9 8
306#define CONFIG_DEF_DMA1_10 8
307#define CONFIG_DEF_DMA1_11 8
308#define CONFIG_DEF_DMA2_0 9
309#define CONFIG_DEF_DMA2_1 9
310#define CONFIG_DEF_DMA2_2 9
311#define CONFIG_DEF_DMA2_3 9
312#define CONFIG_DEF_DMA2_4 9
313#define CONFIG_DEF_DMA2_5 9
314#define CONFIG_DEF_DMA2_6 9
315#define CONFIG_DEF_DMA2_7 9
316#define CONFIG_DEF_DMA2_8 9
317#define CONFIG_DEF_DMA2_9 9
318#define CONFIG_DEF_DMA2_10 9
319#define CONFIG_DEF_DMA2_11 9
320#define CONFIG_DEF_TIMER0 10
321#define CONFIG_DEF_TIMER1 10
322#define CONFIG_DEF_TIMER2 10
323#define CONFIG_DEF_TIMER3 10
324#define CONFIG_DEF_TIMER4 10
325#define CONFIG_DEF_TIMER5 10
326#define CONFIG_DEF_TIMER6 10
327#define CONFIG_DEF_TIMER7 10
328#define CONFIG_DEF_TIMER8 10
329#define CONFIG_DEF_TIMER9 10
330#define CONFIG_DEF_TIMER10 10
331#define CONFIG_DEF_TIMER11 10
332#define CONFIG_DEF_PROG0_INTA 11
333#define CONFIG_DEF_PROG0_INTB 11
334#define CONFIG_DEF_PROG1_INTA 11
335#define CONFIG_DEF_PROG1_INTB 11
336#define CONFIG_DEF_PROG2_INTA 11
337#define CONFIG_DEF_PROG2_INTB 11
338#define CONFIG_DEF_DMA1_WRRD0 8
339#define CONFIG_DEF_DMA1_WRRD1 8
340#define CONFIG_DEF_DMA2_WRRD0 9
341#define CONFIG_DEF_DMA2_WRRD1 9
342#define CONFIG_DEF_IMDMA_WRRD0 12
343#define CONFIG_DEF_IMDMA_WRRD1 12
344#define CONFIG_DEF_WATCH 13
345#define CONFIG_DEF_RESERVED_1 7
346#define CONFIG_DEF_RESERVED_2 7
347#define CONFIG_DEF_SUPPLE_0 7
348#define CONFIG_DEF_SUPPLE_1 7
349 155
350/* IAR0 BIT FIELDS */ 156/* IAR0 BIT FIELDS */
351#define IRQ_PLL_WAKEUP_POS 0 157#define IRQ_PLL_WAKEUP_POS 0
352#define IRQ_DMA1_ERROR_POS 4 158#define IRQ_DMA1_ERROR_POS 4
353#define IRQ_DMA2_ERROR_POS 8 159#define IRQ_DMA2_ERROR_POS 8
354#define IRQ_IMDMA_ERROR_POS 12 160#define IRQ_IMDMA_ERROR_POS 12
355#define IRQ_PPI0_ERROR_POS 16 161#define IRQ_PPI0_ERROR_POS 16
356#define IRQ_PPI1_ERROR_POS 20 162#define IRQ_PPI1_ERROR_POS 20
357#define IRQ_SPORT0_ERROR_POS 24 163#define IRQ_SPORT0_ERROR_POS 24
358#define IRQ_SPORT1_ERROR_POS 28 164#define IRQ_SPORT1_ERROR_POS 28
165
359/* IAR1 BIT FIELDS */ 166/* IAR1 BIT FIELDS */
360#define IRQ_SPI_ERROR_POS 0 167#define IRQ_SPI_ERROR_POS 0
361#define IRQ_UART_ERROR_POS 4 168#define IRQ_UART_ERROR_POS 4
362#define IRQ_RESERVED_ERROR_POS 8 169#define IRQ_RESERVED_ERROR_POS 8
363#define IRQ_DMA1_0_POS 12 170#define IRQ_DMA1_0_POS 12
364#define IRQ_DMA1_1_POS 16 171#define IRQ_DMA1_1_POS 16
365#define IRQ_DMA1_2_POS 20 172#define IRQ_DMA1_2_POS 20
366#define IRQ_DMA1_3_POS 24 173#define IRQ_DMA1_3_POS 24
367#define IRQ_DMA1_4_POS 28 174#define IRQ_DMA1_4_POS 28
175
368/* IAR2 BIT FIELDS */ 176/* IAR2 BIT FIELDS */
369#define IRQ_DMA1_5_POS 0 177#define IRQ_DMA1_5_POS 0
370#define IRQ_DMA1_6_POS 4 178#define IRQ_DMA1_6_POS 4
371#define IRQ_DMA1_7_POS 8 179#define IRQ_DMA1_7_POS 8
372#define IRQ_DMA1_8_POS 12 180#define IRQ_DMA1_8_POS 12
373#define IRQ_DMA1_9_POS 16 181#define IRQ_DMA1_9_POS 16
374#define IRQ_DMA1_10_POS 20 182#define IRQ_DMA1_10_POS 20
375#define IRQ_DMA1_11_POS 24 183#define IRQ_DMA1_11_POS 24
376#define IRQ_DMA2_0_POS 28 184#define IRQ_DMA2_0_POS 28
185
377/* IAR3 BIT FIELDS */ 186/* IAR3 BIT FIELDS */
378#define IRQ_DMA2_1_POS 0 187#define IRQ_DMA2_1_POS 0
379#define IRQ_DMA2_2_POS 4 188#define IRQ_DMA2_2_POS 4
380#define IRQ_DMA2_3_POS 8 189#define IRQ_DMA2_3_POS 8
381#define IRQ_DMA2_4_POS 12 190#define IRQ_DMA2_4_POS 12
382#define IRQ_DMA2_5_POS 16 191#define IRQ_DMA2_5_POS 16
383#define IRQ_DMA2_6_POS 20 192#define IRQ_DMA2_6_POS 20
384#define IRQ_DMA2_7_POS 24 193#define IRQ_DMA2_7_POS 24
385#define IRQ_DMA2_8_POS 28 194#define IRQ_DMA2_8_POS 28
195
386/* IAR4 BIT FIELDS */ 196/* IAR4 BIT FIELDS */
387#define IRQ_DMA2_9_POS 0 197#define IRQ_DMA2_9_POS 0
388#define IRQ_DMA2_10_POS 4 198#define IRQ_DMA2_10_POS 4
389#define IRQ_DMA2_11_POS 8 199#define IRQ_DMA2_11_POS 8
390#define IRQ_TIMER0_POS 12 200#define IRQ_TIMER0_POS 12
391#define IRQ_TIMER1_POS 16 201#define IRQ_TIMER1_POS 16
392#define IRQ_TIMER2_POS 20 202#define IRQ_TIMER2_POS 20
393#define IRQ_TIMER3_POS 24 203#define IRQ_TIMER3_POS 24
394#define IRQ_TIMER4_POS 28 204#define IRQ_TIMER4_POS 28
205
395/* IAR5 BIT FIELDS */ 206/* IAR5 BIT FIELDS */
396#define IRQ_TIMER5_POS 0 207#define IRQ_TIMER5_POS 0
397#define IRQ_TIMER6_POS 4 208#define IRQ_TIMER6_POS 4
398#define IRQ_TIMER7_POS 8 209#define IRQ_TIMER7_POS 8
399#define IRQ_TIMER8_POS 12 210#define IRQ_TIMER8_POS 12
400#define IRQ_TIMER9_POS 16 211#define IRQ_TIMER9_POS 16
401#define IRQ_TIMER10_POS 20 212#define IRQ_TIMER10_POS 20
402#define IRQ_TIMER11_POS 24 213#define IRQ_TIMER11_POS 24
403#define IRQ_PROG0_INTA_POS 28 214#define IRQ_PROG0_INTA_POS 28
215
404/* IAR6 BIT FIELDS */ 216/* IAR6 BIT FIELDS */
405#define IRQ_PROG0_INTB_POS 0 217#define IRQ_PROG0_INTB_POS 0
406#define IRQ_PROG1_INTA_POS 4 218#define IRQ_PROG1_INTA_POS 4
407#define IRQ_PROG1_INTB_POS 8 219#define IRQ_PROG1_INTB_POS 8
408#define IRQ_PROG2_INTA_POS 12 220#define IRQ_PROG2_INTA_POS 12
409#define IRQ_PROG2_INTB_POS 16 221#define IRQ_PROG2_INTB_POS 16
410#define IRQ_DMA1_WRRD0_POS 20 222#define IRQ_DMA1_WRRD0_POS 20
411#define IRQ_DMA1_WRRD1_POS 24 223#define IRQ_DMA1_WRRD1_POS 24
412#define IRQ_DMA2_WRRD0_POS 28 224#define IRQ_DMA2_WRRD0_POS 28
413/* IAR7 BIT FIELDS */
414#define IRQ_DMA2_WRRD1_POS 0
415#define IRQ_IMDMA_WRRD0_POS 4
416#define IRQ_IMDMA_WRRD1_POS 8
417#define IRQ_WDTIMER_POS 12
418#define IRQ_RESERVED_1_POS 16
419#define IRQ_RESERVED_2_POS 20
420#define IRQ_SUPPLE_0_POS 24
421#define IRQ_SUPPLE_1_POS 28
422 225
423#endif /* _BF561_IRQ_H_ */ 226/* IAR7 BIT FIELDS */
227#define IRQ_DMA2_WRRD1_POS 0
228#define IRQ_IMDMA_WRRD0_POS 4
229#define IRQ_IMDMA_WRRD1_POS 8
230#define IRQ_WDTIMER_POS 12
231#define IRQ_RESERVED_1_POS 16
232#define IRQ_RESERVED_2_POS 20
233#define IRQ_SUPPLE_0_POS 24
234#define IRQ_SUPPLE_1_POS 28
235
236#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 5b96ea549a04..4cc91995f781 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -106,7 +106,7 @@
106#define COREA_L1_SCRATCH_START 0xFFB00000 106#define COREA_L1_SCRATCH_START 0xFFB00000
107#define COREB_L1_SCRATCH_START 0xFF700000 107#define COREB_L1_SCRATCH_START 0xFF700000
108 108
109#ifdef __ASSEMBLY__ 109#ifdef CONFIG_SMP
110 110
111/* 111/*
112 * The following macros both return the address of the PDA for the 112 * The following macros both return the address of the PDA for the
@@ -121,8 +121,7 @@
121 * is allowed to use the specified Dreg for determining the PDA 121 * is allowed to use the specified Dreg for determining the PDA
122 * address to be returned into Preg. 122 * address to be returned into Preg.
123 */ 123 */
124#ifdef CONFIG_SMP 124# define GET_PDA_SAFE(preg) \
125#define GET_PDA_SAFE(preg) \
126 preg.l = lo(DSPID); \ 125 preg.l = lo(DSPID); \
127 preg.h = hi(DSPID); \ 126 preg.h = hi(DSPID); \
128 preg = [preg]; \ 127 preg = [preg]; \
@@ -158,7 +157,7 @@
158 preg = [preg]; \ 157 preg = [preg]; \
1594: 1584:
160 159
161#define GET_PDA(preg, dreg) \ 160# define GET_PDA(preg, dreg) \
162 preg.l = lo(DSPID); \ 161 preg.l = lo(DSPID); \
163 preg.h = hi(DSPID); \ 162 preg.h = hi(DSPID); \
164 dreg = [preg]; \ 163 dreg = [preg]; \
@@ -169,13 +168,17 @@
169 preg = [preg]; \ 168 preg = [preg]; \
1701: \ 1691: \
171 170
172#define GET_CPUID(preg, dreg) \ 171# define GET_CPUID(preg, dreg) \
173 preg.l = lo(DSPID); \ 172 preg.l = lo(DSPID); \
174 preg.h = hi(DSPID); \ 173 preg.h = hi(DSPID); \
175 dreg = [preg]; \ 174 dreg = [preg]; \
176 dreg = ROT dreg BY -1; \ 175 dreg = ROT dreg BY -1; \
177 dreg = CC; 176 dreg = CC;
178 177
178# ifndef __ASSEMBLY__
179
180# include <asm/processor.h>
181
179static inline unsigned long get_l1_scratch_start_cpu(int cpu) 182static inline unsigned long get_l1_scratch_start_cpu(int cpu)
180{ 183{
181 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; 184 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
@@ -210,8 +213,7 @@ static inline unsigned long get_l1_data_b_start(void)
210 return get_l1_data_b_start_cpu(blackfin_core_id()); 213 return get_l1_data_b_start_cpu(blackfin_core_id());
211} 214}
212 215
216# endif /* __ASSEMBLY__ */
213#endif /* CONFIG_SMP */ 217#endif /* CONFIG_SMP */
214 218
215#endif /* __ASSEMBLY__ */
216
217#endif 219#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
new file mode 100644
index 000000000000..7977db2f1c12
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#ifndef __ASSEMBLY__
11
12#ifdef CONFIG_SMP
13
14#include <asm/blackfin.h>
15#include <asm/irqflags.h>
16#include <mach/irq.h>
17
18#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
19
20static inline void
21bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
22{
23 unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
24
25 bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
26 bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
27}
28#define bfin_iwr_restore bfin_iwr_restore
29
30static inline void
31bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
32 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
33{
34 unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
35
36 *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
37 *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
38 bfin_iwr_restore(niwr0, niwr1, niwr2);
39}
40#define bfin_iwr_save bfin_iwr_save
41
42static inline void
43bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
44{
45 bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
46}
47
48#endif
49
50#endif
51
52#include <mach-common/pll.h>
53
54#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
index 2c8c514dd386..346c60589be6 100644
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -7,6 +7,8 @@
7#ifndef _MACH_BF561_SMP 7#ifndef _MACH_BF561_SMP
8#define _MACH_BF561_SMP 8#define _MACH_BF561_SMP
9 9
10/* This header has to stand alone to avoid circular deps */
11
10struct task_struct; 12struct task_struct;
11 13
12void platform_init_cpus(void); 14void platform_init_cpus(void);
@@ -17,13 +19,13 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
17 19
18void platform_secondary_init(unsigned int cpu); 20void platform_secondary_init(unsigned int cpu);
19 21
20void platform_request_ipi(int (*handler)(int, void *)); 22void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
21 23
22void platform_send_ipi(cpumask_t callmap); 24void platform_send_ipi(cpumask_t callmap, int irq);
23 25
24void platform_send_ipi_cpu(unsigned int cpu); 26void platform_send_ipi_cpu(unsigned int cpu, int irq);
25 27
26void platform_clear_ipi(unsigned int cpu); 28void platform_clear_ipi(unsigned int cpu, int irq);
27 29
28void bfin_local_timer_setup(void); 30void bfin_local_timer_setup(void);
29 31
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index b4424172ad9e..7ee9262fe132 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -13,7 +13,7 @@
13void __init program_IAR(void) 13void __init program_IAR(void)
14{ 14{
15 /* Program the IAR0 Register with the configured priority */ 15 /* Program the IAR0 Register with the configured priority */
16 bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | 16 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | 17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | 18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | 19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
@@ -22,7 +22,7 @@ void __init program_IAR(void)
22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | 22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); 23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
24 24
25 bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | 25 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | 26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | 27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | 28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
@@ -31,7 +31,7 @@ void __init program_IAR(void)
31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | 31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); 32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
33 33
34 bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | 34 bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | 35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | 36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | 37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
@@ -40,7 +40,7 @@ void __init program_IAR(void)
40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | 40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); 41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
42 42
43 bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | 43 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | 44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | 45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | 46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
@@ -49,7 +49,7 @@ void __init program_IAR(void)
49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | 49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); 50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
51 51
52 bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | 52 bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | 53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | 54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | 55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
@@ -58,7 +58,7 @@ void __init program_IAR(void)
58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | 58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); 59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
60 60
61 bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | 61 bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | 62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | 63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | 64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
@@ -67,7 +67,7 @@ void __init program_IAR(void)
67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | 67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); 68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
69 69
70 bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | 70 bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | 71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | 72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | 73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
@@ -76,7 +76,7 @@ void __init program_IAR(void)
76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | 76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); 77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
78 78
79 bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | 79 bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | 80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | 81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | 82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4624eebbf9c4..4c462838f4e1 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -13,7 +13,11 @@
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/trace.h> 14#include <asm/trace.h>
15 15
16__INIT 16/*
17 * This code must come first as CoreB is hardcoded (in hardware)
18 * to start at the beginning of its L1 instruction memory.
19 */
20.section .l1.text.head
17 21
18/* Lay the initial stack into the L1 scratch area of Core B */ 22/* Lay the initial stack into the L1 scratch area of Core B */
19#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) 23#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
@@ -160,43 +164,34 @@ ENTRY(_coreb_trampoline_start)
160.LWAIT_HERE: 164.LWAIT_HERE:
161 jump .LWAIT_HERE; 165 jump .LWAIT_HERE;
162ENDPROC(_coreb_trampoline_start) 166ENDPROC(_coreb_trampoline_start)
163ENTRY(_coreb_trampoline_end)
164 167
168#ifdef CONFIG_HOTPLUG_CPU
165.section ".text" 169.section ".text"
166ENTRY(_set_sicb_iwr) 170ENTRY(_coreb_die)
167 P0.H = hi(SICB_IWR0);
168 P0.L = lo(SICB_IWR0);
169 P1.H = hi(SICB_IWR1);
170 P1.L = lo(SICB_IWR1);
171 [P0] = R0;
172 [P1] = R1;
173 SSYNC;
174 RTS;
175ENDPROC(_set_sicb_iwr)
176
177ENTRY(_coreb_sleep)
178 sp.l = lo(INITIAL_STACK); 171 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK); 172 sp.h = hi(INITIAL_STACK);
180 fp = sp; 173 fp = sp;
181 usp = sp; 174 usp = sp;
182 175
183 call _set_sicb_iwr;
184
185 CLI R2; 176 CLI R2;
186 SSYNC; 177 SSYNC;
187 IDLE; 178 IDLE;
188 STI R2; 179 STI R2;
189 180
190 R0 = IWR_DISABLE_ALL; 181 R0 = IWR_DISABLE_ALL;
191 R1 = IWR_DISABLE_ALL; 182 P0.H = hi(SYSMMR_BASE);
192 call _set_sicb_iwr; 183 P0.L = lo(SYSMMR_BASE);
184 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
185 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
186 SSYNC;
193 187
194 p0.h = hi(COREB_L1_CODE_START); 188 p0.h = hi(COREB_L1_CODE_START);
195 p0.l = lo(COREB_L1_CODE_START); 189 p0.l = lo(COREB_L1_CODE_START);
196 jump (p0); 190 jump (p0);
197ENDPROC(_coreb_sleep) 191ENDPROC(_coreb_die)
192#endif
198 193
199__CPUINIT 194__INIT
200ENTRY(_coreb_start) 195ENTRY(_coreb_start)
201 [--sp] = reti; 196 [--sp] = reti;
202 197
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 3b9a4bf7dacc..85abd8be1343 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -24,24 +24,23 @@ static DEFINE_SPINLOCK(boot_lock);
24 24
25void __init platform_init_cpus(void) 25void __init platform_init_cpus(void)
26{ 26{
27 cpu_set(0, cpu_possible_map); /* CoreA */ 27 struct cpumask mask;
28 cpu_set(1, cpu_possible_map); /* CoreB */ 28
29 cpumask_set_cpu(0, &mask); /* CoreA */
30 cpumask_set_cpu(1, &mask); /* CoreB */
31 init_cpu_possible(&mask);
29} 32}
30 33
31void __init platform_prepare_cpus(unsigned int max_cpus) 34void __init platform_prepare_cpus(unsigned int max_cpus)
32{ 35{
33 int len; 36 struct cpumask mask;
34
35 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
36 BUG_ON(len > L1_CODE_LENGTH);
37 37
38 dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len); 38 bfin_relocate_coreb_l1_mem();
39 39
40 /* Both cores ought to be present on a bf561! */ 40 /* Both cores ought to be present on a bf561! */
41 cpu_set(0, cpu_present_map); /* CoreA */ 41 cpumask_set_cpu(0, &mask); /* CoreA */
42 cpu_set(1, cpu_present_map); /* CoreB */ 42 cpumask_set_cpu(1, &mask); /* CoreB */
43 43 init_cpu_present(&mask);
44 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
45} 44}
46 45
47int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ 46int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
@@ -52,26 +51,23 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
52void __cpuinit platform_secondary_init(unsigned int cpu) 51void __cpuinit platform_secondary_init(unsigned int cpu)
53{ 52{
54 /* Clone setup for peripheral interrupt sources from CoreA. */ 53 /* Clone setup for peripheral interrupt sources from CoreA. */
55 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); 54 bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
56 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); 55 bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
57 SSYNC(); 56 SSYNC();
58 57
59 /* Clone setup for IARs from CoreA. */ 58 /* Clone setup for IARs from CoreA. */
60 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); 59 bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
61 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); 60 bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
62 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); 61 bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
63 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); 62 bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
64 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); 63 bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
65 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); 64 bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
66 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); 65 bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
67 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); 66 bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
68 bfin_write_SICB_IWR0(IWR_DISABLE_ALL); 67 bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL); 68 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
70 SSYNC(); 69 SSYNC();
71 70
72 /* Store CPU-private information to the cpu_data array. */
73 bfin_setup_cpudata(cpu);
74
75 /* We are done with local CPU inits, unblock the boot CPU. */ 71 /* We are done with local CPU inits, unblock the boot CPU. */
76 set_cpu_online(cpu, true); 72 set_cpu_online(cpu, true);
77 spin_lock(&boot_lock); 73 spin_lock(&boot_lock);
@@ -86,12 +82,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
86 82
87 spin_lock(&boot_lock); 83 spin_lock(&boot_lock);
88 84
89 if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { 85 if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
90 /* CoreB already running, sending ipi to wakeup it */ 86 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 87 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else { 88 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ 89 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); 90 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
95 SSYNC(); 91 SSYNC();
96 } 92 }
97 93
@@ -111,41 +107,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
111 panic("CPU%u: processor failed to boot\n", cpu); 107 panic("CPU%u: processor failed to boot\n", cpu);
112} 108}
113 109
114void __init platform_request_ipi(irq_handler_t handler) 110static const char supple0[] = "IRQ_SUPPLE_0";
111static const char supple1[] = "IRQ_SUPPLE_1";
112void __init platform_request_ipi(int irq, void *handler)
115{ 113{
116 int ret; 114 int ret;
115 const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
117 116
118 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, 117 ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
119 "Supplemental Interrupt0", handler);
120 if (ret) 118 if (ret)
121 panic("Cannot request supplemental interrupt 0 for IPI service"); 119 panic("Cannot request %s for IPI service", name);
122} 120}
123 121
124void platform_send_ipi(cpumask_t callmap) 122void platform_send_ipi(cpumask_t callmap, int irq)
125{ 123{
126 unsigned int cpu; 124 unsigned int cpu;
125 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
127 126
128 for_each_cpu_mask(cpu, callmap) { 127 for_each_cpu_mask(cpu, callmap) {
129 BUG_ON(cpu >= 2); 128 BUG_ON(cpu >= 2);
130 SSYNC(); 129 SSYNC();
131 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); 130 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
132 SSYNC(); 131 SSYNC();
133 } 132 }
134} 133}
135 134
136void platform_send_ipi_cpu(unsigned int cpu) 135void platform_send_ipi_cpu(unsigned int cpu, int irq)
137{ 136{
137 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
138 BUG_ON(cpu >= 2); 138 BUG_ON(cpu >= 2);
139 SSYNC(); 139 SSYNC();
140 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); 140 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
141 SSYNC(); 141 SSYNC();
142} 142}
143 143
144void platform_clear_ipi(unsigned int cpu) 144void platform_clear_ipi(unsigned int cpu, int irq)
145{ 145{
146 int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
146 BUG_ON(cpu >= 2); 147 BUG_ON(cpu >= 2);
147 SSYNC(); 148 SSYNC();
148 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); 149 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
149 SSYNC(); 150 SSYNC();
150} 151}
151 152
@@ -156,9 +157,13 @@ void platform_clear_ipi(unsigned int cpu)
156void __cpuinit bfin_local_timer_setup(void) 157void __cpuinit bfin_local_timer_setup(void)
157{ 158{
158#if defined(CONFIG_TICKSOURCE_CORETMR) 159#if defined(CONFIG_TICKSOURCE_CORETMR)
160 struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
161 struct irq_chip *chip = irq_data_get_irq_chip(data);
162
159 bfin_coretmr_init(); 163 bfin_coretmr_init();
160 bfin_coretmr_clockevent_init(); 164 bfin_coretmr_clockevent_init();
161 get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR); 165
166 chip->irq_unmask(data);
162#else 167#else
163 /* Power down the core timer, just to play safe. */ 168 /* Power down the core timer, just to play safe. */
164 bfin_write_TCNTL(0); 169 bfin_write_TCNTL(0);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 22:53:55 -0400