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authorIngo Molnar <mingo@elte.hu>2009-01-10 22:45:50 -0500
committerIngo Molnar <mingo@elte.hu>2009-01-10 22:45:50 -0500
commite8b722f487589a1f60ca27adc695494f188d404e (patch)
treebe3897dceb9b7c0949a8917ab11eea2752375e3b /arch/blackfin/mach-bf561/include/mach
parent01d07820a0df6b6134c1bb75b1e84c9d0cdab3be (diff)
parentc59765042f53a79a7a65585042ff463b69cb248c (diff)
Merge commit 'v2.6.29-rc1' into irq/urgent
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bf561.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h4
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h103
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h3
-rw-r--r--arch/blackfin/mach-bf561/include/mach/dma.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h68
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_init.h295
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h80
-rw-r--r--arch/blackfin/mach-bf561/include/mach/smp.h22
11 files changed, 256 insertions, 478 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22990df04ae1..1a9e17562821 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List 10 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -264,6 +264,18 @@
264#define ANOMALY_05000371 (1) 264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1) 266#define ANOMALY_05000403 (1)
267/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
268#define ANOMALY_05000412 (1)
269/* Speculative Fetches Can Cause Undesired External FIFO Operations */
270#define ANOMALY_05000416 (1)
271/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
272#define ANOMALY_05000425 (1)
273/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
274#define ANOMALY_05000426 (1)
275/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
278#define ANOMALY_05000443 (1)
267 279
268/* Anomalies that don't exist on this proc */ 280/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000158 (0) 281#define ANOMALY_05000158 (0)
@@ -272,5 +284,7 @@
272#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
273#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
274#define ANOMALY_05000386 (1) 286#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0)
288#define ANOMALY_05000435 (0)
275 289
276#endif 290#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
index 18b1b3a223ab..9968362a2ee4 100644
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -215,7 +215,7 @@
215#endif 215#endif
216 216
217#ifndef CPU 217#ifndef CPU
218#error Unknown CPU type - This kernel doesn't seem to be configured properly 218#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
219#endif 219#endif
220 220
221#endif /* __MACH_BF561_H__ */ 221#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 0ea8666e6764..f79f6626b7ec 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -66,8 +66,12 @@
66 66
67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) 67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) 68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
69#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
70#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 71#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 72#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
73#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
74#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
71 75
72#define BFIN_UART_NR_PORTS 1 76#define BFIN_UART_NR_PORTS 1
73 77
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index c14d63402e70..95d609f11c97 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -39,65 +39,15 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44/*********************************************************************************** */ 42/*********************************************************************************** */
45/* System MMR Register Map */ 43/* System MMR Register Map */
46/*********************************************************************************** */ 44/*********************************************************************************** */
47 45
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 50#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 51#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 52#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 53#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() 1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) 1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578 1528
1529/* These need to be last due to the cdef/linux inter-dependencies */
1530#include <asm/irq.h>
1531
1532/* Writing to PLL_CTL initiates a PLL relock sequence. */
1533static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1534{
1535 unsigned long flags, iwr0, iwr1;
1536
1537 if (val == bfin_read_PLL_CTL())
1538 return;
1539
1540 local_irq_save_hw(flags);
1541 /* Enable the PLL Wakeup bit in SIC IWR */
1542 iwr0 = bfin_read32(SICA_IWR0);
1543 iwr1 = bfin_read32(SICA_IWR1);
1544 /* Only allow PPL Wakeup) */
1545 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1546 bfin_write32(SICA_IWR1, 0);
1547
1548 bfin_write16(PLL_CTL, val);
1549 SSYNC();
1550 asm("IDLE;");
1551
1552 bfin_write32(SICA_IWR0, iwr0);
1553 bfin_write32(SICA_IWR1, iwr1);
1554 local_irq_restore_hw(flags);
1555}
1556
1557/* Writing to VR_CTL initiates a PLL relock sequence. */
1558static __inline__ void bfin_write_VR_CTL(unsigned int val)
1559{
1560 unsigned long flags, iwr0, iwr1;
1561
1562 if (val == bfin_read_VR_CTL())
1563 return;
1564
1565 local_irq_save_hw(flags);
1566 /* Enable the PLL Wakeup bit in SIC IWR */
1567 iwr0 = bfin_read32(SICA_IWR0);
1568 iwr1 = bfin_read32(SICA_IWR1);
1569 /* Only allow PPL Wakeup) */
1570 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1571 bfin_write32(SICA_IWR1, 0);
1572
1573 bfin_write16(VR_CTL, val);
1574 SSYNC();
1575 asm("IDLE;");
1576
1577 bfin_write32(SICA_IWR0, iwr0);
1578 bfin_write32(SICA_IWR1, iwr1);
1579 local_irq_restore_hw(flags);
1580}
1581
1579#endif /* _CDEF_BF561_H */ 1582#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 4eca2026bb92..d7c509759659 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -912,6 +912,9 @@
912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
914 914
915/* SICA_SYSCR Masks */
916#define COREB_SRAM_INIT 0x0020
917
915/* SWRST Mask */ 918/* SWRST Mask */
916#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ 919#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
917#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ 920#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
index 8bc46cd89a02..13647c71f1c7 100644
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ b/arch/blackfin/mach-bf561/include/mach/dma.h
@@ -1,13 +1,17 @@
1/***************************************************************************** 1/* mach/dma.h - arch-specific DMA defines
2* 2 *
3* BF-533/2/1 Specific Declarations 3 * Copyright 2004-2008 Analog Devices Inc.
4* 4 *
5****************************************************************************/ 5 * Licensed under the GPL-2 or later.
6 */
6 7
7#ifndef _MACH_DMA_H_ 8#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_ 9#define _MACH_DMA_H_
9 10
10#define MAX_BLACKFIN_DMA_CHANNEL 36 11#define MAX_DMA_CHANNELS 36
12
13/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
14#define MAX_DMA_SUSPEND_CHANNELS 32
11 15
12#define CH_PPI0 0 16#define CH_PPI0 0
13#define CH_PPI (CH_PPI0) 17#define CH_PPI (CH_PPI0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
new file mode 100644
index 000000000000..7882f79e1ade
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -0,0 +1,68 @@
1/*
2 * File: arch/blackfin/mach-bf561/include/mach/gpio.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9
10#ifndef _MACH_GPIO_H_
11#define _MACH_GPIO_H_
12
13#define MAX_BLACKFIN_GPIOS 48
14
15#define GPIO_PF0 0
16#define GPIO_PF1 1
17#define GPIO_PF2 2
18#define GPIO_PF3 3
19#define GPIO_PF4 4
20#define GPIO_PF5 5
21#define GPIO_PF6 6
22#define GPIO_PF7 7
23#define GPIO_PF8 8
24#define GPIO_PF9 9
25#define GPIO_PF10 10
26#define GPIO_PF11 11
27#define GPIO_PF12 12
28#define GPIO_PF13 13
29#define GPIO_PF14 14
30#define GPIO_PF15 15
31#define GPIO_PF16 16
32#define GPIO_PF17 17
33#define GPIO_PF18 18
34#define GPIO_PF19 19
35#define GPIO_PF20 20
36#define GPIO_PF21 21
37#define GPIO_PF22 22
38#define GPIO_PF23 23
39#define GPIO_PF24 24
40#define GPIO_PF25 25
41#define GPIO_PF26 26
42#define GPIO_PF27 27
43#define GPIO_PF28 28
44#define GPIO_PF29 29
45#define GPIO_PF30 30
46#define GPIO_PF31 31
47#define GPIO_PF32 32
48#define GPIO_PF33 33
49#define GPIO_PF34 34
50#define GPIO_PF35 35
51#define GPIO_PF36 36
52#define GPIO_PF37 37
53#define GPIO_PF38 38
54#define GPIO_PF39 39
55#define GPIO_PF40 40
56#define GPIO_PF41 41
57#define GPIO_PF42 42
58#define GPIO_PF43 43
59#define GPIO_PF44 44
60#define GPIO_PF45 45
61#define GPIO_PF46 46
62#define GPIO_PF47 47
63
64#define PORT_FIO0 GPIO_0
65#define PORT_FIO1 GPIO_16
66#define PORT_FIO2 GPIO_32
67
68#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134/* Equation from section 17 (p17-46) of BF533 HRM */
135#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136
137/* Enable SCLK Out */
138#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139
140#if defined CONFIG_CLKIN_HALF
141#define CLKIN_HALF 1
142#else
143#define CLKIN_HALF 0
144#endif
145
146#if defined CONFIG_PLL_BYPASS
147#define PLL_BYPASS 1
148#else
149#define PLL_BYPASS 0
150#endif
151
152/***************************************Currently Not Being Used *********************************/
153#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158
159#if (flash_EBIU_AMBCTL_TT > 3)
160#define flash_EBIU_AMBCTL0_TT B0TT_4
161#endif
162#if (flash_EBIU_AMBCTL_TT == 3)
163#define flash_EBIU_AMBCTL0_TT B0TT_3
164#endif
165#if (flash_EBIU_AMBCTL_TT == 2)
166#define flash_EBIU_AMBCTL0_TT B0TT_2
167#endif
168#if (flash_EBIU_AMBCTL_TT < 2)
169#define flash_EBIU_AMBCTL0_TT B0TT_1
170#endif
171
172#if (flash_EBIU_AMBCTL_ST > 3)
173#define flash_EBIU_AMBCTL0_ST B0ST_4
174#endif
175#if (flash_EBIU_AMBCTL_ST == 3)
176#define flash_EBIU_AMBCTL0_ST B0ST_3
177#endif
178#if (flash_EBIU_AMBCTL_ST == 2)
179#define flash_EBIU_AMBCTL0_ST B0ST_2
180#endif
181#if (flash_EBIU_AMBCTL_ST < 2)
182#define flash_EBIU_AMBCTL0_ST B0ST_1
183#endif
184
185#if (flash_EBIU_AMBCTL_HT > 2)
186#define flash_EBIU_AMBCTL0_HT B0HT_3
187#endif
188#if (flash_EBIU_AMBCTL_HT == 2)
189#define flash_EBIU_AMBCTL0_HT B0HT_2
190#endif
191#if (flash_EBIU_AMBCTL_HT == 1)
192#define flash_EBIU_AMBCTL0_HT B0HT_1
193#endif
194#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195#define flash_EBIU_AMBCTL0_HT B0HT_0
196#endif
197#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198#define flash_EBIU_AMBCTL0_HT B0HT_1
199#endif
200
201#if (flash_EBIU_AMBCTL_WAT > 14)
202#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203#endif
204#if (flash_EBIU_AMBCTL_WAT == 14)
205#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206#endif
207#if (flash_EBIU_AMBCTL_WAT == 13)
208#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209#endif
210#if (flash_EBIU_AMBCTL_WAT == 12)
211#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212#endif
213#if (flash_EBIU_AMBCTL_WAT == 11)
214#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215#endif
216#if (flash_EBIU_AMBCTL_WAT == 10)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 9)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 8)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 7)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 6)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 5)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 4)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 3)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 2)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 1)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245#endif
246
247#if (flash_EBIU_AMBCTL_RAT > 14)
248#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249#endif
250#if (flash_EBIU_AMBCTL_RAT == 14)
251#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252#endif
253#if (flash_EBIU_AMBCTL_RAT == 13)
254#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255#endif
256#if (flash_EBIU_AMBCTL_RAT == 12)
257#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258#endif
259#if (flash_EBIU_AMBCTL_RAT == 11)
260#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261#endif
262#if (flash_EBIU_AMBCTL_RAT == 10)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 9)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 8)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 7)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 6)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 5)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 4)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 3)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 2)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 1)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291#endif
292
293#define flash_EBIU_AMBCTL0 \
294 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index f1d4c0637bd2..419dffdc96eb 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -85,4 +85,84 @@
85#define L1_SCRATCH_START COREA_L1_SCRATCH_START 85#define L1_SCRATCH_START COREA_L1_SCRATCH_START
86#define L1_SCRATCH_LENGTH 0x1000 86#define L1_SCRATCH_LENGTH 0x1000
87 87
88#ifdef __ASSEMBLY__
89
90/*
91 * The following macros both return the address of the PDA for the
92 * current core.
93 *
94 * In its first safe (and hairy) form, the macro neither clobbers any
95 * register aside of the output Preg, nor uses the stack, since it
96 * could be called with an invalid stack pointer, or the current stack
97 * space being uncovered by any CPLB (e.g. early exception handling).
98 *
99 * The constraints on the second form are a bit relaxed, and the code
100 * is allowed to use the specified Dreg for determining the PDA
101 * address to be returned into Preg.
102 */
103#ifdef CONFIG_SMP
104#define GET_PDA_SAFE(preg) \
105 preg.l = lo(DSPID); \
106 preg.h = hi(DSPID); \
107 preg = [preg]; \
108 preg = preg << 2; \
109 preg = preg << 2; \
110 preg = preg << 2; \
111 preg = preg << 2; \
112 preg = preg << 2; \
113 preg = preg << 2; \
114 preg = preg << 2; \
115 preg = preg << 2; \
116 preg = preg << 2; \
117 preg = preg << 2; \
118 preg = preg << 2; \
119 preg = preg << 2; \
120 if cc jump 2f; \
121 cc = preg == 0x0; \
122 preg.l = _cpu_pda; \
123 preg.h = _cpu_pda; \
124 if !cc jump 3f; \
1251: \
126 /* preg = 0x0; */ \
127 cc = !cc; /* restore cc to 0 */ \
128 jump 4f; \
1292: \
130 cc = preg == 0x0; \
131 preg.l = _cpu_pda; \
132 preg.h = _cpu_pda; \
133 if cc jump 4f; \
134 /* preg = 0x1000000; */ \
135 cc = !cc; /* restore cc to 1 */ \
1363: \
137 preg = [preg]; \
1384:
139
140#define GET_PDA(preg, dreg) \
141 preg.l = lo(DSPID); \
142 preg.h = hi(DSPID); \
143 dreg = [preg]; \
144 preg.l = _cpu_pda; \
145 preg.h = _cpu_pda; \
146 cc = bittst(dreg, 0); \
147 if !cc jump 1f; \
148 preg = [preg]; \
1491: \
150
151#define GET_CPUID(preg, dreg) \
152 preg.l = lo(DSPID); \
153 preg.h = hi(DSPID); \
154 dreg = [preg]; \
155 dreg = ROT dreg BY -1; \
156 dreg = CC;
157
158#else
159#define GET_PDA_SAFE(preg) \
160 preg.l = _cpu_pda; \
161 preg.h = _cpu_pda;
162
163#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
164#endif /* CONFIG_SMP */
165
166#endif /* __ASSEMBLY__ */
167
88#endif /* _MEM_MAP_533_H_ */ 168#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
new file mode 100644
index 000000000000..f9e65ebe81b2
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -0,0 +1,22 @@
1#ifndef _MACH_BF561_SMP
2#define _MACH_BF561_SMP
3
4struct task_struct;
5
6void platform_init_cpus(void);
7
8void platform_prepare_cpus(unsigned int max_cpus);
9
10int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
11
12void platform_secondary_init(unsigned int cpu);
13
14void platform_request_ipi(int (*handler)(int, void *));
15
16void platform_send_ipi(cpumask_t callmap);
17
18void platform_send_ipi_cpu(unsigned int cpu);
19
20void platform_clear_ipi(unsigned int cpu);
21
22#endif /* !_MACH_BF561_SMP */
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