Blackfin: TWI: clean up the MMR names

The standard short name for control is CTL and not CTRL. Use TWI0_xxx even on parts that only have one TWI bus to keep things simple. Drop all the cdef helpers since the bus driver takes care of everything. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
author: Mike Frysinger <vapier@gentoo.org> 2010-07-28 15:59:03 -0400
committer: Mike Frysinger <vapier@gentoo.org> 2010-08-06 12:55:55 -0400
commit: ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (patch)
tree: 45880a04101440fe731ab15bca490886aaf50754 /arch/blackfin/mach-bf548
parent: ada091729e8737edc3d455681fda9f745cfd2b63 (diff)
3 files changed, 9 insertions, 9 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index f916c52a148a..e2771094de02 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -60,15 +60,15 @@
 #define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
 #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
 #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
 #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
 #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
 #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
 #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
 #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
 #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 72c343646b2a..3d131065f8e6 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
 #define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
 #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
 #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
 #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
 #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
 #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
 #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
 #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
 #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 54143441af5e..01d52fade45e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -105,15 +105,15 @@
 #define                     TWI0_REGBASE  0xffc00700
 #define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
 #define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
-#define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
+#define                   TWI0_SLAVE_CTL  0xffc00708   /* TWI Slave Mode Control Register */
 #define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
 #define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
-#define                 TWI0_MASTER_CTRL  0xffc00714   /* TWI Master Mode Control Register */
+#define                  TWI0_MASTER_CTL  0xffc00714   /* TWI Master Mode Control Register */
 #define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
 #define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
 #define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
 #define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
-#define                   TWI0_FIFO_CTRL  0xffc00728   /* TWI FIFO Control Register */
+#define                    TWI0_FIFO_CTL  0xffc00728   /* TWI FIFO Control Register */
 #define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
 #define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
author	Mike Frysinger <vapier@gentoo.org>	2010-07-28 15:59:03 -0400
committer	Mike Frysinger <vapier@gentoo.org>	2010-08-06 12:55:55 -0400
commit	ba3f5973ce3eb7ef4894ccd3df78c5cb410b17cc (patch)
tree	45880a04101440fe731ab15bca490886aaf50754 /arch/blackfin/mach-bf548
parent	ada091729e8737edc3d455681fda9f745cfd2b63 (diff)

diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148a..e2771094de02 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -60,15 +60,15 @@
60	#define TWI1_REGBASE 0xffc02200	60	#define TWI1_REGBASE 0xffc02200
61	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */	61	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
62	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */	62	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
63	#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */	63	#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
64	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */	64	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
65	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */	65	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
66	#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */	66	#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
67	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */	67	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
68	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */	68	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
69	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */	69	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
70	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */	70	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
71	#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */	71	#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
72	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */	72	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
73	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */	73	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
74	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */	74	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */


diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2a..3d131065f8e6 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
99	#define TWI1_REGBASE 0xffc02200	99	#define TWI1_REGBASE 0xffc02200
100	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */	100	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
101	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */	101	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
102	#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */	102	#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
103	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */	103	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
104	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */	104	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
105	#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */	105	#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
106	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */	106	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
107	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */	107	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
108	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */	108	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
109	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */	109	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
110	#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */	110	#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
111	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */	111	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
112	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */	112	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
113	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */	113	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */


diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 54143441af5e..01d52fade45e 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -105,15 +105,15 @@
105	#define TWI0_REGBASE 0xffc00700	105	#define TWI0_REGBASE 0xffc00700
106	#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */	106	#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
107	#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */	107	#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
108	#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */	108	#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
109	#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */	109	#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
110	#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */	110	#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
111	#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */	111	#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
112	#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */	112	#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
113	#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */	113	#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
114	#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */	114	#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
115	#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */	115	#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
116	#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */	116	#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
117	#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */	117	#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
118	#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */	118	#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
119	#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */	119	#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */