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authorMike Frysinger <vapier@gentoo.org>2009-10-14 23:45:47 -0400
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:40 -0500
commitcd32cc73625641c068393978e7bb337d29c0cd29 (patch)
tree2919e991260ccb6603b9ac713cd0dff5f83d8854 /arch/blackfin/mach-bf548/include
parentb1fa2e8f626e997c2c4f991f10ed00b6ee080b99 (diff)
Blackfin: punt OTP MMRs
People should not be accessing OTP MMRs directly. They should instead go through the Blackfin ROM helper functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h30
2 files changed, 0 insertions, 52 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index a2e9d9849eba..32f71e6a7c15 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2615,17 +2615,6 @@
2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2617 2617
2618/* OTP/FUSE Registers */
2619
2620#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2621#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2622#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2623#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2624#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2625#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2626#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2627#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2628
2629/* Security Registers */ 2618/* Security Registers */
2630 2619
2631#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 2620#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -2640,17 +2629,6 @@
2640#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) 2629#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2641#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) 2630#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2642 2631
2643/* OTP Read/Write Data Buffer Registers */
2644
2645#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2646#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2647#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2648#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2649#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2650#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2651#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2652#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2653
2654/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ 2632/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2655 2633
2656/* legacy definitions */ 2634/* legacy definitions */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 3ce5ce6c4971..f07c0f76e6d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2143,36 +2143,6 @@
2143 2143
2144#define DPRESCALE 0xf /* Load Counter Register */ 2144#define DPRESCALE 0xf /* Load Counter Register */
2145 2145
2146/* Bit masks for OTP_CONTROL */
2147
2148#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2149#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2150#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2151#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2152#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2153#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2154
2155/* Bit masks for OTP_BEN */
2156
2157#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2158
2159/* Bit masks for OTP_STATUS */
2160
2161#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2162#define FERROR 0x2 /* OTP/Fuse Access Error */
2163#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2164#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2165#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2166
2167/* Bit masks for OTP_TIMING */
2168
2169#define USECDIV 0xff /* Micro Second Divider */
2170#define READACC 0x7f00 /* Read Access Time */
2171#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2172#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2173#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2174#define PGMTIME 0xff000000 /* Program Time */
2175
2176/* Bit masks for SECURE_SYSSWT */ 2146/* Bit masks for SECURE_SYSSWT */
2177 2147
2178#define EMUDABL 0x1 /* Emulation Disable. */ 2148#define EMUDABL 0x1 /* Emulation Disable. */