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authorDavid Howells <dhowells@redhat.com>2010-10-07 09:08:52 -0400
committerDavid Howells <dhowells@redhat.com>2010-10-07 09:08:52 -0400
commit3b139cdb373282dfa72316aa56887371e97cafe8 (patch)
treec8755b136c0787011409d6f8116d5493406d0b55 /arch/blackfin/mach-bf548/include/mach
parent5c74874bc9a838b185fe463153e63f7d895ebb77 (diff)
Blackfin: Rename IRQ flags handling functions
Rename h/w IRQ flags handling functions to be in line with what is expected for the irq renaming patch. This renames local_*_hw() to hard_local_*() using the following perl command: perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"` and then fixing up asm/irqflags.h manually. Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both return the flags rather than passing it through the argument list. Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 777fee61fab8..7865a090d333 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
18 if (val == bfin_read_PLL_CTL()) 18 if (val == bfin_read_PLL_CTL())
19 return; 19 return;
20 20
21 local_irq_save_hw(flags); 21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */ 22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0); 23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1); 24 iwr1 = bfin_read32(SIC_IWR1);
@@ -35,7 +35,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
35 bfin_write32(SIC_IWR0, iwr0); 35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1); 36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2); 37 bfin_write32(SIC_IWR2, iwr2);
38 local_irq_restore_hw(flags); 38 hard_local_irq_restore(flags);
39} 39}
40 40
41/* Writing to VR_CTL initiates a PLL relock sequence. */ 41/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -46,7 +46,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
46 if (val == bfin_read_VR_CTL()) 46 if (val == bfin_read_VR_CTL())
47 return; 47 return;
48 48
49 local_irq_save_hw(flags); 49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */ 50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0); 51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1); 52 iwr1 = bfin_read32(SIC_IWR1);
@@ -63,7 +63,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
63 bfin_write32(SIC_IWR0, iwr0); 63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1); 64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2); 65 bfin_write32(SIC_IWR2, iwr2);
66 local_irq_restore_hw(flags); 66 hard_local_irq_restore(flags);
67} 67}
68 68
69#endif /* _MACH_PLL_H */ 69#endif /* _MACH_PLL_H */