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authorMike Frysinger <vapier@gentoo.org>2010-10-27 15:29:26 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:16 -0500
commit10cdc1a78a02bb1d76b28b146083cb060399d86f (patch)
tree0b2cdb9379109ca114983186b4a7430fe896d543 /arch/blackfin/mach-bf548/include/mach
parent73a400646b8e26615f3ef1a0a4bc0cd0d5bd284c (diff)
Blackfin: unify pll.h headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h70
1 files changed, 1 insertions, 69 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d333..94cca674d835 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
67}
68
69#endif /* _MACH_PLL_H */