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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:01:11 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:01:11 -0400
commit0fc2f137226eff4c9dd90864dda5c237474c3ec5 (patch)
tree50ec67f1f9d144a3ceb5ccff45a37bc5005f6c3d /arch/blackfin/mach-bf548/include/mach/portmux.h
parentdcded10f6dce10411b16134ce9cc87bfdf75c13f (diff)
parentaab2393e2ec52c74b419af7c26a12e21584e483b (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits) Blackfin: gpio: add a debounce stub Blackfin: update defconfigs Blackfin: remove CONFIG_MEM_GENERIC_BOARD Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing Blackfin: unify rotary encoder bitmasks Blackfin: unify SDH/RSI bitmasks Blackfin: BF54x: tweak DMAC MMR naming to match other ports Blackfin: TWI: clean up the MMR names Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers Blackfin: add support for dynamic ftrace Blackfin: add support for LZO compressed kernels Blackfin: portmux: fix peripheral map overflow when requesting pins Blackfin: document SPI CS limitations with CPHA=0 Blackfin: remove useless and outdated documentation Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options Blackfin: gpio/portmux: clean up whitespace corruption Blackfin: make sure mmiowb inserts a write barrier with SSYNC Blackfin: fix DMA/cache bug when resuming from suspend to RAM Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin) Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS ...
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/portmux.h')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/portmux.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
index 89ad6a886362..e22246202730 100644
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11 11
12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
@@ -131,6 +131,7 @@
131#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) 131#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
132#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) 132#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
133 133
134#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
134#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 135#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
135#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) 136#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
136#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) 137#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))