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authorDavid S. Miller <davem@davemloft.net>2008-09-16 17:11:43 -0400
committerDavid S. Miller <davem@davemloft.net>2008-09-16 17:11:43 -0400
commit2e57572a50a4de41c6cbc879a4866a312d4cd316 (patch)
treec4f58ec96c06642c4b415b881d3f0a3b673d5b44 /arch/blackfin/mach-bf548/include/mach/defBF547.h
parent9b2e43ae4e9609f80034dfe8de895045cac52d77 (diff)
parentf948cc6ab9e61a8e88d70ee9aafc690e6d26f92c (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
Conflicts: arch/sparc64/kernel/pci_psycho.c
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF547.h')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h1244
1 files changed, 1244 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
new file mode 100644
index 000000000000..661f0d877bd1
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -0,0 +1,1244 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF547.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_REGBASE 0xffc02400
144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* ATAPI Registers */
153
154#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
155#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
156#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
157#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
158#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
159#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
160#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
161#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
162#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
163#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
164#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
165#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
166#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
167#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
168#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
169#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
170#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
171#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
172#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
173#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
174#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
175#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
176#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
177#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
178#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
179
180/* SDH Registers */
181
182#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
183#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
184#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
185#define SDH_COMMAND 0xffc0390c /* SDH Command */
186#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
187#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
188#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
189#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
190#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
191#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
192#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
193#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
194#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
195#define SDH_STATUS 0xffc03934 /* SDH Status */
196#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
197#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
198#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
199#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
200#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
201#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
202#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
203#define SDH_CFG 0xffc039c8 /* SDH Configuration */
204#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
205#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
206#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
207#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
208#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
209#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
210#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
211#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
212#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
213
214/* HOST Port Registers */
215
216#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
217#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
218#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
219
220/* USB Control Registers */
221
222#define USB_FADDR 0xffc03c00 /* Function address register */
223#define USB_POWER 0xffc03c04 /* Power management register */
224#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
225#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
226#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
227#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
228#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
229#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
230#define USB_FRAME 0xffc03c20 /* USB frame number */
231#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
232#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
233#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
234#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
235
236/* USB Packet Control Registers */
237
238#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
239#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
240#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
241#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
242#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
243#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
244#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
245#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
246#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
247#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
248#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
249#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
250#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
251
252/* USB Endpoint FIFO Registers */
253
254#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
255#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
256#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
257#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
258#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
259#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
260#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
261#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
262
263/* USB OTG Control Registers */
264
265#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
266#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
267#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
268
269/* USB Phy Control Registers */
270
271#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
272#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
273#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
274#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
275#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
276
277/* (APHY_CNTRL is for ADI usage only) */
278
279#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
280
281/* (APHY_CALIB is for ADI usage only) */
282
283#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
284#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
285
286/* (PHY_TEST is for ADI usage only) */
287
288#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
289#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
290#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
291
292/* USB Endpoint 0 Control Registers */
293
294#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
295#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
296#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
297#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
298#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
299#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
300#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
301#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
302#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
303
304/* USB Endpoint 1 Control Registers */
305
306#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
307#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
308#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
309#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
310#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
311#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
312#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
313#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
314#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
315#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
316
317/* USB Endpoint 2 Control Registers */
318
319#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
320#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
321#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
322#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
323#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
324#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
325#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
326#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
327#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
328#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
329
330/* USB Endpoint 3 Control Registers */
331
332#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
333#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
334#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
335#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
336#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
337#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
338#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
339#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
340#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
341#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
342
343/* USB Endpoint 4 Control Registers */
344
345#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
346#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
347#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
348#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
349#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
350#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
351#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
352#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
353#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
354#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
355
356/* USB Endpoint 5 Control Registers */
357
358#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
359#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
360#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
361#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
362#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
363#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
364#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
365#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
366#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
367#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
368
369/* USB Endpoint 6 Control Registers */
370
371#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
372#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
373#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
374#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
375#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
376#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
377#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
378#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
379#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
380#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
381
382/* USB Endpoint 7 Control Registers */
383
384#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
385#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
386#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
387#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
388#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
389#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
390#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
391#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
392#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
393#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
394#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
395#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
396
397/* USB Channel 0 Config Registers */
398
399#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
400#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
401#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
402#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
403#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
404
405/* USB Channel 1 Config Registers */
406
407#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
408#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
409#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
410#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
411#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
412
413/* USB Channel 2 Config Registers */
414
415#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
416#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
417#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
418#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
419#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
420
421/* USB Channel 3 Config Registers */
422
423#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
424#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
425#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
426#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
427#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
428
429/* USB Channel 4 Config Registers */
430
431#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
432#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
433#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
434#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
435#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
436
437/* USB Channel 5 Config Registers */
438
439#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
440#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
441#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
442#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
443#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
444
445/* USB Channel 6 Config Registers */
446
447#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
448#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
449#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
450#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
451#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
452
453/* USB Channel 7 Config Registers */
454
455#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
456#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
457#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
458#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
459#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
460
461/* Keypad Registers */
462
463#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
464#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
465#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
466#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
467#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
468#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
469
470/* Pixel Compositor (PIXC) Registers */
471
472#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
473#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
474#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
475#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
476#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
477#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
478#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
479#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
480#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
481#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
482#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
483#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
484#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
485#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
486#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
487#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
488#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
489#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
490#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
491
492/* Handshake MDMA 0 Registers */
493
494#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
495#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
496#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
497#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
498#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
499#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
500#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
501
502/* Handshake MDMA 1 Registers */
503
504#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
505#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
506#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
507#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
508#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
509#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
510#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
511
512
513/* ********************************************************** */
514/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
515/* and MULTI BIT READ MACROS */
516/* ********************************************************** */
517
518/* Bit masks for PIXC_CTL */
519
520#define PIXC_EN 0x1 /* Pixel Compositor Enable */
521#define OVR_A_EN 0x2 /* Overlay A Enable */
522#define OVR_B_EN 0x4 /* Overlay B Enable */
523#define IMG_FORM 0x8 /* Image Data Format */
524#define OVR_FORM 0x10 /* Overlay Data Format */
525#define OUT_FORM 0x20 /* Output Data Format */
526#define UDS_MOD 0x40 /* Resampling Mode */
527#define TC_EN 0x80 /* Transparent Color Enable */
528#define IMG_STAT 0x300 /* Image FIFO Status */
529#define OVR_STAT 0xc00 /* Overlay FIFO Status */
530#define WM_LVL 0x3000 /* FIFO Watermark Level */
531
532/* Bit masks for PIXC_AHSTART */
533
534#define A_HSTART 0xfff /* Horizontal Start Coordinates */
535
536/* Bit masks for PIXC_AHEND */
537
538#define A_HEND 0xfff /* Horizontal End Coordinates */
539
540/* Bit masks for PIXC_AVSTART */
541
542#define A_VSTART 0x3ff /* Vertical Start Coordinates */
543
544/* Bit masks for PIXC_AVEND */
545
546#define A_VEND 0x3ff /* Vertical End Coordinates */
547
548/* Bit masks for PIXC_ATRANSP */
549
550#define A_TRANSP 0xf /* Transparency Value */
551
552/* Bit masks for PIXC_BHSTART */
553
554#define B_HSTART 0xfff /* Horizontal Start Coordinates */
555
556/* Bit masks for PIXC_BHEND */
557
558#define B_HEND 0xfff /* Horizontal End Coordinates */
559
560/* Bit masks for PIXC_BVSTART */
561
562#define B_VSTART 0x3ff /* Vertical Start Coordinates */
563
564/* Bit masks for PIXC_BVEND */
565
566#define B_VEND 0x3ff /* Vertical End Coordinates */
567
568/* Bit masks for PIXC_BTRANSP */
569
570#define B_TRANSP 0xf /* Transparency Value */
571
572/* Bit masks for PIXC_INTRSTAT */
573
574#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
575#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
576#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
577#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
578
579/* Bit masks for PIXC_RYCON */
580
581#define A11 0x3ff /* A11 in the Coefficient Matrix */
582#define A12 0xffc00 /* A12 in the Coefficient Matrix */
583#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
584#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
585
586/* Bit masks for PIXC_GUCON */
587
588#define A21 0x3ff /* A21 in the Coefficient Matrix */
589#define A22 0xffc00 /* A22 in the Coefficient Matrix */
590#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
591#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
592
593/* Bit masks for PIXC_BVCON */
594
595#define A31 0x3ff /* A31 in the Coefficient Matrix */
596#define A32 0xffc00 /* A32 in the Coefficient Matrix */
597#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
598#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
599
600/* Bit masks for PIXC_CCBIAS */
601
602#define A14 0x3ff /* A14 in the Bias Vector */
603#define A24 0xffc00 /* A24 in the Bias Vector */
604#define A34 0x3ff00000 /* A34 in the Bias Vector */
605
606/* Bit masks for PIXC_TC */
607
608#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
609#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
610#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
611
612/* Bit masks for HOST_CONTROL */
613
614#define HOST_EN 0x1 /* Host Enable */
615#define HOST_END 0x2 /* Host Endianess */
616#define DATA_SIZE 0x4 /* Data Size */
617#define HOST_RST 0x8 /* Host Reset */
618#define HRDY_OVR 0x20 /* Host Ready Override */
619#define INT_MODE 0x40 /* Interrupt Mode */
620#define BT_EN 0x80 /* Bus Timeout Enable */
621#define EHW 0x100 /* Enable Host Write */
622#define EHR 0x200 /* Enable Host Read */
623#define BDR 0x400 /* Burst DMA Requests */
624
625/* Bit masks for HOST_STATUS */
626
627#define DMA_READY 0x1 /* DMA Ready */
628#define FIFOFULL 0x2 /* FIFO Full */
629#define FIFOEMPTY 0x4 /* FIFO Empty */
630#define DMA_COMPLETE 0x8 /* DMA Complete */
631#define HSHK 0x10 /* Host Handshake */
632#define HSTIMEOUT 0x20 /* Host Timeout */
633#define HIRQ 0x40 /* Host Interrupt Request */
634#define ALLOW_CNFG 0x80 /* Allow New Configuration */
635#define DMA_DIR 0x100 /* DMA Direction */
636#define BTE 0x200 /* Bus Timeout Enabled */
637
638/* Bit masks for HOST_TIMEOUT */
639
640#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
641
642/* Bit masks for KPAD_CTL */
643
644#define KPAD_EN 0x1 /* Keypad Enable */
645#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
646#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
647#define KPAD_COLEN 0xe000 /* Column Enable Width */
648
649/* Bit masks for KPAD_PRESCALE */
650
651#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
652
653/* Bit masks for KPAD_MSEL */
654
655#define DBON_SCALE 0xff /* Debounce Scale Value */
656#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
657
658/* Bit masks for KPAD_ROWCOL */
659
660#define KPAD_ROW 0xff /* Rows Pressed */
661#define KPAD_COL 0xff00 /* Columns Pressed */
662
663/* Bit masks for KPAD_STAT */
664
665#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
666#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
667#define KPAD_PRESSED 0x8 /* Key press current status */
668
669/* Bit masks for KPAD_SOFTEVAL */
670
671#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
672
673/* Bit masks for SDH_COMMAND */
674
675#define CMD_IDX 0x3f /* Command Index */
676#define CMD_RSP 0x40 /* Response */
677#define CMD_L_RSP 0x80 /* Long Response */
678#define CMD_INT_E 0x100 /* Command Interrupt */
679#define CMD_PEND_E 0x200 /* Command Pending */
680#define CMD_E 0x400 /* Command Enable */
681
682/* Bit masks for SDH_PWR_CTL */
683
684#define PWR_ON 0x3 /* Power On */
685#if 0
686#define TBD 0x3c /* TBD */
687#endif
688#define SD_CMD_OD 0x40 /* Open Drain Output */
689#define ROD_CTL 0x80 /* Rod Control */
690
691/* Bit masks for SDH_CLK_CTL */
692
693#define CLKDIV 0xff /* MC_CLK Divisor */
694#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
695#define PWR_SV_E 0x200 /* Power Save Enable */
696#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
697#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
698
699/* Bit masks for SDH_RESP_CMD */
700
701#define RESP_CMD 0x3f /* Response Command */
702
703/* Bit masks for SDH_DATA_CTL */
704
705#define DTX_E 0x1 /* Data Transfer Enable */
706#define DTX_DIR 0x2 /* Data Transfer Direction */
707#define DTX_MODE 0x4 /* Data Transfer Mode */
708#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
709#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
710
711/* Bit masks for SDH_STATUS */
712
713#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
714#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
715#define CMD_TIME_OUT 0x4 /* CMD Time Out */
716#define DAT_TIME_OUT 0x8 /* Data Time Out */
717#define TX_UNDERRUN 0x10 /* Transmit Underrun */
718#define RX_OVERRUN 0x20 /* Receive Overrun */
719#define CMD_RESP_END 0x40 /* CMD Response End */
720#define CMD_SENT 0x80 /* CMD Sent */
721#define DAT_END 0x100 /* Data End */
722#define START_BIT_ERR 0x200 /* Start Bit Error */
723#define DAT_BLK_END 0x400 /* Data Block End */
724#define CMD_ACT 0x800 /* CMD Active */
725#define TX_ACT 0x1000 /* Transmit Active */
726#define RX_ACT 0x2000 /* Receive Active */
727#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
728#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
729#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
730#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
731#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
732#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
733#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
734#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
735
736/* Bit masks for SDH_STATUS_CLR */
737
738#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
739#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
740#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
741#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
742#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
743#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
744#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
745#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
746#define DAT_END_STAT 0x100 /* Data End Status */
747#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
748#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
749
750/* Bit masks for SDH_MASK0 */
751
752#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
753#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
754#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
755#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
756#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
757#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
758#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
759#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
760#define DAT_END_MASK 0x100 /* Data End Mask */
761#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
762#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
763#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
764#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
765#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
766#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
767#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
768#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
769#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
770#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
771#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
772#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
773#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
774
775/* Bit masks for SDH_FIFO_CNT */
776
777#define FIFO_COUNT 0x7fff /* FIFO Count */
778
779/* Bit masks for SDH_E_STATUS */
780
781#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
782#define SD_CARD_DET 0x10 /* SD Card Detect */
783
784/* Bit masks for SDH_E_MASK */
785
786#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
787#define SCD_MSK 0x40 /* Mask Card Detect */
788
789/* Bit masks for SDH_CFG */
790
791#define CLKS_EN 0x1 /* Clocks Enable */
792#define SD4E 0x4 /* SDIO 4-Bit Enable */
793#define MWE 0x8 /* Moving Window Enable */
794#define SD_RST 0x10 /* SDMMC Reset */
795#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
796#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
797#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
798
799/* Bit masks for SDH_RD_WAIT_EN */
800
801#define RWR 0x1 /* Read Wait Request */
802
803/* Bit masks for ATAPI_CONTROL */
804
805#define PIO_START 0x1 /* Start PIO/Reg Op */
806#define MULTI_START 0x2 /* Start Multi-DMA Op */
807#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
808#define XFER_DIR 0x8 /* Transfer Direction */
809#define IORDY_EN 0x10 /* IORDY Enable */
810#define FIFO_FLUSH 0x20 /* Flush FIFOs */
811#define SOFT_RST 0x40 /* Soft Reset */
812#define DEV_RST 0x80 /* Device Reset */
813#define TFRCNT_RST 0x100 /* Trans Count Reset */
814#define END_ON_TERM 0x200 /* End/Terminate Select */
815#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
816#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
817
818/* Bit masks for ATAPI_STATUS */
819
820#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
821#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
822#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
823#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
824
825/* Bit masks for ATAPI_DEV_ADDR */
826
827#define DEV_ADDR 0x1f /* Device Address */
828
829/* Bit masks for ATAPI_INT_MASK */
830
831#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
832#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
833#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
834#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
835#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
836#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
837#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
838#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
839#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
840
841/* Bit masks for ATAPI_INT_STATUS */
842
843#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
844#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
845#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
846#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
847#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
848#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
849#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
850#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
851#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
852
853/* Bit masks for ATAPI_LINE_STATUS */
854
855#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
856#define ATAPI_DASP 0x2 /* Device dasp to host line status */
857#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
858#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
859#define ATAPI_ADDR 0x70 /* ATAPI address line status */
860#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
861#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
862#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
863#define ATAPI_DIORN 0x400 /* ATAPI read line status */
864#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
865
866/* Bit masks for ATAPI_SM_STATE */
867
868#define PIO_CSTATE 0xf /* PIO mode state machine current state */
869#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
870#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
871#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
872
873/* Bit masks for ATAPI_TERMINATE */
874
875#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
876
877/* Bit masks for ATAPI_REG_TIM_0 */
878
879#define T2_REG 0xff /* End of cycle time for register access transfers */
880#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
881
882/* Bit masks for ATAPI_PIO_TIM_0 */
883
884#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
885#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
886#define T4_REG 0xf000 /* DIOW data hold */
887
888/* Bit masks for ATAPI_PIO_TIM_1 */
889
890#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
891
892/* Bit masks for ATAPI_MULTI_TIM_0 */
893
894#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
895#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
896
897/* Bit masks for ATAPI_MULTI_TIM_1 */
898
899#define TKW 0xff /* Selects DIOW negated pulsewidth */
900#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
901
902/* Bit masks for ATAPI_MULTI_TIM_2 */
903
904#define TH 0xff /* Selects DIOW data hold */
905#define TEOC 0xff00 /* Selects end of cycle for DMA */
906
907/* Bit masks for ATAPI_ULTRA_TIM_0 */
908
909#define TACK 0xff /* Selects setup and hold times for TACK */
910#define TENV 0xff00 /* Selects envelope time */
911
912/* Bit masks for ATAPI_ULTRA_TIM_1 */
913
914#define TDVS 0xff /* Selects data valid setup time */
915#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
916
917/* Bit masks for ATAPI_ULTRA_TIM_2 */
918
919#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
920#define TMLI 0xff00 /* Selects interlock time */
921
922/* Bit masks for ATAPI_ULTRA_TIM_3 */
923
924#define TZAH 0xff /* Selects minimum delay required for output */
925#define READY_PAUSE 0xff00 /* Selects ready to pause */
926
927/* Bit masks for TIMER_ENABLE1 */
928
929#define TIMEN8 0x1 /* Timer 8 Enable */
930#define TIMEN9 0x2 /* Timer 9 Enable */
931#define TIMEN10 0x4 /* Timer 10 Enable */
932
933/* Bit masks for TIMER_DISABLE1 */
934
935#define TIMDIS8 0x1 /* Timer 8 Disable */
936#define TIMDIS9 0x2 /* Timer 9 Disable */
937#define TIMDIS10 0x4 /* Timer 10 Disable */
938
939/* Bit masks for TIMER_STATUS1 */
940
941#define TIMIL8 0x1 /* Timer 8 Interrupt */
942#define TIMIL9 0x2 /* Timer 9 Interrupt */
943#define TIMIL10 0x4 /* Timer 10 Interrupt */
944#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
945#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
946#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
947#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
948#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
949#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
950
951/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
952
953/* Bit masks for USB_FADDR */
954
955#define FUNCTION_ADDRESS 0x7f /* Function address */
956
957/* Bit masks for USB_POWER */
958
959#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
960#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
961#define RESUME_MODE 0x4 /* DMA Mode */
962#define RESET 0x8 /* Reset indicator */
963#define HS_MODE 0x10 /* High Speed mode indicator */
964#define HS_ENABLE 0x20 /* high Speed Enable */
965#define SOFT_CONN 0x40 /* Soft connect */
966#define ISO_UPDATE 0x80 /* Isochronous update */
967
968/* Bit masks for USB_INTRTX */
969
970#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
971#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
972#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
973#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
975#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
976#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
977#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
978
979/* Bit masks for USB_INTRRX */
980
981#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
982#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
983#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
984#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
985#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
986#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
987#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
988
989/* Bit masks for USB_INTRTXE */
990
991#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
992#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
993#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
994#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
995#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
996#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
997#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
998#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
999
1000/* Bit masks for USB_INTRRXE */
1001
1002#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1003#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1004#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1005#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1006#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1007#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1008#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1009
1010/* Bit masks for USB_INTRUSB */
1011
1012#define SUSPEND_B 0x1 /* Suspend indicator */
1013#define RESUME_B 0x2 /* Resume indicator */
1014#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1015#define SOF_B 0x8 /* Start of frame */
1016#define CONN_B 0x10 /* Connection indicator */
1017#define DISCON_B 0x20 /* Disconnect indicator */
1018#define SESSION_REQ_B 0x40 /* Session Request */
1019#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1020
1021/* Bit masks for USB_INTRUSBE */
1022
1023#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1024#define RESUME_BE 0x2 /* Resume indicator int enable */
1025#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1026#define SOF_BE 0x8 /* Start of frame int enable */
1027#define CONN_BE 0x10 /* Connection indicator int enable */
1028#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1029#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1030#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1031
1032/* Bit masks for USB_FRAME */
1033
1034#define FRAME_NUMBER 0x7ff /* Frame number */
1035
1036/* Bit masks for USB_INDEX */
1037
1038#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1039
1040/* Bit masks for USB_GLOBAL_CTL */
1041
1042#define GLOBAL_ENA 0x1 /* enables USB module */
1043#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1044#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1045#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1046#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1047#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1048#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1049#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1050#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1051#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1052#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1053#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1054#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1055#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1056#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1057
1058/* Bit masks for USB_OTG_DEV_CTL */
1059
1060#define SESSION 0x1 /* session indicator */
1061#define HOST_REQ 0x2 /* Host negotiation request */
1062#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1063#define VBUS0 0x8 /* Vbus level indicator[0] */
1064#define VBUS1 0x10 /* Vbus level indicator[1] */
1065#define LSDEV 0x20 /* Low-speed indicator */
1066#define FSDEV 0x40 /* Full or High-speed indicator */
1067#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1068
1069/* Bit masks for USB_OTG_VBUS_IRQ */
1070
1071#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1072#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1073#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1074#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1075#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1076#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1077
1078/* Bit masks for USB_OTG_VBUS_MASK */
1079
1080#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1081#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1082#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1083#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1084#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1085#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1086
1087/* Bit masks for USB_CSR0 */
1088
1089#define RXPKTRDY 0x1 /* data packet receive indicator */
1090#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1091#define STALL_SENT 0x4 /* STALL handshake sent */
1092#define DATAEND 0x8 /* Data end indicator */
1093#define SETUPEND 0x10 /* Setup end */
1094#define SENDSTALL 0x20 /* Send STALL handshake */
1095#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1096#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1097#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1098#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1099#define SETUPPKT_H 0x8 /* send Setup token host mode */
1100#define ERROR_H 0x10 /* timeout error indicator host mode */
1101#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1102#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1103#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1104
1105/* Bit masks for USB_COUNT0 */
1106
1107#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1108
1109/* Bit masks for USB_NAKLIMIT0 */
1110
1111#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1112
1113/* Bit masks for USB_TX_MAX_PACKET */
1114
1115#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1116
1117/* Bit masks for USB_RX_MAX_PACKET */
1118
1119#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1120
1121/* Bit masks for USB_TXCSR */
1122
1123#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1124#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1125#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1126#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1127#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1128#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1129#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1130#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1131#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1132#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1133#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1134#define ISO_T 0x4000 /* enable Isochronous transfers */
1135#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1136#define ERROR_TH 0x4 /* error condition host mode */
1137#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1138#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1139
1140/* Bit masks for USB_TXCOUNT */
1141
1142#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1143
1144/* Bit masks for USB_RXCSR */
1145
1146#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1147#define FIFO_FULL_R 0x2 /* FIFO not empty */
1148#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1149#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1150#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1151#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1152#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1153#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1154#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1155#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1156#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1157#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1158#define ISO_R 0x4000 /* enable Isochronous transfers */
1159#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1160#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1161#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1162#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1163#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1164#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1165#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1166
1167/* Bit masks for USB_RXCOUNT */
1168
1169#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1170
1171/* Bit masks for USB_TXTYPE */
1172
1173#define TARGET_EP_NO_T 0xf /* EP number */
1174#define PROTOCOL_T 0xc /* transfer type */
1175
1176/* Bit masks for USB_TXINTERVAL */
1177
1178#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1179
1180/* Bit masks for USB_RXTYPE */
1181
1182#define TARGET_EP_NO_R 0xf /* EP number */
1183#define PROTOCOL_R 0xc /* transfer type */
1184
1185/* Bit masks for USB_RXINTERVAL */
1186
1187#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1188
1189/* Bit masks for USB_DMA_INTERRUPT */
1190
1191#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1192#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1193#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1194#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1195#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1196#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1197#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1198#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1199
1200/* Bit masks for USB_DMAxCONTROL */
1201
1202#define DMA_ENA 0x1 /* DMA enable */
1203#define DIRECTION 0x2 /* direction of DMA transfer */
1204#define MODE 0x4 /* DMA Bus error */
1205#define INT_ENA 0x8 /* Interrupt enable */
1206#define EPNUM 0xf0 /* EP number */
1207#define BUSERROR 0x100 /* DMA Bus error */
1208
1209/* Bit masks for USB_DMAxADDRHIGH */
1210
1211#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1212
1213/* Bit masks for USB_DMAxADDRLOW */
1214
1215#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1216
1217/* Bit masks for USB_DMAxCOUNTHIGH */
1218
1219#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1220
1221/* Bit masks for USB_DMAxCOUNTLOW */
1222
1223#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1224
1225/* Bit masks for HMDMAx_CONTROL */
1226
1227#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1228#define REP 0x2 /* Handshake MDMA Request Polarity */
1229#define UTE 0x8 /* Urgency Threshold Enable */
1230#define OIE 0x10 /* Overflow Interrupt Enable */
1231#define BDIE 0x20 /* Block Done Interrupt Enable */
1232#define MBDI 0x40 /* Mask Block Done Interrupt */
1233#define DRQ 0x300 /* Handshake MDMA Request Type */
1234#define RBC 0x1000 /* Force Reload of BCOUNT */
1235#define PS 0x2000 /* Pin Status */
1236#define OI 0x4000 /* Overflow Interrupt Generated */
1237#define BDI 0x8000 /* Block Done Interrupt Generated */
1238
1239/* ******************************************* */
1240/* MULTI BIT MACRO ENUMERATIONS */
1241/* ******************************************* */
1242
1243
1244#endif /* _DEF_BF548_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 04:19:24 -0500