Blackfin: punt unused MXVR masks

There are no MXVR device drivers, and if someday there is, we can put
these in a dedicated header rather than polluting the global namespace.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 0 insertions, 1013 deletions

diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5a9d0d56ea75..312686a5194d 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -2540,1019 +2540,6 @@
 #define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
 
 
-/********************************* MXVR MASKS ****************************************/
-
-/* MXVR_CONFIG Masks */
-
-#define MXVREN    0x00000001lu
-#define MMSM      0x00000002lu
-#define ACTIVE    0x00000004lu
-#define SDELAY    0x00000008lu
-#define NCMRXEN   0x00000010lu
-#define RWRRXEN   0x00000020lu
-#define MTXEN     0x00000040lu
-#define MTXON     0x00000080lu /*legacy*/
-#define MTXONB    0x00000080lu
-#define EPARITY   0x00000100lu
-#define MSB       0x00001E00lu
-#define APRXEN    0x00002000lu
-#define WAKEUP    0x00004000lu
-#define LMECH     0x00008000lu
-
-#ifdef _MISRA_RULES
-#define SET_MSB(x)     (((x)&0xFu) << 0x9)
-#else
-#define SET_MSB(x)     (((x)&0xF) << 0x9)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_0 Masks */
-
-#define MXTALCEN  0x00000001lu
-#define MXTALFEN  0x00000002lu
-#define MPLLMS    0x00000008lu
-#define MXTALMUL  0x00000030lu
-#define MPLLEN    0x00000040lu
-#define MPLLEN0   0x00000040lu /* legacy */
-#define MPLLEN1   0x00000080lu /* legacy */
-#define MMCLKEN   0x00000100lu
-#define MMCLKMUL  0x00001E00lu
-#define MPLLRSTB  0x00002000lu
-#define MPLLRSTB0 0x00002000lu /* legacy */
-#define MPLLRSTB1 0x00004000lu /* legacy */
-#define MBCLKEN   0x00010000lu
-#define MBCLKDIV  0x001E0000lu
-#define MPLLCDR   0x00200000lu
-#define MPLLCDR0  0x00200000lu /* legacy */
-#define MPLLCDR1  0x00400000lu /* legacy */
-#define INVRX     0x00800000lu
-#define MFSEN     0x01000000lu
-#define MFSDIV    0x1E000000lu
-#define MFSSEL    0x60000000lu
-#define MFSSYNC   0x80000000lu
-
-#define MXTALMUL_256FS   0x00000000lu /* legacy */
-#define MXTALMUL_384FS   0x00000010lu /* legacy */
-#define MXTALMUL_512FS   0x00000020lu /* legacy */
-#define MXTALMUL_1024FS  0x00000030lu
-
-#define MMCLKMUL_1024FS  0x00000000lu
-#define MMCLKMUL_512FS   0x00000200lu
-#define MMCLKMUL_256FS   0x00000400lu
-#define MMCLKMUL_128FS   0x00000600lu
-#define MMCLKMUL_64FS    0x00000800lu
-#define MMCLKMUL_32FS    0x00000A00lu
-#define MMCLKMUL_16FS    0x00000C00lu
-#define MMCLKMUL_8FS     0x00000E00lu
-#define MMCLKMUL_4FS     0x00001000lu
-#define MMCLKMUL_2FS     0x00001200lu
-#define MMCLKMUL_1FS     0x00001400lu
-#define MMCLKMUL_1536FS  0x00001A00lu
-#define MMCLKMUL_768FS   0x00001C00lu
-#define MMCLKMUL_384FS   0x00001E00lu
-
-#define MBCLKDIV_DIV2    0x00020000lu
-#define MBCLKDIV_DIV4    0x00040000lu
-#define MBCLKDIV_DIV8    0x00060000lu
-#define MBCLKDIV_DIV16   0x00080000lu
-#define MBCLKDIV_DIV32   0x000A0000lu
-#define MBCLKDIV_DIV64   0x000C0000lu
-#define MBCLKDIV_DIV128  0x000E0000lu
-#define MBCLKDIV_DIV256  0x00100000lu
-#define MBCLKDIV_DIV512  0x00120000lu
-#define MBCLKDIV_DIV1024 0x00140000lu
-
-#define MFSDIV_DIV2      0x02000000lu
-#define MFSDIV_DIV4      0x04000000lu
-#define MFSDIV_DIV8      0x06000000lu
-#define MFSDIV_DIV16     0x08000000lu
-#define MFSDIV_DIV32     0x0A000000lu
-#define MFSDIV_DIV64     0x0C000000lu
-#define MFSDIV_DIV128    0x0E000000lu
-#define MFSDIV_DIV256    0x10000000lu
-#define MFSDIV_DIV512    0x12000000lu
-#define MFSDIV_DIV1024   0x14000000lu
-
-#define MFSSEL_CLOCK     0x00000000lu
-#define MFSSEL_PULSE_HI  0x20000000lu
-#define MFSSEL_PULSE_LO  0x40000000lu
-
-
-/* MXVR_PLL_CTL_1 Masks */
-
-#define MSTO       0x00000001lu
-#define MSTO0      0x00000001lu /* legacy */
-#define MHOGGD     0x00000004lu
-#define MHOGGD0    0x00000004lu /* legacy */
-#define MHOGGD1    0x00000008lu /* legacy */
-#define MSHAPEREN  0x00000010lu
-#define MSHAPEREN0 0x00000010lu /* legacy */
-#define MSHAPEREN1 0x00000020lu /* legacy */
-#define MPLLCNTEN  0x00008000lu
-#define MPLLCNT    0xFFFF0000lu
-
-#ifdef _MISRA_RULES
-#define SET_MPLLCNT(x)     (((x)&0xFFFFu) << 0x10)
-#else
-#define SET_MPLLCNT(x)     (((x)&0xFFFF) << 0x10)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_2 Masks */
-
-#define MSHAPERSEL 0x00000007lu
-#define MCPSEL     0x000000E0lu
-
-/* MXVR_INT_STAT_0 Masks */
-
-#define NI2A  0x00000001lu
-#define NA2I  0x00000002lu
-#define SBU2L 0x00000004lu
-#define SBL2U 0x00000008lu
-#define PRU   0x00000010lu
-#define MPRU  0x00000020lu
-#define DRU   0x00000040lu
-#define MDRU  0x00000080lu
-#define SBU   0x00000100lu
-#define ATU   0x00000200lu
-#define FCZ0  0x00000400lu
-#define FCZ1  0x00000800lu
-#define PERR  0x00001000lu
-#define MH2L  0x00002000lu
-#define ML2H  0x00004000lu
-#define WUP   0x00008000lu
-#define FU2L  0x00010000lu
-#define FL2U  0x00020000lu
-#define BU2L  0x00040000lu
-#define BL2U  0x00080000lu
-#define PCZ   0x00400000lu
-#define FERR  0x00800000lu
-#define CMR   0x01000000lu
-#define CMROF 0x02000000lu
-#define CMTS  0x04000000lu
-#define CMTC  0x08000000lu
-#define RWRC  0x10000000lu
-#define BCZ   0x20000000lu
-#define BMERR 0x40000000lu
-#define DERR  0x80000000lu
-
-
-/* MXVR_INT_EN_0 Masks */
-
-#define NI2AEN  NI2A
-#define NA2IEN  NA2I
-#define SBU2LEN SBU2L
-#define SBL2UEN SBL2U
-#define PRUEN   PRU
-#define MPRUEN  MPRU
-#define DRUEN   DRU
-#define MDRUEN  MDRU
-#define SBUEN   SBU
-#define ATUEN   ATU
-#define FCZ0EN  FCZ0
-#define FCZ1EN  FCZ1
-#define PERREN  PERR
-#define MH2LEN  MH2L
-#define ML2HEN  ML2H
-#define WUPEN   WUP
-#define FU2LEN  FU2L
-#define FL2UEN  FL2U
-#define BU2LEN  BU2L
-#define BL2UEN  BL2U
-#define PCZEN   PCZ
-#define FERREN  FERR
-#define CMREN   CMR
-#define CMROFEN CMROF
-#define CMTSEN  CMTS
-#define CMTCEN  CMTC
-#define RWRCEN  RWRC
-#define BCZEN   BCZ
-#define BMERREN BMERR
-#define DERREN  DERR
-
-
-/* MXVR_INT_STAT_1 Masks */
-
-#define APR   0x00000004lu
-#define APROF 0x00000008lu
-#define APTS  0x00000040lu
-#define APTC  0x00000080lu
-#define APRCE 0x00000400lu
-#define APRPE 0x00000800lu
-
-#define HDONE0 0x00000001lu
-#define DONE0  0x00000002lu
-#define HDONE1 0x00000010lu
-#define DONE1  0x00000020lu
-#define HDONE2 0x00000100lu
-#define DONE2  0x00000200lu
-#define HDONE3 0x00001000lu
-#define DONE3  0x00002000lu
-#define HDONE4 0x00010000lu
-#define DONE4  0x00020000lu
-#define HDONE5 0x00100000lu
-#define DONE5  0x00200000lu
-#define HDONE6 0x01000000lu
-#define DONE6  0x02000000lu
-#define HDONE7 0x10000000lu
-#define DONE7  0x20000000lu
-
-#define DONEX(x) (0x00000002 << (4 * (x)))
-#define HDONEX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_INT_EN_1 Masks */
-
-#define APREN   APR
-#define APROFEN APROF
-#define APTSEN  APTS
-#define APTCEN  APTC
-#define APRCEEN APRCE
-#define APRPEEN APRPE
-
-#define HDONEEN0 HDONE0
-#define DONEEN0  DONE0
-#define HDONEEN1 HDONE1
-#define DONEEN1  DONE1
-#define HDONEEN2 HDONE2
-#define DONEEN2  DONE2
-#define HDONEEN3 HDONE3
-#define DONEEN3  DONE3
-#define HDONEEN4 HDONE4
-#define DONEEN4  DONE4
-#define HDONEEN5 HDONE5
-#define DONEEN5  DONE5
-#define HDONEEN6 HDONE6
-#define DONEEN6  DONE6
-#define HDONEEN7 HDONE7
-#define DONEEN7  DONE7
-
-#define DONEENX(x) (0x00000002 << (4 * (x)))
-#define HDONEENX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_STATE_0 Masks */
-
-#define NACT     0x00000001lu
-#define SBLOCK   0x00000002lu
-#define PFDLOCK  0x00000004lu
-#define PFDLOCK0 0x00000004lu /* legacy */
-#define PDD      0x00000008lu
-#define PDD0     0x00000008lu /* legacy */
-#define PVCO     0x00000010lu
-#define PVCO0    0x00000010lu /* legacy */
-#define PFDLOCK1 0x00000020lu /* legacy */
-#define PDD1     0x00000040lu /* legacy */
-#define PVCO1    0x00000080lu /* legacy */
-#define APBSY    0x00000100lu
-#define APARB    0x00000200lu
-#define APTX     0x00000400lu
-#define APRX     0x00000800lu
-#define CMBSY    0x00001000lu
-#define CMARB    0x00002000lu
-#define CMTX     0x00004000lu
-#define CMRX     0x00008000lu
-#define MRXONB   0x00010000lu
-#define RGSIP    0x00020000lu
-#define DALIP    0x00040000lu
-#define ALIP     0x00080000lu
-#define RRDIP    0x00100000lu
-#define RWRIP    0x00200000lu
-#define FLOCK    0x00400000lu
-#define BLOCK    0x00800000lu
-#define RSB      0x0F000000lu
-#define DERRNUM  0xF0000000lu
-
-
-/* MXVR_STATE_1 Masks */
-
-#define STXNUMB     0x0000000Flu
-#define SRXNUMB     0x000000F0lu
-#define APCONT      0x00000100lu
-#define DMAACTIVEX  0x00FF0000lu
-#define DMAACTIVE0  0x00010000lu
-#define DMAACTIVE1  0x00020000lu
-#define DMAACTIVE2  0x00040000lu
-#define DMAACTIVE3  0x00080000lu
-#define DMAACTIVE4  0x00100000lu
-#define DMAACTIVE5  0x00200000lu
-#define DMAACTIVE6  0x00400000lu
-#define DMAACTIVE7  0x00800000lu
-#define DMAPMENX    0xFF000000lu
-#define DMAPMEN0    0x01000000lu
-#define DMAPMEN1    0x02000000lu
-#define DMAPMEN2    0x04000000lu
-#define DMAPMEN3    0x08000000lu
-#define DMAPMEN4    0x10000000lu
-#define DMAPMEN5    0x20000000lu
-#define DMAPMEN6    0x40000000lu
-#define DMAPMEN7    0x80000000lu
-
-
-/* MXVR_POSITION Masks */
-
-#define PVALID       0x8000
-#define POSITION     0x003F
-
-
-/* MXVR_MAX_POSITION Masks */
-
-#define MPVALID      0x8000
-#define MPOSITION    0x003F
-
-
-/* MXVR_DELAY Masks */
-
-#define DVALID       0x8000
-#define DELAY        0x003F
-
-
-/* MXVR_MAX_DELAY Masks */
-
-#define MDVALID      0x8000
-#define MDELAY       0x003F
-
-
-/* MXVR_LADDR Masks */
-
-#define LVALID       0x80000000lu
-#define LADDR        0x0000FFFFlu
-
-
-/* MXVR_GADDR Masks */
-
-#define GVALID       0x8000
-#define GADDRL       0x00FF
-
-
-/* MXVR_AADDR Masks */
-
-#define AVALID       0x80000000lu
-#define AADDR        0x0000FFFFlu
-
-
-/* MXVR_ALLOC_0 Masks */
-
-#define CIU0         0x00000080lu
-#define CIU1         0x00008000lu
-#define CIU2         0x00800000lu
-#define CIU3         0x80000000lu
-
-#define CL0          0x0000007Flu
-#define CL1          0x00007F00lu
-#define CL2          0x007F0000lu
-#define CL3          0x7F000000lu
-
-
-/* MXVR_ALLOC_1 Masks */
-
-#define CIU4         0x00000080lu
-#define CIU5         0x00008000lu
-#define CIU6         0x00800000lu
-#define CIU7         0x80000000lu
-
-#define CL4          0x0000007Flu
-#define CL5          0x00007F00lu
-#define CL6          0x007F0000lu
-#define CL7          0x7F000000lu
-
-
-/* MXVR_ALLOC_2 Masks */
-
-#define CIU8         0x00000080lu
-#define CIU9         0x00008000lu
-#define CIU10        0x00800000lu
-#define CIU11        0x80000000lu
-
-#define CL8          0x0000007Flu
-#define CL9          0x00007F00lu
-#define CL10         0x007F0000lu
-#define CL11         0x7F000000lu
-
-
-/* MXVR_ALLOC_3 Masks */
-
-#define CIU12        0x00000080lu
-#define CIU13        0x00008000lu
-#define CIU14        0x00800000lu
-#define CIU15        0x80000000lu
-
-#define CL12         0x0000007Flu
-#define CL13         0x00007F00lu
-#define CL14         0x007F0000lu
-#define CL15         0x7F000000lu
-
-
-/* MXVR_ALLOC_4 Masks */
-
-#define CIU16        0x00000080lu
-#define CIU17        0x00008000lu
-#define CIU18        0x00800000lu
-#define CIU19        0x80000000lu
-
-#define CL16         0x0000007Flu
-#define CL17         0x00007F00lu
-#define CL18         0x007F0000lu
-#define CL19         0x7F000000lu
-
-
-/* MXVR_ALLOC_5 Masks */
-
-#define CIU20        0x00000080lu
-#define CIU21        0x00008000lu
-#define CIU22        0x00800000lu
-#define CIU23        0x80000000lu
-
-#define CL20         0x0000007Flu
-#define CL21         0x00007F00lu
-#define CL22         0x007F0000lu
-#define CL23         0x7F000000lu
-
-
-/* MXVR_ALLOC_6 Masks */
-
-#define CIU24        0x00000080lu
-#define CIU25        0x00008000lu
-#define CIU26        0x00800000lu
-#define CIU27        0x80000000lu
-
-#define CL24         0x0000007Flu
-#define CL25         0x00007F00lu
-#define CL26         0x007F0000lu
-#define CL27         0x7F000000lu
-
-
-/* MXVR_ALLOC_7 Masks */
-
-#define CIU28        0x00000080lu
-#define CIU29        0x00008000lu
-#define CIU30        0x00800000lu
-#define CIU31        0x80000000lu
-
-#define CL28         0x0000007Flu
-#define CL29         0x00007F00lu
-#define CL30         0x007F0000lu
-#define CL31         0x7F000000lu
-
-
-/* MXVR_ALLOC_8 Masks */
-
-#define CIU32        0x00000080lu
-#define CIU33        0x00008000lu
-#define CIU34        0x00800000lu
-#define CIU35        0x80000000lu
-
-#define CL32         0x0000007Flu
-#define CL33         0x00007F00lu
-#define CL34         0x007F0000lu
-#define CL35         0x7F000000lu
-
-
-/* MXVR_ALLOC_9 Masks */
-
-#define CIU36        0x00000080lu
-#define CIU37        0x00008000lu
-#define CIU38        0x00800000lu
-#define CIU39        0x80000000lu
-
-#define CL36         0x0000007Flu
-#define CL37         0x00007F00lu
-#define CL38         0x007F0000lu
-#define CL39         0x7F000000lu
-
-
-/* MXVR_ALLOC_10 Masks */
-
-#define CIU40        0x00000080lu
-#define CIU41        0x00008000lu
-#define CIU42        0x00800000lu
-#define CIU43        0x80000000lu
-
-#define CL40         0x0000007Flu
-#define CL41         0x00007F00lu
-#define CL42         0x007F0000lu
-#define CL43         0x7F000000lu
-
-
-/* MXVR_ALLOC_11 Masks */
-
-#define CIU44        0x00000080lu
-#define CIU45        0x00008000lu
-#define CIU46        0x00800000lu
-#define CIU47        0x80000000lu
-
-#define CL44         0x0000007Flu
-#define CL45         0x00007F00lu
-#define CL46         0x007F0000lu
-#define CL47         0x7F000000lu
-
-
-/* MXVR_ALLOC_12 Masks */
-
-#define CIU48        0x00000080lu
-#define CIU49        0x00008000lu
-#define CIU50        0x00800000lu
-#define CIU51        0x80000000lu
-
-#define CL48         0x0000007Flu
-#define CL49         0x00007F00lu
-#define CL50         0x007F0000lu
-#define CL51         0x7F000000lu
-
-
-/* MXVR_ALLOC_13 Masks */
-
-#define CIU52        0x00000080lu
-#define CIU53        0x00008000lu
-#define CIU54        0x00800000lu
-#define CIU55        0x80000000lu
-
-#define CL52         0x0000007Flu
-#define CL53         0x00007F00lu
-#define CL54         0x007F0000lu
-#define CL55         0x7F000000lu
-
-
-/* MXVR_ALLOC_14 Masks */
-
-#define CIU56        0x00000080lu
-#define CIU57        0x00008000lu
-#define CIU58        0x00800000lu
-#define CIU59        0x80000000lu
-
-#define CL56         0x0000007Flu
-#define CL57         0x00007F00lu
-#define CL58         0x007F0000lu
-#define CL59         0x7F000000lu
-
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-
-/* MXVR_DMAx_CONFIG Masks */
-
-#define MDMAEN      0x00000001lu
-#define DD          0x00000002lu
-#define LCHAN       0x000003C0lu
-#define BITSWAPEN   0x00000400lu
-#define BYSWAPEN    0x00000800lu
-#define MFLOW       0x00007000lu
-#define FIXEDPM     0x00080000lu
-#define STARTPAT    0x00300000lu
-#define STOPPAT     0x00C00000lu
-#define COUNTPOS    0x1C000000lu
-
-#define DD_TX       0x00000000lu
-#define DD_RX       0x00000002lu
-
-#define LCHAN_0     0x00000000lu
-#define LCHAN_1     0x00000040lu
-#define LCHAN_2     0x00000080lu
-#define LCHAN_3     0x000000C0lu
-#define LCHAN_4     0x00000100lu
-#define LCHAN_5     0x00000140lu
-#define LCHAN_6     0x00000180lu
-#define LCHAN_7     0x000001C0lu
-
-#define MFLOW_STOP  0x00000000lu
-#define MFLOW_AUTO  0x00001000lu
-#define MFLOW_PVC   0x00002000lu
-#define MFLOW_PSS   0x00003000lu
-#define MFLOW_PFC   0x00004000lu
-
-#define STARTPAT_0  0x00000000lu
-#define STARTPAT_1  0x00100000lu
-
-#define STOPPAT_0   0x00000000lu
-#define STOPPAT_1   0x00400000lu
-
-#define COUNTPOS_0  0x00000000lu
-#define COUNTPOS_1  0x04000000lu
-#define COUNTPOS_2  0x08000000lu
-#define COUNTPOS_3  0x0C000000lu
-#define COUNTPOS_4  0x10000000lu
-#define COUNTPOS_5  0x14000000lu
-#define COUNTPOS_6  0x18000000lu
-#define COUNTPOS_7  0x1C000000lu
-
-
-/* MXVR_AP_CTL Masks */
-
-#define STARTAP    0x00000001lu
-#define CANCELAP   0x00000002lu
-#define RESETAP    0x00000004lu
-#define APRBE0     0x00004000lu
-#define APRBE1     0x00008000lu
-#define APRBEX     0x0000C000lu
-
-
-/* MXVR_CM_CTL Masks */
-
-#define STARTCM    0x00000001lu
-#define CANCELCM   0x00000002lu
-#define CMRBEX     0xFFFF0000lu
-#define CMRBE0     0x00010000lu
-#define CMRBE1     0x00020000lu
-#define CMRBE2     0x00040000lu
-#define CMRBE3     0x00080000lu
-#define CMRBE4     0x00100000lu
-#define CMRBE5     0x00200000lu
-#define CMRBE6     0x00400000lu
-#define CMRBE7     0x00800000lu
-#define CMRBE8     0x01000000lu
-#define CMRBE9     0x02000000lu
-#define CMRBE10    0x04000000lu
-#define CMRBE11    0x08000000lu
-#define CMRBE12    0x10000000lu
-#define CMRBE13    0x20000000lu
-#define CMRBE14    0x40000000lu
-#define CMRBE15    0x80000000lu
-
-
-/* MXVR_PAT_DATA_x Masks */
-
-#define MATCH_DATA_0 0x000000FFlu
-#define MATCH_DATA_1 0x0000FF00lu
-#define MATCH_DATA_2 0x00FF0000lu
-#define MATCH_DATA_3 0xFF000000lu
-
-
-
-/* MXVR_PAT_EN_x Masks */
-
-#define MATCH_EN_0_0 0x00000001lu
-#define MATCH_EN_0_1 0x00000002lu
-#define MATCH_EN_0_2 0x00000004lu
-#define MATCH_EN_0_3 0x00000008lu
-#define MATCH_EN_0_4 0x00000010lu
-#define MATCH_EN_0_5 0x00000020lu
-#define MATCH_EN_0_6 0x00000040lu
-#define MATCH_EN_0_7 0x00000080lu
-
-#define MATCH_EN_1_0 0x00000100lu
-#define MATCH_EN_1_1 0x00000200lu
-#define MATCH_EN_1_2 0x00000400lu
-#define MATCH_EN_1_3 0x00000800lu
-#define MATCH_EN_1_4 0x00001000lu
-#define MATCH_EN_1_5 0x00002000lu
-#define MATCH_EN_1_6 0x00004000lu
-#define MATCH_EN_1_7 0x00008000lu
-
-#define MATCH_EN_2_0 0x00010000lu
-#define MATCH_EN_2_1 0x00020000lu
-#define MATCH_EN_2_2 0x00040000lu
-#define MATCH_EN_2_3 0x00080000lu
-#define MATCH_EN_2_4 0x00100000lu
-#define MATCH_EN_2_5 0x00200000lu
-#define MATCH_EN_2_6 0x00400000lu
-#define MATCH_EN_2_7 0x00800000lu
-
-#define MATCH_EN_3_0 0x01000000lu
-#define MATCH_EN_3_1 0x02000000lu
-#define MATCH_EN_3_2 0x04000000lu
-#define MATCH_EN_3_3 0x08000000lu
-#define MATCH_EN_3_4 0x10000000lu
-#define MATCH_EN_3_5 0x20000000lu
-#define MATCH_EN_3_6 0x40000000lu
-#define MATCH_EN_3_7 0x80000000lu
-
-
-/* MXVR_ROUTING_0 Masks */
-
-#define MUTE_CH0        0x00000080lu
-#define MUTE_CH1        0x00008000lu
-#define MUTE_CH2        0x00800000lu
-#define MUTE_CH3        0x80000000lu
-
-#define TX_CH0          0x0000007Flu
-#define TX_CH1          0x00007F00lu
-#define TX_CH2          0x007F0000lu
-#define TX_CH3          0x7F000000lu
-
-
-/* MXVR_ROUTING_1 Masks */
-
-#define MUTE_CH4        0x00000080lu
-#define MUTE_CH5        0x00008000lu
-#define MUTE_CH6        0x00800000lu
-#define MUTE_CH7        0x80000000lu
-
-#define TX_CH4          0x0000007Flu
-#define TX_CH5          0x00007F00lu
-#define TX_CH6          0x007F0000lu
-#define TX_CH7          0x7F000000lu
-
-
-/* MXVR_ROUTING_2 Masks */
-
-#define MUTE_CH8        0x00000080lu
-#define MUTE_CH9        0x00008000lu
-#define MUTE_CH10       0x00800000lu
-#define MUTE_CH11       0x80000000lu
-
-#define TX_CH8          0x0000007Flu
-#define TX_CH9          0x00007F00lu
-#define TX_CH10         0x007F0000lu
-#define TX_CH11         0x7F000000lu
-
-/* MXVR_ROUTING_3 Masks */
-
-#define MUTE_CH12       0x00000080lu
-#define MUTE_CH13       0x00008000lu
-#define MUTE_CH14       0x00800000lu
-#define MUTE_CH15       0x80000000lu
-
-#define TX_CH12         0x0000007Flu
-#define TX_CH13         0x00007F00lu
-#define TX_CH14         0x007F0000lu
-#define TX_CH15         0x7F000000lu
-
-
-/* MXVR_ROUTING_4 Masks */
-
-#define MUTE_CH16       0x00000080lu
-#define MUTE_CH17       0x00008000lu
-#define MUTE_CH18       0x00800000lu
-#define MUTE_CH19       0x80000000lu
-
-#define TX_CH16         0x0000007Flu
-#define TX_CH17         0x00007F00lu
-#define TX_CH18         0x007F0000lu
-#define TX_CH19         0x7F000000lu
-
-
-/* MXVR_ROUTING_5 Masks */
-
-#define MUTE_CH20       0x00000080lu
-#define MUTE_CH21       0x00008000lu
-#define MUTE_CH22       0x00800000lu
-#define MUTE_CH23       0x80000000lu
-
-#define TX_CH20         0x0000007Flu
-#define TX_CH21         0x00007F00lu
-#define TX_CH22         0x007F0000lu
-#define TX_CH23         0x7F000000lu
-
-
-/* MXVR_ROUTING_6 Masks */
-
-#define MUTE_CH24       0x00000080lu
-#define MUTE_CH25       0x00008000lu
-#define MUTE_CH26       0x00800000lu
-#define MUTE_CH27       0x80000000lu
-
-#define TX_CH24         0x0000007Flu
-#define TX_CH25         0x00007F00lu
-#define TX_CH26         0x007F0000lu
-#define TX_CH27         0x7F000000lu
-
-
-/* MXVR_ROUTING_7 Masks */
-
-#define MUTE_CH28       0x00000080lu
-#define MUTE_CH29       0x00008000lu
-#define MUTE_CH30       0x00800000lu
-#define MUTE_CH31       0x80000000lu
-
-#define TX_CH28         0x0000007Flu
-#define TX_CH29         0x00007F00lu
-#define TX_CH30         0x007F0000lu
-#define TX_CH31         0x7F000000lu
-
-
-/* MXVR_ROUTING_8 Masks */
-
-#define MUTE_CH32       0x00000080lu
-#define MUTE_CH33       0x00008000lu
-#define MUTE_CH34       0x00800000lu
-#define MUTE_CH35       0x80000000lu
-
-#define TX_CH32         0x0000007Flu
-#define TX_CH33         0x00007F00lu
-#define TX_CH34         0x007F0000lu
-#define TX_CH35         0x7F000000lu
-
-
-/* MXVR_ROUTING_9 Masks */
-
-#define MUTE_CH36       0x00000080lu
-#define MUTE_CH37       0x00008000lu
-#define MUTE_CH38       0x00800000lu
-#define MUTE_CH39       0x80000000lu
-
-#define TX_CH36         0x0000007Flu
-#define TX_CH37         0x00007F00lu
-#define TX_CH38         0x007F0000lu
-#define TX_CH39         0x7F000000lu
-
-
-/* MXVR_ROUTING_10 Masks */
-
-#define MUTE_CH40       0x00000080lu
-#define MUTE_CH41       0x00008000lu
-#define MUTE_CH42       0x00800000lu
-#define MUTE_CH43       0x80000000lu
-
-#define TX_CH40         0x0000007Flu
-#define TX_CH41         0x00007F00lu
-#define TX_CH42         0x007F0000lu
-#define TX_CH43         0x7F000000lu
-
-
-/* MXVR_ROUTING_11 Masks */
-
-#define MUTE_CH44       0x00000080lu
-#define MUTE_CH45       0x00008000lu
-#define MUTE_CH46       0x00800000lu
-#define MUTE_CH47       0x80000000lu
-
-#define TX_CH44         0x0000007Flu
-#define TX_CH45         0x00007F00lu
-#define TX_CH46         0x007F0000lu
-#define TX_CH47         0x7F000000lu
-
-
-/* MXVR_ROUTING_12 Masks */
-
-#define MUTE_CH48       0x00000080lu
-#define MUTE_CH49       0x00008000lu
-#define MUTE_CH50       0x00800000lu
-#define MUTE_CH51       0x80000000lu
-
-#define TX_CH48         0x0000007Flu
-#define TX_CH49         0x00007F00lu
-#define TX_CH50         0x007F0000lu
-#define TX_CH51         0x7F000000lu
-
-
-/* MXVR_ROUTING_13 Masks */
-
-#define MUTE_CH52       0x00000080lu
-#define MUTE_CH53       0x00008000lu
-#define MUTE_CH54       0x00800000lu
-#define MUTE_CH55       0x80000000lu
-
-#define TX_CH52         0x0000007Flu
-#define TX_CH53         0x00007F00lu
-#define TX_CH54         0x007F0000lu
-#define TX_CH55         0x7F000000lu
-
-
-/* MXVR_ROUTING_14 Masks */
-
-#define MUTE_CH56       0x00000080lu
-#define MUTE_CH57       0x00008000lu
-#define MUTE_CH58       0x00800000lu
-#define MUTE_CH59       0x80000000lu
-
-#define TX_CH56         0x0000007Flu
-#define TX_CH57         0x00007F00lu
-#define TX_CH58         0x007F0000lu
-#define TX_CH59         0x7F000000lu
-
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-
-
 /* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
 /* CAN_CONTROL Masks                                     */
 #define SRS                     0x0001  /* Software Reset */