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authorSonic Zhang <sonic.zhang@analog.com>2009-04-07 11:52:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-07 11:44:05 -0400
commitd307d36adeaa70074773b3e5eab8d7e1beb008a4 (patch)
tree2a51257927be7c1a99ffb38b4752e0a4b56edc2a /arch/blackfin/mach-bf538/include
parent6f95570e407d03c5140a220e054f9b18abdc7041 (diff)
tty: Blackin CTS/RTS
Both software emulated and hardware based CTS and RTS are enabled in serial driver. The CTS RTS PIN connection on BF548 UART port is defined as a modem device not as a host device. In order to test it under Linux, please nake a cross UART cable to exchange CTS and RTS signal. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 3c2811ebecdd..c536551eb4b8 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -53,9 +53,9 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) 56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61 61
@@ -87,6 +87,7 @@
87struct bfin_serial_port { 87struct bfin_serial_port {
88 struct uart_port port; 88 struct uart_port port;
89 unsigned int old_status; 89 unsigned int old_status;
90 int status_irq;
90 unsigned int lsr; 91 unsigned int lsr;
91#ifdef CONFIG_SERIAL_BFIN_DMA 92#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done; 93 int tx_done;
@@ -125,6 +126,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
125struct bfin_serial_res { 126struct bfin_serial_res {
126 unsigned long uart_base_addr; 127 unsigned long uart_base_addr;
127 int uart_irq; 128 int uart_irq;
129 int uart_status_irq;
128#ifdef CONFIG_SERIAL_BFIN_DMA 130#ifdef CONFIG_SERIAL_BFIN_DMA
129 unsigned int uart_tx_dma_channel; 131 unsigned int uart_tx_dma_channel;
130 unsigned int uart_rx_dma_channel; 132 unsigned int uart_rx_dma_channel;
@@ -140,6 +142,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
140 { 142 {
141 0xFFC00400, 143 0xFFC00400,
142 IRQ_UART0_RX, 144 IRQ_UART0_RX,
145 IRQ_UART0_ERROR,
143#ifdef CONFIG_SERIAL_BFIN_DMA 146#ifdef CONFIG_SERIAL_BFIN_DMA
144 CH_UART0_TX, 147 CH_UART0_TX,
145 CH_UART0_RX, 148 CH_UART0_RX,
@@ -154,6 +157,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 { 157 {
155 0xFFC02000, 158 0xFFC02000,
156 IRQ_UART1_RX, 159 IRQ_UART1_RX,
160 IRQ_UART1_ERROR,
157#ifdef CONFIG_SERIAL_BFIN_DMA 161#ifdef CONFIG_SERIAL_BFIN_DMA
158 CH_UART1_TX, 162 CH_UART1_TX,
159 CH_UART1_RX, 163 CH_UART1_RX,