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authorMike Frysinger <vapier@gentoo.org>2009-09-27 23:16:01 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:02 -0500
commitb1524e29e318e79b2d04bcbd651a7af8dff32bb3 (patch)
tree7e138995fa0f8727b61fdada567cbda3f95e1670 /arch/blackfin/mach-bf538/include
parent709465d6ea0466454ef547e7d1065db2b23033a9 (diff)
Blackfin: bfin_serial.h: unify heavily duplicated serial code
Each Blackfin port has been duplicating UART structures and defines when there really is no need for it. So start a new bfin_serial.h header to unify all these pieces and give ourselves a fresh start. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h77
4 files changed, 16 insertions, 163 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..c66e2760aad3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 3
13
14#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 5c148142f041..beb502e9cb33 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
160}; 89};
161 90
162#define DRIVER_NAME "bfin-uart" 91#define DRIVER_NAME "bfin-uart"
92
93#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 08b5eabb1ed5..b82cb0248ab6 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -22,19 +22,4 @@
22#endif 22#endif
23#endif 23#endif
24 24
25#define BFIN_UART_NR_PORTS 3
26
27#define OFFSET_THR 0x00 /* Transmit Holding register */
28#define OFFSET_RBR 0x00 /* Receive Buffer register */
29#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
30#define OFFSET_IER 0x04 /* Interrupt Enable Register */
31#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
32#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
33#define OFFSET_LCR 0x0C /* Line Control Register */
34#define OFFSET_MCR 0x10 /* Modem Control Register */
35#define OFFSET_LSR 0x14 /* Line Status Register */
36#define OFFSET_MSR 0x18 /* Modem Status Register */
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */
39
40#endif 25#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 7a8ac5f44204..0ef05c9845b8 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1534,83 +1534,6 @@
1534#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1534#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1535#endif /* _MISRA_RULES */ 1535#endif /* _MISRA_RULES */
1536 1536
1537
1538/* ***************************** UART CONTROLLER MASKS ********************** */
1539/* UARTx_LCR Register */
1540#ifdef _MISRA_RULES
1541#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
1542#else
1543#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1544#endif /* _MISRA_RULES */
1545#define STB 0x04 /* Stop Bits */
1546#define PEN 0x08 /* Parity Enable */
1547#define EPS 0x10 /* Even Parity Select */
1548#define STP 0x20 /* Stick Parity */
1549#define SB 0x40 /* Set Break */
1550#define DLAB 0x80 /* Divisor Latch Access */
1551
1552#define DLAB_P 0x07
1553#define SB_P 0x06
1554#define STP_P 0x05
1555#define EPS_P 0x04
1556#define PEN_P 0x03
1557#define STB_P 0x02
1558#define WLS_P1 0x01
1559#define WLS_P0 0x00
1560
1561/* UARTx_MCR Register */
1562#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1563#define LOOP_ENA_P 0x04
1564/* Deprecated UARTx_MCR Mask */
1565
1566/* UARTx_LSR Register */
1567#define DR 0x01 /* Data Ready */
1568#define OE 0x02 /* Overrun Error */
1569#define PE 0x04 /* Parity Error */
1570#define FE 0x08 /* Framing Error */
1571#define BI 0x10 /* Break Interrupt */
1572#define THRE 0x20 /* THR Empty */
1573#define TEMT 0x40 /* TSR and UART_THR Empty */
1574
1575#define TEMP_P 0x06
1576#define THRE_P 0x05
1577#define BI_P 0x04
1578#define FE_P 0x03
1579#define PE_P 0x02
1580#define OE_P 0x01
1581#define DR_P 0x00
1582
1583/* UARTx_IER Register */
1584#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1585#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1586#define ELSI 0x04 /* Enable RX Status Interrupt */
1587
1588#define ELSI_P 0x02
1589#define ETBEI_P 0x01
1590#define ERBFI_P 0x00
1591
1592/* UARTx_IIR Register */
1593#define NINT 0x01
1594#define STATUS_P1 0x02
1595#define STATUS_P0 0x01
1596#define NINT_P 0x00
1597
1598/* UARTx_GCTL Register */
1599#define UCEN 0x01 /* Enable UARTx Clocks */
1600#define IREN 0x02 /* Enable IrDA Mode */
1601#define TPOLC 0x04 /* IrDA TX Polarity Change */
1602#define RPOLC 0x08 /* IrDA RX Polarity Change */
1603#define FPE 0x10 /* Force Parity Error On Transmit */
1604#define FFE 0x20 /* Force Framing Error On Transmit */
1605
1606#define FFE_P 0x05
1607#define FPE_P 0x04
1608#define RPOLC_P 0x03
1609#define TPOLC_P 0x02
1610#define IREN_P 0x01
1611#define UCEN_P 0x00
1612
1613
1614/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1537/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1615/* PPI_CONTROL Masks */ 1538/* PPI_CONTROL Masks */
1616#define PORT_EN 0x0001 /* PPI Port Enable */ 1539#define PORT_EN 0x0001 /* PPI Port Enable */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 17:11:41 -0500