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authorMike Frysinger <vapier@gentoo.org>2009-11-17 10:40:30 -0500
committerMike Frysinger <vapier@gentoo.org>2010-08-27 15:58:27 -0400
commitac0a5042befbe4396b7650358ad35298512d683d (patch)
treeed0ce62c139f88153a4f7acd787e3c82d761298c /arch/blackfin/mach-bf538/include
parentd4348c678977c7093438bbbf2067c49396ae941b (diff)
Blackfin: punt duplicate SPORT MMR defines
The common bfin_sport.h header now has unified definitions of these, so stop polluting the global namespace. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h107
1 files changed, 0 insertions, 107 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index b674a1c4aef1..fe43062b4975 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1610,113 +1610,6 @@
1610#define UCEN_P 0x00 1610#define UCEN_P 0x00
1611 1611
1612 1612
1613/* ********** SERIAL PORT MASKS ********************** */
1614/* SPORTx_TCR1 Masks */
1615#define TSPEN 0x0001 /* TX enable */
1616#define ITCLK 0x0002 /* Internal TX Clock Select */
1617#define TDTYPE 0x000C /* TX Data Formatting Select */
1618#define DTYPE_NORM 0x0000 /* Data Format Normal */
1619#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1620#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1621#define TLSBIT 0x0010 /* TX Bit Order */
1622#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1623#define TFSR 0x0400 /* TX Frame Sync Required Select */
1624#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1625#define LTFS 0x1000 /* Low TX Frame Sync Select */
1626#define LATFS 0x2000 /* Late TX Frame Sync Select */
1627#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1628/* SPORTx_RCR1 Deprecated Masks */
1629#define TULAW DTYPE_ULAW /* Compand Using u-Law */
1630#define TALAW DTYPE_ALAW /* Compand Using A-Law */
1631
1632/* SPORTx_TCR2 Masks */
1633#ifdef _MISRA_RULES
1634#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
1635#else
1636#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1637#endif /* _MISRA_RULES */
1638#define TXSE 0x0100 /*TX Secondary Enable */
1639#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
1640#define TRFST 0x0400 /*TX Right-First Data Order */
1641
1642/* SPORTx_RCR1 Masks */
1643#define RSPEN 0x0001 /* RX enable */
1644#define IRCLK 0x0002 /* Internal RX Clock Select */
1645#define RDTYPE 0x000C /* RX Data Formatting Select */
1646#define DTYPE_NORM 0x0000 /* no companding */
1647#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1648#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1649#define RLSBIT 0x0010 /* RX Bit Order */
1650#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1651#define RFSR 0x0400 /* RX Frame Sync Required Select */
1652#define LRFS 0x1000 /* Low RX Frame Sync Select */
1653#define LARFS 0x2000 /* Late RX Frame Sync Select */
1654#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1655/* SPORTx_RCR1 Deprecated Masks */
1656#define RULAW DTYPE_ULAW /* Compand Using u-Law */
1657#define RALAW DTYPE_ALAW /* Compand Using A-Law */
1658
1659/* SPORTx_RCR2 Masks */
1660#ifdef _MISRA_RULES
1661#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
1662#else
1663#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1664#endif /* _MISRA_RULES */
1665#define RXSE 0x0100 /*RX Secondary Enable */
1666#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
1667#define RRFST 0x0400 /*Right-First Data Order */
1668
1669/*SPORTx_STAT Masks */
1670#define RXNE 0x0001 /*RX FIFO Not Empty Status */
1671#define RUVF 0x0002 /*RX Underflow Status */
1672#define ROVF 0x0004 /*RX Overflow Status */
1673#define TXF 0x0008 /*TX FIFO Full Status */
1674#define TUVF 0x0010 /*TX Underflow Status */
1675#define TOVF 0x0020 /*TX Overflow Status */
1676#define TXHRE 0x0040 /*TX Hold Register Empty */
1677
1678/*SPORTx_MCMC1 Masks */
1679#define WOFF 0x000003FF /*Multichannel Window Offset Field */
1680/* SPORTx_MCMC1 Macros */
1681#ifdef _MISRA_RULES
1682#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
1683/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1684#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1685#else
1686#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1687/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1688#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1689#endif /* _MISRA_RULES */
1690
1691
1692/*SPORTx_MCMC2 Masks */
1693#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
1694#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1695#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1696#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1697#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
1698#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
1699#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
1700#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
1701#define MFD 0xF000 /*Multichannel Frame Delay */
1702#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1703#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1704#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1705#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1706#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1707#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1708#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1709#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1710#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1711#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1712#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1713#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1714#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1715#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1716#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1717#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1718
1719
1720/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1613/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1721/* PPI_CONTROL Masks */ 1614/* PPI_CONTROL Masks */
1722#define PORT_EN 0x0001 /* PPI Port Enable */ 1615#define PORT_EN 0x0001 /* PPI Port Enable */