diff options
author | Mike Frysinger <vapier@gentoo.org> | 2011-03-30 02:54:33 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 08:13:42 -0400 |
commit | 6adc521e7127732512ebd7fcfd3926d7970a82e1 (patch) | |
tree | 1de12c99fde995c82a8cd7487f45c6f6ea0b4ef4 /arch/blackfin/mach-bf538/include | |
parent | 6b108049d67090988fbb0b9d9905ffca114b6ff1 (diff) |
Blackfin: unify core IRQ definitions
Start a new common IRQ header and move all of the CEC pieces there. This
lets the individual part headers worry just about its SIC defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include')
-rw-r--r-- | arch/blackfin/mach-bf538/include/mach/irq.h | 42 |
1 files changed, 1 insertions, 41 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h index 7a479d224dc7..08d47675d71f 100644 --- a/arch/blackfin/mach-bf538/include/mach/irq.h +++ b/arch/blackfin/mach-bf538/include/mach/irq.h | |||
@@ -7,39 +7,10 @@ | |||
7 | #ifndef _BF538_IRQ_H_ | 7 | #ifndef _BF538_IRQ_H_ |
8 | #define _BF538_IRQ_H_ | 8 | #define _BF538_IRQ_H_ |
9 | 9 | ||
10 | /* | 10 | #include <mach-common/irq.h> |
11 | * Interrupt source definitions | ||
12 | Event Source Core Event Name | ||
13 | Core Emulation ** | ||
14 | Events (highest priority) EMU 0 | ||
15 | Reset RST 1 | ||
16 | NMI NMI 2 | ||
17 | Exception EVX 3 | ||
18 | Reserved -- 4 | ||
19 | Hardware Error IVHW 5 | ||
20 | Core Timer IVTMR 6 * | ||
21 | |||
22 | ..... | ||
23 | |||
24 | Software Interrupt 1 IVG14 31 | ||
25 | Software Interrupt 2 -- | ||
26 | (lowest priority) IVG15 32 * | ||
27 | */ | ||
28 | 11 | ||
29 | #define NR_PERI_INTS (2 * 32) | 12 | #define NR_PERI_INTS (2 * 32) |
30 | 13 | ||
31 | /* The ABSTRACT IRQ definitions */ | ||
32 | /** the first seven of the following are fixed, the rest you change if you need to **/ | ||
33 | #define IRQ_EMU 0 /* Emulation */ | ||
34 | #define IRQ_RST 1 /* reset */ | ||
35 | #define IRQ_NMI 2 /* Non Maskable */ | ||
36 | #define IRQ_EVX 3 /* Exception */ | ||
37 | #define IRQ_UNUSED 4 /* - unused interrupt */ | ||
38 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
39 | #define IRQ_CORETMR 6 /* Core timer */ | ||
40 | |||
41 | #define BFIN_IRQ(x) ((x) + 7) | ||
42 | |||
43 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ | 14 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
44 | #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ | 15 | #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ |
45 | #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ | 16 | #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ |
@@ -111,17 +82,6 @@ | |||
111 | #define GPIO_IRQ_BASE IRQ_PF0 | 82 | #define GPIO_IRQ_BASE IRQ_PF0 |
112 | 83 | ||
113 | #define NR_MACH_IRQS (IRQ_PF15 + 1) | 84 | #define NR_MACH_IRQS (IRQ_PF15 + 1) |
114 | #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) | ||
115 | |||
116 | #define IVG7 7 | ||
117 | #define IVG8 8 | ||
118 | #define IVG9 9 | ||
119 | #define IVG10 10 | ||
120 | #define IVG11 11 | ||
121 | #define IVG12 12 | ||
122 | #define IVG13 13 | ||
123 | #define IVG14 14 | ||
124 | #define IVG15 15 | ||
125 | 85 | ||
126 | /* IAR0 BIT FIELDS */ | 86 | /* IAR0 BIT FIELDS */ |
127 | #define IRQ_PLL_WAKEUP_POS 0 | 87 | #define IRQ_PLL_WAKEUP_POS 0 |