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authorMike Frysinger <vapier@gentoo.org>2009-07-26 20:44:25 -0400
committerMike Frysinger <vapier@gentoo.org>2009-09-16 22:09:55 -0400
commit8d71e075966e29232cd38d8ca6335047a164c1dc (patch)
tree8e958abca578238c383ab99d8b2b170d8648c12a /arch/blackfin/mach-bf537
parent61f09b5a09fb3962bbd3990a9a5a8470197955bb (diff)
Blackfin: drop unused MMR defines that only cause bad code to be written
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r--arch/blackfin/mach-bf537/dma.c8
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h90
2 files changed, 4 insertions, 94 deletions
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 81185051de91..d23fc0edf2b9 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -96,12 +96,12 @@ int channel2irq(unsigned int channel)
96 ret_irq = IRQ_SPI; 96 ret_irq = IRQ_SPI;
97 break; 97 break;
98 98
99 case CH_UART_RX: 99 case CH_UART0_RX:
100 ret_irq = IRQ_UART_RX; 100 ret_irq = IRQ_UART0_RX;
101 break; 101 break;
102 102
103 case CH_UART_TX: 103 case CH_UART0_TX:
104 ret_irq = IRQ_UART_TX; 104 ret_irq = IRQ_UART0_TX;
105 break; 105 break;
106 106
107 case CH_MEM_STREAM0_SRC: 107 case CH_MEM_STREAM0_SRC:
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index f5e5015ad831..9ee8834c8f1a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -45,96 +45,11 @@
45#if !defined(__ASSEMBLY__) 45#if !defined(__ASSEMBLY__)
46#include "cdefBF534.h" 46#include "cdefBF534.h"
47 47
48/* UART 0*/
49#define bfin_read_UART_THR() bfin_read_UART0_THR()
50#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
51#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
52#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
53#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
54#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
55#define bfin_read_UART_IER() bfin_read_UART0_IER()
56#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
57#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
58#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
59#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
60#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
61#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
62#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
63#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
64#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
65#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
66#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
67#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
68#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
69#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
70#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
71
72#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 48#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
73#include "cdefBF537.h" 49#include "cdefBF537.h"
74#endif 50#endif
75#endif 51#endif
76 52
77/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
78
79/* UART_IIR Register */
80#define STATUS(x) ((x << 1) & 0x06)
81#define STATUS_P1 0x02
82#define STATUS_P0 0x01
83
84/* DMA Channel */
85#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
86#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
87#define CH_UART_RX CH_UART0_RX
88#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
89#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
90#define CH_UART_TX CH_UART0_TX
91
92/* System Interrupt Controller */
93#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
94#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
95#define IRQ_UART_RX IRQ_UART0_RX
96#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
97#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
98#define IRQ_UART_TX IRQ_UART0_TX
99#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
100#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
101#define IRQ_UART_ERROR IRQ_UART0_ERROR
102
103/* MMR Registers*/
104#define bfin_read_UART_THR() bfin_read_UART0_THR()
105#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
106#define BFIN_UART_THR UART0_THR
107#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
108#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
109#define BFIN_UART_RBR UART0_RBR
110#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
111#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
112#define BFIN_UART_DLL UART0_DLL
113#define bfin_read_UART_IER() bfin_read_UART0_IER()
114#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
115#define BFIN_UART_IER UART0_IER
116#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
117#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
118#define BFIN_UART_DLH UART0_DLH
119#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
120#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
121#define BFIN_UART_IIR UART0_IIR
122#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
123#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
124#define BFIN_UART_LCR UART0_LCR
125#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
126#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
127#define BFIN_UART_MCR UART0_MCR
128#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
129#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
130#define BFIN_UART_LSR UART0_LSR
131#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
132#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
133#define BFIN_UART_SCR UART0_SCR
134#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
135#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
136#define BFIN_UART_GCTL UART0_GCTL
137
138#define BFIN_UART_NR_PORTS 2 53#define BFIN_UART_NR_PORTS 2
139 54
140#define OFFSET_THR 0x00 /* Transmit Holding register */ 55#define OFFSET_THR 0x00 /* Transmit Holding register */
@@ -150,11 +65,6 @@
150#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 65#define OFFSET_SCR 0x1C /* SCR Scratch Register */
151#define OFFSET_GCTL 0x24 /* Global Control Register */ 66#define OFFSET_GCTL 0x24 /* Global Control Register */
152 67
153/* DPMC*/
154#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
155#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
156#define STOPCK_OFF STOPCK
157
158/* PLL_DIV Masks */ 68/* PLL_DIV Masks */
159#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 69#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
160#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 70#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */