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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/blackfin/mach-bf537
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/blackfin/mach-bf537')
-rw-r--r--arch/blackfin/mach-bf537/Kconfig4
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig6
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c48
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c48
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c398
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c36
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c40
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c753
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c48
-rw-r--r--arch/blackfin/mach-bf537/dma.c2
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h10
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h147
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h38
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h71
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h175
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h365
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c163
23 files changed, 1608 insertions, 774 deletions
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index d81224f9d723..08b2b343ccec 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -14,8 +14,8 @@ config IRQ_DMA_ERROR
14 int "IRQ_DMA_ERROR Generic" 14 int "IRQ_DMA_ERROR Generic"
15 default 7 15 default 7
16config IRQ_ERROR 16config IRQ_ERROR
17 int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" 17 int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
18 default 7 18 default 11
19config IRQ_RTC 19config IRQ_RTC
20 int "IRQ_RTC" 20 int "IRQ_RTC"
21 default 8 21 default 8
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
39 help 39 help
40 Board supply package for CSP Minotaur 40 Board supply package for CSP Minotaur
41 41
42config DNP5370
43 bool "SSV Dil/NetPC DNP/5370"
44 depends on (BF537)
45 help
46 Board supply package for DNP/5370 DIL64 module
47
42endchoice 48endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
9obj-$(CONFIG_PNAV10) += pnav10.o 9obj-$(CONFIG_PNAV10) += pnav10.o
10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o 10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
11obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index d35fc5fe4c2b..d582b810e7a7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -73,7 +73,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
73}; 73};
74#endif 74#endif
75 75
76#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 76#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
77static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 77static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
78 .enable_dma = 0, 78 .enable_dma = 0,
79 .bits_per_word = 16, 79 .bits_per_word = 16,
@@ -112,12 +112,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
112 }, 112 },
113#endif 113#endif
114 114
115#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 115#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
116 { 116 {
117 .modalias = "ad1836", 117 .modalias = "ad183x",
118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
119 .bus_num = 0, 119 .bus_num = 0,
120 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 120 .chip_select = 4,
121 .controller_data = &ad1836_spi_chip_info, 121 .controller_data = &ad1836_spi_chip_info,
122 }, 122 },
123#endif 123#endif
@@ -229,7 +229,7 @@ static struct resource isp1362_hcd_resources[] = {
229 }, { 229 }, {
230 .start = IRQ_PG15, 230 .start = IRQ_PG15,
231 .end = IRQ_PG15, 231 .end = IRQ_PG15,
232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
233 }, 233 },
234}; 234};
235 235
@@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
373#endif 373#endif
374}; 374};
375 375
376unsigned short bfin_uart0_peripherals[] = { 376static unsigned short bfin_uart0_peripherals[] = {
377 P_UART0_TX, P_UART0_RX, 0 377 P_UART0_TX, P_UART0_RX, 0
378}; 378};
379 379
@@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
434#endif 434#endif
435}; 435};
436 436
437unsigned short bfin_uart1_peripherals[] = { 437static unsigned short bfin_uart1_peripherals[] = {
438 P_UART1_TX, P_UART1_RX, 0 438 P_UART1_TX, P_UART1_RX, 0
439}; 439};
440 440
@@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
545 }, 545 },
546}; 546};
547 547
548unsigned short bfin_sport0_peripherals[] = { 548static unsigned short bfin_sport0_peripherals[] = {
549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
551}; 551};
552 552
553static struct platform_device bfin_sport0_uart_device = { 553static struct platform_device bfin_sport0_uart_device = {
@@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
579 }, 579 },
580}; 580};
581 581
582unsigned short bfin_sport1_peripherals[] = { 582static unsigned short bfin_sport1_peripherals[] = {
583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
585}; 585};
586 586
587static struct platform_device bfin_sport1_uart_device = { 587static struct platform_device bfin_sport1_uart_device = {
@@ -597,13 +597,35 @@ static struct platform_device bfin_sport1_uart_device = {
597#endif 597#endif
598 598
599#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 599#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
600#include <linux/bfin_mac.h>
601static const unsigned short bfin_mac_peripherals[] = P_MII0;
602
603static struct bfin_phydev_platform_data bfin_phydev_data[] = {
604 {
605 .addr = 1,
606 .irq = IRQ_MAC_PHYINT,
607 },
608};
609
610static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
611 .phydev_number = 1,
612 .phydev_data = bfin_phydev_data,
613 .phy_mode = PHY_INTERFACE_MODE_MII,
614 .mac_peripherals = bfin_mac_peripherals,
615};
616
600static struct platform_device bfin_mii_bus = { 617static struct platform_device bfin_mii_bus = {
601 .name = "bfin_mii_bus", 618 .name = "bfin_mii_bus",
619 .dev = {
620 .platform_data = &bfin_mii_bus_data,
621 }
602}; 622};
603 623
604static struct platform_device bfin_mac_device = { 624static struct platform_device bfin_mac_device = {
605 .name = "bfin_mac", 625 .name = "bfin_mac",
606 .dev.platform_data = &bfin_mii_bus, 626 .dev = {
627 .platform_data = &bfin_mii_bus,
628 }
607}; 629};
608#endif 630#endif
609 631
@@ -753,7 +775,7 @@ static int __init cm_bf537e_init(void)
753#endif 775#endif
754 776
755#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 777#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
756 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 778 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
757#endif 779#endif
758 return 0; 780 return 0;
759} 781}
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index d464ad5b72b2..cbb8098604c5 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
74}; 74};
75#endif 75#endif
76 76
77#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0, 79 .enable_dma = 0,
80 .bits_per_word = 16, 80 .bits_per_word = 16,
@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
113 }, 113 },
114#endif 114#endif
115 115
116#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 117 {
118 .modalias = "ad1836", 118 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 120 .bus_num = 0,
121 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 121 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info, 122 .controller_data = &ad1836_spi_chip_info,
123 }, 123 },
124#endif 124#endif
@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
230 }, { 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
234 }, 234 },
235}; 235};
236 236
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
510 }, 510 },
511}; 511};
512 512
513unsigned short bfin_sport0_peripherals[] = { 513static unsigned short bfin_sport0_peripherals[] = {
514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
516}; 516};
517 517
518static struct platform_device bfin_sport0_uart_device = { 518static struct platform_device bfin_sport0_uart_device = {
@@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
544 }, 544 },
545}; 545};
546 546
547unsigned short bfin_sport1_peripherals[] = { 547static unsigned short bfin_sport1_peripherals[] = {
548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
550}; 550};
551 551
552static struct platform_device bfin_sport1_uart_device = { 552static struct platform_device bfin_sport1_uart_device = {
@@ -562,13 +562,35 @@ static struct platform_device bfin_sport1_uart_device = {
562#endif 562#endif
563 563
564#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 564#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
565#include <linux/bfin_mac.h>
566static const unsigned short bfin_mac_peripherals[] = P_MII0;
567
568static struct bfin_phydev_platform_data bfin_phydev_data[] = {
569 {
570 .addr = 1,
571 .irq = IRQ_MAC_PHYINT,
572 },
573};
574
575static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
576 .phydev_number = 1,
577 .phydev_data = bfin_phydev_data,
578 .phy_mode = PHY_INTERFACE_MODE_MII,
579 .mac_peripherals = bfin_mac_peripherals,
580};
581
565static struct platform_device bfin_mii_bus = { 582static struct platform_device bfin_mii_bus = {
566 .name = "bfin_mii_bus", 583 .name = "bfin_mii_bus",
584 .dev = {
585 .platform_data = &bfin_mii_bus_data,
586 }
567}; 587};
568 588
569static struct platform_device bfin_mac_device = { 589static struct platform_device bfin_mac_device = {
570 .name = "bfin_mac", 590 .name = "bfin_mac",
571 .dev.platform_data = &bfin_mii_bus, 591 .dev = {
592 .platform_data = &bfin_mii_bus,
593 }
572}; 594};
573#endif 595#endif
574 596
@@ -718,7 +740,7 @@ static int __init cm_bf537u_init(void)
718#endif 740#endif
719 741
720#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 742#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
721 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 743 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
722#endif 744#endif
723 return 0; 745 return 0;
724} 746}
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..6b4ff4605bff
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,398 @@
1/*
2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
3 *
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
6 *
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/plat-ram.h>
22#include <linux/mtd/physmap.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/i2c.h>
28#include <linux/spi/mmc_spi.h>
29#include <linux/phy.h>
30#include <asm/dma.h>
31#include <asm/bfin5xx_spi.h>
32#include <asm/reboot.h>
33#include <asm/portmux.h>
34#include <asm/dpmc.h>
35
36/*
37 * Name the Board for the /proc/cpuinfo
38 */
39const char bfin_board_name[] = "DNP/5370";
40#define FLASH_MAC 0x202f0000
41#define CONFIG_MTD_PHYSMAP_LEN 0x300000
42
43#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44static struct platform_device rtc_device = {
45 .name = "rtc-bfin",
46 .id = -1,
47};
48#endif
49
50#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51#include <linux/bfin_mac.h>
52static const unsigned short bfin_mac_peripherals[] = P_RMII0;
53
54static struct bfin_phydev_platform_data bfin_phydev_data[] = {
55 {
56 .addr = 1,
57 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
58 },
59};
60
61static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
62 .phydev_number = 1,
63 .phydev_data = bfin_phydev_data,
64 .phy_mode = PHY_INTERFACE_MODE_RMII,
65 .mac_peripherals = bfin_mac_peripherals,
66};
67
68static struct platform_device bfin_mii_bus = {
69 .name = "bfin_mii_bus",
70 .dev = {
71 .platform_data = &bfin_mii_bus_data,
72 }
73};
74
75static struct platform_device bfin_mac_device = {
76 .name = "bfin_mac",
77 .dev = {
78 .platform_data = &bfin_mii_bus,
79 }
80};
81#endif
82
83#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
84static struct mtd_partition asmb_flash_partitions[] = {
85 {
86 .name = "bootloader(nor)",
87 .size = 0x30000,
88 .offset = 0,
89 }, {
90 .name = "linux kernel and rootfs(nor)",
91 .size = 0x300000 - 0x30000 - 0x10000,
92 .offset = MTDPART_OFS_APPEND,
93 }, {
94 .name = "MAC address(nor)",
95 .size = 0x10000,
96 .offset = MTDPART_OFS_APPEND,
97 .mask_flags = MTD_WRITEABLE,
98 }
99};
100
101static struct physmap_flash_data asmb_flash_data = {
102 .width = 1,
103 .parts = asmb_flash_partitions,
104 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
105};
106
107static struct resource asmb_flash_resource = {
108 .start = 0x20000000,
109 .end = 0x202fffff,
110 .flags = IORESOURCE_MEM,
111};
112
113/* 4 MB NOR flash attached to async memory banks 0-2,
114 * therefore only 3 MB visible.
115 */
116static struct platform_device asmb_flash_device = {
117 .name = "physmap-flash",
118 .id = 0,
119 .dev = {
120 .platform_data = &asmb_flash_data,
121 },
122 .num_resources = 1,
123 .resource = &asmb_flash_resource,
124};
125#endif
126
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128
129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
130
131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132 .enable_dma = 0, /* use no dma transfer with this chip*/
133 .bits_per_word = 8,
134};
135
136#endif
137
138#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
139/* This mapping is for at45db642 it has 1056 page size,
140 * partition size and offset should be page aligned
141 */
142static struct mtd_partition bfin_spi_dataflash_partitions[] = {
143 {
144 .name = "JFFS2 dataflash(nor)",
145#ifdef CONFIG_MTD_PAGESIZE_1024
146 .offset = 0x40000,
147 .size = 0x7C0000,
148#else
149 .offset = 0x0,
150 .size = 0x840000,
151#endif
152 }
153};
154
155static struct flash_platform_data bfin_spi_dataflash_data = {
156 .name = "mtd_dataflash",
157 .parts = bfin_spi_dataflash_partitions,
158 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
159 .type = "mtd_dataflash",
160};
161
162static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
163 .enable_dma = 0, /* use no dma transfer with this chip*/
164 .bits_per_word = 8,
165};
166#endif
167
168static struct spi_board_info bfin_spi_board_info[] __initdata = {
169/* SD/MMC card reader at SPI bus */
170#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
171 {
172 .modalias = "mmc_spi",
173 .max_speed_hz = 20000000,
174 .bus_num = 0,
175 .chip_select = 1,
176 .controller_data = &mmc_spi_chip_info,
177 .mode = SPI_MODE_3,
178 },
179#endif
180
181/* 8 Megabyte Atmel NOR flash chip at SPI bus */
182#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
183 {
184 .modalias = "mtd_dataflash",
185 .max_speed_hz = 16700000,
186 .bus_num = 0,
187 .chip_select = 2,
188 .platform_data = &bfin_spi_dataflash_data,
189 .controller_data = &spi_dataflash_chip_info,
190 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
191 },
192#endif
193};
194
195/* SPI controller data */
196/* SPI (0) */
197static struct resource bfin_spi0_resource[] = {
198 [0] = {
199 .start = SPI0_REGBASE,
200 .end = SPI0_REGBASE + 0xFF,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = CH_SPI,
205 .end = CH_SPI,
206 .flags = IORESOURCE_DMA,
207 },
208 [2] = {
209 .start = IRQ_SPI,
210 .end = IRQ_SPI,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct bfin5xx_spi_master spi_bfin_master_info = {
216 .num_chipselect = 8,
217 .enable_dma = 1, /* master has the ability to do dma transfer */
218 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
219};
220
221static struct platform_device spi_bfin_master_device = {
222 .name = "bfin-spi",
223 .id = 0, /* Bus number */
224 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
225 .resource = bfin_spi0_resource,
226 .dev = {
227 .platform_data = &spi_bfin_master_info, /* Passed to driver */
228 },
229};
230#endif
231
232#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
233#ifdef CONFIG_SERIAL_BFIN_UART0
234static struct resource bfin_uart0_resources[] = {
235 {
236 .start = UART0_THR,
237 .end = UART0_GCTL+2,
238 .flags = IORESOURCE_MEM,
239 },
240 {
241 .start = IRQ_UART0_RX,
242 .end = IRQ_UART0_RX+1,
243 .flags = IORESOURCE_IRQ,
244 },
245 {
246 .start = IRQ_UART0_ERROR,
247 .end = IRQ_UART0_ERROR,
248 .flags = IORESOURCE_IRQ,
249 },
250 {
251 .start = CH_UART0_TX,
252 .end = CH_UART0_TX,
253 .flags = IORESOURCE_DMA,
254 },
255 {
256 .start = CH_UART0_RX,
257 .end = CH_UART0_RX,
258 .flags = IORESOURCE_DMA,
259 },
260};
261
262static unsigned short bfin_uart0_peripherals[] = {
263 P_UART0_TX, P_UART0_RX, 0
264};
265
266static struct platform_device bfin_uart0_device = {
267 .name = "bfin-uart",
268 .id = 0,
269 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
270 .resource = bfin_uart0_resources,
271 .dev = {
272 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
273 },
274};
275#endif
276
277#ifdef CONFIG_SERIAL_BFIN_UART1
278static struct resource bfin_uart1_resources[] = {
279 {
280 .start = UART1_THR,
281 .end = UART1_GCTL+2,
282 .flags = IORESOURCE_MEM,
283 },
284 {
285 .start = IRQ_UART1_RX,
286 .end = IRQ_UART1_RX+1,
287 .flags = IORESOURCE_IRQ,
288 },
289 {
290 .start = IRQ_UART1_ERROR,
291 .end = IRQ_UART1_ERROR,
292 .flags = IORESOURCE_IRQ,
293 },
294 {
295 .start = CH_UART1_TX,
296 .end = CH_UART1_TX,
297 .flags = IORESOURCE_DMA,
298 },
299 {
300 .start = CH_UART1_RX,
301 .end = CH_UART1_RX,
302 .flags = IORESOURCE_DMA,
303 },
304};
305
306static unsigned short bfin_uart1_peripherals[] = {
307 P_UART1_TX, P_UART1_RX, 0
308};
309
310static struct platform_device bfin_uart1_device = {
311 .name = "bfin-uart",
312 .id = 1,
313 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
314 .resource = bfin_uart1_resources,
315 .dev = {
316 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
317 },
318};
319#endif
320#endif
321
322#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
323static struct resource bfin_twi0_resource[] = {
324 [0] = {
325 .start = TWI0_REGBASE,
326 .end = TWI0_REGBASE + 0xff,
327 .flags = IORESOURCE_MEM,
328 },
329 [1] = {
330 .start = IRQ_TWI,
331 .end = IRQ_TWI,
332 .flags = IORESOURCE_IRQ,
333 },
334};
335
336static struct platform_device i2c_bfin_twi_device = {
337 .name = "i2c-bfin-twi",
338 .id = 0,
339 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
340 .resource = bfin_twi0_resource,
341};
342#endif
343
344static struct platform_device *dnp5370_devices[] __initdata = {
345
346#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
347#ifdef CONFIG_SERIAL_BFIN_UART0
348 &bfin_uart0_device,
349#endif
350#ifdef CONFIG_SERIAL_BFIN_UART1
351 &bfin_uart1_device,
352#endif
353#endif
354
355#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
356 &asmb_flash_device,
357#endif
358
359#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
360 &bfin_mii_bus,
361 &bfin_mac_device,
362#endif
363
364#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
365 &spi_bfin_master_device,
366#endif
367
368#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
369 &i2c_bfin_twi_device,
370#endif
371
372#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
373 &rtc_device,
374#endif
375
376};
377
378static int __init dnp5370_init(void)
379{
380 printk(KERN_INFO "DNP/5370: registering device resources\n");
381 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
382 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
383 ARRAY_SIZE(bfin_spi_board_info));
384 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
385 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
386 return 0;
387}
388arch_initcall(dnp5370_init);
389
390/*
391 * Currently the MAC address is saved in Flash by U-Boot
392 */
393void bfin_get_ether_addr(char *addr)
394{
395 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
396 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
397}
398EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 05d45994480e..bfb3671a78da 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -68,13 +68,35 @@ static struct platform_device rtc_device = {
68#endif 68#endif
69 69
70#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 70#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
71#include <linux/bfin_mac.h>
72static const unsigned short bfin_mac_peripherals[] = P_MII0;
73
74static struct bfin_phydev_platform_data bfin_phydev_data[] = {
75 {
76 .addr = 1,
77 .irq = IRQ_MAC_PHYINT,
78 },
79};
80
81static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
82 .phydev_number = 1,
83 .phydev_data = bfin_phydev_data,
84 .phy_mode = PHY_INTERFACE_MODE_MII,
85 .mac_peripherals = bfin_mac_peripherals,
86};
87
71static struct platform_device bfin_mii_bus = { 88static struct platform_device bfin_mii_bus = {
72 .name = "bfin_mii_bus", 89 .name = "bfin_mii_bus",
90 .dev = {
91 .platform_data = &bfin_mii_bus_data,
92 }
73}; 93};
74 94
75static struct platform_device bfin_mac_device = { 95static struct platform_device bfin_mac_device = {
76 .name = "bfin_mac", 96 .name = "bfin_mac",
77 .dev.platform_data = &bfin_mii_bus, 97 .dev = {
98 .platform_data = &bfin_mii_bus,
99 }
78}; 100};
79#endif 101#endif
80 102
@@ -241,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
241 }, 263 },
242}; 264};
243 265
244unsigned short bfin_uart0_peripherals[] = { 266static unsigned short bfin_uart0_peripherals[] = {
245 P_UART0_TX, P_UART0_RX, 0 267 P_UART0_TX, P_UART0_RX, 0
246}; 268};
247 269
@@ -284,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
284 }, 306 },
285}; 307};
286 308
287unsigned short bfin_uart1_peripherals[] = { 309static unsigned short bfin_uart1_peripherals[] = {
288 P_UART1_TX, P_UART1_RX, 0 310 P_UART1_TX, P_UART1_RX, 0
289}; 311};
290 312
@@ -397,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
397 }, 419 },
398}; 420};
399 421
400unsigned short bfin_sport0_peripherals[] = { 422static unsigned short bfin_sport0_peripherals[] = {
401 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
402 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
403}; 425};
404 426
405static struct platform_device bfin_sport0_uart_device = { 427static struct platform_device bfin_sport0_uart_device = {
@@ -431,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
431 }, 453 },
432}; 454};
433 455
434unsigned short bfin_sport1_peripherals[] = { 456static unsigned short bfin_sport1_peripherals[] = {
435 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
436 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
437}; 459};
438 460
439static struct platform_device bfin_sport1_uart_device = { 461static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 812e8f991601..9389f03e3b0a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -99,13 +99,35 @@ static struct platform_device smc91x_device = {
99#endif 99#endif
100 100
101#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 101#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
102#include <linux/bfin_mac.h>
103static const unsigned short bfin_mac_peripherals[] = P_RMII0;
104
105static struct bfin_phydev_platform_data bfin_phydev_data[] = {
106 {
107 .addr = 1,
108 .irq = IRQ_MAC_PHYINT,
109 },
110};
111
112static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
113 .phydev_number = 1,
114 .phydev_data = bfin_phydev_data,
115 .phy_mode = PHY_INTERFACE_MODE_RMII,
116 .mac_peripherals = bfin_mac_peripherals,
117};
118
102static struct platform_device bfin_mii_bus = { 119static struct platform_device bfin_mii_bus = {
103 .name = "bfin_mii_bus", 120 .name = "bfin_mii_bus",
121 .dev = {
122 .platform_data = &bfin_mii_bus_data,
123 }
104}; 124};
105 125
106static struct platform_device bfin_mac_device = { 126static struct platform_device bfin_mac_device = {
107 .name = "bfin_mac", 127 .name = "bfin_mac",
108 .dev.platform_data = &bfin_mii_bus, 128 .dev = {
129 .platform_data = &bfin_mii_bus,
130 }
109}; 131};
110#endif 132#endif
111 133
@@ -175,8 +197,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
175}; 197};
176#endif 198#endif
177 199
178#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 200#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
179 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 201 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
180static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 202static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
181 .enable_dma = 0, 203 .enable_dma = 0,
182 .bits_per_word = 16, 204 .bits_per_word = 16,
@@ -238,13 +260,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
238 }, 260 },
239#endif 261#endif
240 262
241#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 263#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
242 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 264 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
243 { 265 {
244 .modalias = "ad1836", 266 .modalias = "ad183x",
245 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 267 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
246 .bus_num = 0, 268 .bus_num = 0,
247 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 269 .chip_select = 4,
248 .controller_data = &ad1836_spi_chip_info, 270 .controller_data = &ad1836_spi_chip_info,
249 }, 271 },
250#endif 272#endif
@@ -345,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
345 }, 367 },
346}; 368};
347 369
348unsigned short bfin_uart0_peripherals[] = { 370static unsigned short bfin_uart0_peripherals[] = {
349 P_UART0_TX, P_UART0_RX, 0 371 P_UART0_TX, P_UART0_RX, 0
350}; 372};
351 373
@@ -388,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
388 }, 410 },
389}; 411};
390 412
391unsigned short bfin_uart1_peripherals[] = { 413static unsigned short bfin_uart1_peripherals[] = {
392 P_UART1_TX, P_UART1_RX, 0 414 P_UART1_TX, P_UART1_RX, 0
393}; 415};
394 416
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 68a27bccc7d4..76db1d483173 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -35,12 +35,11 @@
35#include <asm/reboot.h> 35#include <asm/reboot.h>
36#include <asm/portmux.h> 36#include <asm/portmux.h>
37#include <asm/dpmc.h> 37#include <asm/dpmc.h>
38#ifdef CONFIG_REGULATOR_ADP_SWITCH 38#include <asm/bfin_sport.h>
39#include <linux/regulator/adp_switch.h> 39#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
40#endif 40#include <linux/regulator/fixed.h>
41#ifdef CONFIG_REGULATOR_AD5398
42#include <linux/regulator/ad5398.h>
43#endif 41#endif
42#include <linux/regulator/machine.h>
44#include <linux/regulator/consumer.h> 43#include <linux/regulator/consumer.h>
45#include <linux/regulator/userspace-consumer.h> 44#include <linux/regulator/userspace-consumer.h>
46 45
@@ -264,7 +263,7 @@ static struct resource isp1362_hcd_resources[] = {
264 }, { 263 }, {
265 .start = IRQ_PF3, 264 .start = IRQ_PF3,
266 .end = IRQ_PF3, 265 .end = IRQ_PF3,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 266 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
268 }, 267 },
269}; 268};
270 269
@@ -291,7 +290,7 @@ static struct platform_device isp1362_hcd_device = {
291#endif 290#endif
292 291
293#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 292#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
294unsigned short bfin_can_peripherals[] = { 293static unsigned short bfin_can_peripherals[] = {
295 P_CAN0_RX, P_CAN0_TX, 0 294 P_CAN0_RX, P_CAN0_TX, 0
296}; 295};
297 296
@@ -329,13 +328,35 @@ static struct platform_device bfin_can_device = {
329#endif 328#endif
330 329
331#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 330#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
331#include <linux/bfin_mac.h>
332static const unsigned short bfin_mac_peripherals[] = P_MII0;
333
334static struct bfin_phydev_platform_data bfin_phydev_data[] = {
335 {
336 .addr = 1,
337 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
338 },
339};
340
341static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
342 .phydev_number = 1,
343 .phydev_data = bfin_phydev_data,
344 .phy_mode = PHY_INTERFACE_MODE_MII,
345 .mac_peripherals = bfin_mac_peripherals,
346};
347
332static struct platform_device bfin_mii_bus = { 348static struct platform_device bfin_mii_bus = {
333 .name = "bfin_mii_bus", 349 .name = "bfin_mii_bus",
350 .dev = {
351 .platform_data = &bfin_mii_bus_data,
352 }
334}; 353};
335 354
336static struct platform_device bfin_mac_device = { 355static struct platform_device bfin_mac_device = {
337 .name = "bfin_mac", 356 .name = "bfin_mac",
338 .dev.platform_data = &bfin_mii_bus, 357 .dev = {
358 .platform_data = &bfin_mii_bus,
359 }
339}; 360};
340#endif 361#endif
341 362
@@ -361,7 +382,6 @@ static struct platform_device net2272_bfin_device = {
361#endif 382#endif
362 383
363#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 384#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
364#ifdef CONFIG_MTD_PARTITIONS
365const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; 385const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
366 386
367static struct mtd_partition bfin_plat_nand_partitions[] = { 387static struct mtd_partition bfin_plat_nand_partitions[] = {
@@ -375,7 +395,6 @@ static struct mtd_partition bfin_plat_nand_partitions[] = {
375 .offset = MTDPART_OFS_APPEND, 395 .offset = MTDPART_OFS_APPEND,
376 }, 396 },
377}; 397};
378#endif
379 398
380#define BFIN_NAND_PLAT_CLE 2 399#define BFIN_NAND_PLAT_CLE 2
381#define BFIN_NAND_PLAT_ALE 1 400#define BFIN_NAND_PLAT_ALE 1
@@ -402,11 +421,9 @@ static struct platform_nand_data bfin_plat_nand_data = {
402 .chip = { 421 .chip = {
403 .nr_chips = 1, 422 .nr_chips = 1,
404 .chip_delay = 30, 423 .chip_delay = 30,
405#ifdef CONFIG_MTD_PARTITIONS
406 .part_probe_types = part_probes, 424 .part_probe_types = part_probes,
407 .partitions = bfin_plat_nand_partitions, 425 .partitions = bfin_plat_nand_partitions,
408 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), 426 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
409#endif
410 }, 427 },
411 .ctrl = { 428 .ctrl = {
412 .cmd_ctrl = bfin_plat_nand_cmd_ctrl, 429 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
@@ -418,7 +435,7 @@ static struct platform_nand_data bfin_plat_nand_data = {
418static struct resource bfin_plat_nand_resources = { 435static struct resource bfin_plat_nand_resources = {
419 .start = 0x20212000, 436 .start = 0x20212000,
420 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), 437 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
421 .flags = IORESOURCE_IO, 438 .flags = IORESOURCE_MEM,
422}; 439};
423 440
424static struct platform_device bfin_async_nand_device = { 441static struct platform_device bfin_async_nand_device = {
@@ -545,6 +562,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
545}; 562};
546#endif 563#endif
547 564
565#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
566 || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
567static struct bfin5xx_spi_chip adav801_spi_chip_info = {
568 .enable_dma = 0,
569 .bits_per_word = 8,
570};
571#endif
572
548#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) 573#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
549#include <linux/input/ad714x.h> 574#include <linux/input/ad714x.h>
550static struct bfin5xx_spi_chip ad7147_spi_chip_info = { 575static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
@@ -665,7 +690,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
665#endif 690#endif
666 691
667#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE) 692#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
668unsigned short ad2s120x_platform_data[] = { 693static unsigned short ad2s120x_platform_data[] = {
669 /* used as SAMPLE and RDVEL */ 694 /* used as SAMPLE and RDVEL */
670 GPIO_PF5, GPIO_PF6, 0 695 GPIO_PF5, GPIO_PF6, 0
671}; 696};
@@ -677,7 +702,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
677#endif 702#endif
678 703
679#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE) 704#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
680unsigned short ad2s1210_platform_data[] = { 705static unsigned short ad2s1210_platform_data[] = {
681 /* use as SAMPLE, A0, A1 */ 706 /* use as SAMPLE, A0, A1 */
682 GPIO_PF7, GPIO_PF8, GPIO_PF9, 707 GPIO_PF7, GPIO_PF8, GPIO_PF9,
683# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) 708# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@@ -693,6 +718,65 @@ static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
693}; 718};
694#endif 719#endif
695 720
721#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
722static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
723 .enable_dma = 0,
724 .bits_per_word = 16,
725};
726#endif
727
728#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
729static unsigned short ad7816_platform_data[] = {
730 GPIO_PF4, /* rdwr_pin */
731 GPIO_PF5, /* convert_pin */
732 GPIO_PF7, /* busy_pin */
733 0,
734};
735
736static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
737 .enable_dma = 0,
738 .bits_per_word = 8,
739};
740#endif
741
742#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
743static unsigned long adt7310_platform_data[3] = {
744/* INT bound temperature alarm event. line 1 */
745 IRQ_PG4, IRQF_TRIGGER_LOW,
746/* CT bound temperature alarm event irq_flags. line 0 */
747 IRQF_TRIGGER_LOW,
748};
749
750static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
751 .enable_dma = 0,
752 .bits_per_word = 8,
753};
754#endif
755
756#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
757static unsigned short ad7298_platform_data[] = {
758 GPIO_PF7, /* busy_pin */
759 0,
760};
761
762static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
763 .enable_dma = 0,
764 .bits_per_word = 16,
765};
766#endif
767
768#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
769static unsigned long adt7316_spi_data[2] = {
770 IRQF_TRIGGER_LOW, /* interrupt flags */
771 GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
772};
773
774static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
775 .enable_dma = 0,
776 .bits_per_word = 8,
777};
778#endif
779
696#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 780#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
697#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 781#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
698 782
@@ -824,14 +908,12 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
824static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { 908static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
825 .enable_dma = 1, 909 .enable_dma = 1,
826 .bits_per_word = 8, 910 .bits_per_word = 8,
827 .cs_gpio = GPIO_PF10,
828}; 911};
829#endif 912#endif
830 913
831#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) 914#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
832static struct bfin5xx_spi_chip adf7021_spi_chip_info = { 915static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
833 .bits_per_word = 16, 916 .bits_per_word = 16,
834 .cs_gpio = GPIO_PF10,
835}; 917};
836 918
837#include <linux/spi/adf702x.h> 919#include <linux/spi/adf702x.h>
@@ -938,6 +1020,13 @@ static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
938}; 1020};
939#endif 1021#endif
940 1022
1023#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
1024static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
1025 .enable_dma = 0, /* use dma transfer with this chip*/
1026 .bits_per_word = 8,
1027};
1028#endif
1029
941static struct spi_board_info bfin_spi_board_info[] __initdata = { 1030static struct spi_board_info bfin_spi_board_info[] __initdata = {
942#if defined(CONFIG_MTD_M25P80) \ 1031#if defined(CONFIG_MTD_M25P80) \
943 || defined(CONFIG_MTD_M25P80_MODULE) 1032 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -982,7 +1071,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
982 .modalias = "ad183x", 1071 .modalias = "ad183x",
983 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1072 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
984 .bus_num = 0, 1073 .bus_num = 0,
985 .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ 1074 .chip_select = 4,
986 .platform_data = "ad1836", /* only includes chip name for the moment */ 1075 .platform_data = "ad1836", /* only includes chip name for the moment */
987 .controller_data = &ad1836_spi_chip_info, 1076 .controller_data = &ad1836_spi_chip_info,
988 .mode = SPI_MODE_3, 1077 .mode = SPI_MODE_3,
@@ -1000,6 +1089,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1000 }, 1089 },
1001#endif 1090#endif
1002 1091
1092#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
1093 {
1094 .modalias = "adav80x",
1095 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1096 .bus_num = 0,
1097 .chip_select = 1,
1098 .controller_data = &adav801_spi_chip_info,
1099 .mode = SPI_MODE_3,
1100 },
1101#endif
1102
1003#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) 1103#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
1004 { 1104 {
1005 .modalias = "ad714x_captouch", 1105 .modalias = "ad714x_captouch",
@@ -1018,6 +1118,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1018 .modalias = "ad2s90", 1118 .modalias = "ad2s90",
1019 .bus_num = 0, 1119 .bus_num = 0,
1020 .chip_select = 3, /* change it for your board */ 1120 .chip_select = 3, /* change it for your board */
1121 .mode = SPI_MODE_3,
1021 .platform_data = NULL, 1122 .platform_data = NULL,
1022 .controller_data = &ad2s90_spi_chip_info, 1123 .controller_data = &ad2s90_spi_chip_info,
1023 }, 1124 },
@@ -1044,6 +1145,67 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1044 }, 1145 },
1045#endif 1146#endif
1046 1147
1148#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
1149 {
1150 .modalias = "ad7314",
1151 .max_speed_hz = 1000000,
1152 .bus_num = 0,
1153 .chip_select = 4, /* CS, change it for your board */
1154 .controller_data = &ad7314_spi_chip_info,
1155 .mode = SPI_MODE_1,
1156 },
1157#endif
1158
1159#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
1160 {
1161 .modalias = "ad7818",
1162 .max_speed_hz = 1000000,
1163 .bus_num = 0,
1164 .chip_select = 4, /* CS, change it for your board */
1165 .platform_data = ad7816_platform_data,
1166 .controller_data = &ad7816_spi_chip_info,
1167 .mode = SPI_MODE_3,
1168 },
1169#endif
1170
1171#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
1172 {
1173 .modalias = "adt7310",
1174 .max_speed_hz = 1000000,
1175 .irq = IRQ_PG5, /* CT alarm event. Line 0 */
1176 .bus_num = 0,
1177 .chip_select = 4, /* CS, change it for your board */
1178 .platform_data = adt7310_platform_data,
1179 .controller_data = &adt7310_spi_chip_info,
1180 .mode = SPI_MODE_3,
1181 },
1182#endif
1183
1184#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
1185 {
1186 .modalias = "ad7298",
1187 .max_speed_hz = 1000000,
1188 .bus_num = 0,
1189 .chip_select = 4, /* CS, change it for your board */
1190 .platform_data = ad7298_platform_data,
1191 .controller_data = &ad7298_spi_chip_info,
1192 .mode = SPI_MODE_3,
1193 },
1194#endif
1195
1196#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
1197 {
1198 .modalias = "adt7316",
1199 .max_speed_hz = 1000000,
1200 .irq = IRQ_PG5, /* interrupt line */
1201 .bus_num = 0,
1202 .chip_select = 4, /* CS, change it for your board */
1203 .platform_data = adt7316_spi_data,
1204 .controller_data = &adt7316_spi_chip_info,
1205 .mode = SPI_MODE_3,
1206 },
1207#endif
1208
1047#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 1209#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1048 { 1210 {
1049 .modalias = "mmc_spi", 1211 .modalias = "mmc_spi",
@@ -1103,7 +1265,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1103 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 1265 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1104 .irq = IRQ_PF6, 1266 .irq = IRQ_PF6,
1105 .bus_num = 0, 1267 .bus_num = 0,
1106 .chip_select = 0, /* GPIO controlled SSEL */ 1268 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1107 .controller_data = &enc28j60_spi_chip_info, 1269 .controller_data = &enc28j60_spi_chip_info,
1108 .mode = SPI_MODE_0, 1270 .mode = SPI_MODE_0,
1109 }, 1271 },
@@ -1125,7 +1287,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1125 .modalias = "adf702x", 1287 .modalias = "adf702x",
1126 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ 1288 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1127 .bus_num = 0, 1289 .bus_num = 0,
1128 .chip_select = 0, /* GPIO controlled SSEL */ 1290 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1129 .controller_data = &adf7021_spi_chip_info, 1291 .controller_data = &adf7021_spi_chip_info,
1130 .platform_data = &adf7021_platform_data, 1292 .platform_data = &adf7021_platform_data,
1131 .mode = SPI_MODE_0, 1293 .mode = SPI_MODE_0,
@@ -1143,12 +1305,239 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1143 .mode = SPI_MODE_0, 1305 .mode = SPI_MODE_0,
1144 }, 1306 },
1145#endif 1307#endif
1308#if defined(CONFIG_AD7476) \
1309 || defined(CONFIG_AD7476_MODULE)
1310 {
1311 .modalias = "ad7476", /* Name of spi_driver for this device */
1312 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
1313 .bus_num = 0, /* Framework bus number */
1314 .chip_select = 1, /* Framework chip select. */
1315 .platform_data = NULL, /* No spi_driver specific config */
1316 .controller_data = &spi_ad7476_chip_info,
1317 .mode = SPI_MODE_3,
1318 },
1319#endif
1320#if defined(CONFIG_ADE7753) \
1321 || defined(CONFIG_ADE7753_MODULE)
1322 {
1323 .modalias = "ade7753",
1324 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1325 .bus_num = 0,
1326 .chip_select = 1, /* CS, change it for your board */
1327 .platform_data = NULL, /* No spi_driver specific config */
1328 .mode = SPI_MODE_1,
1329 },
1330#endif
1331#if defined(CONFIG_ADE7754) \
1332 || defined(CONFIG_ADE7754_MODULE)
1333 {
1334 .modalias = "ade7754",
1335 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1336 .bus_num = 0,
1337 .chip_select = 1, /* CS, change it for your board */
1338 .platform_data = NULL, /* No spi_driver specific config */
1339 .mode = SPI_MODE_1,
1340 },
1341#endif
1342#if defined(CONFIG_ADE7758) \
1343 || defined(CONFIG_ADE7758_MODULE)
1344 {
1345 .modalias = "ade7758",
1346 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1347 .bus_num = 0,
1348 .chip_select = 1, /* CS, change it for your board */
1349 .platform_data = NULL, /* No spi_driver specific config */
1350 .mode = SPI_MODE_1,
1351 },
1352#endif
1353#if defined(CONFIG_ADE7759) \
1354 || defined(CONFIG_ADE7759_MODULE)
1355 {
1356 .modalias = "ade7759",
1357 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1358 .bus_num = 0,
1359 .chip_select = 1, /* CS, change it for your board */
1360 .platform_data = NULL, /* No spi_driver specific config */
1361 .mode = SPI_MODE_1,
1362 },
1363#endif
1364#if defined(CONFIG_ADE7854_SPI) \
1365 || defined(CONFIG_ADE7854_SPI_MODULE)
1366 {
1367 .modalias = "ade7854",
1368 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1369 .bus_num = 0,
1370 .chip_select = 1, /* CS, change it for your board */
1371 .platform_data = NULL, /* No spi_driver specific config */
1372 .mode = SPI_MODE_3,
1373 },
1374#endif
1375#if defined(CONFIG_ADIS16060) \
1376 || defined(CONFIG_ADIS16060_MODULE)
1377 {
1378 .modalias = "adis16060_r",
1379 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1380 .bus_num = 0,
1381 .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
1382 .platform_data = NULL, /* No spi_driver specific config */
1383 .mode = SPI_MODE_0,
1384 },
1385 {
1386 .modalias = "adis16060_w",
1387 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1388 .bus_num = 0,
1389 .chip_select = 2, /* CS for write, change it for your board */
1390 .platform_data = NULL, /* No spi_driver specific config */
1391 .mode = SPI_MODE_1,
1392 },
1393#endif
1394#if defined(CONFIG_ADIS16130) \
1395 || defined(CONFIG_ADIS16130_MODULE)
1396 {
1397 .modalias = "adis16130",
1398 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1399 .bus_num = 0,
1400 .chip_select = 1, /* CS for read, change it for your board */
1401 .platform_data = NULL, /* No spi_driver specific config */
1402 .mode = SPI_MODE_3,
1403 },
1404#endif
1405#if defined(CONFIG_ADIS16201) \
1406 || defined(CONFIG_ADIS16201_MODULE)
1407 {
1408 .modalias = "adis16201",
1409 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1410 .bus_num = 0,
1411 .chip_select = 5, /* CS, change it for your board */
1412 .platform_data = NULL, /* No spi_driver specific config */
1413 .mode = SPI_MODE_3,
1414 .irq = IRQ_PF4,
1415 },
1416#endif
1417#if defined(CONFIG_ADIS16203) \
1418 || defined(CONFIG_ADIS16203_MODULE)
1419 {
1420 .modalias = "adis16203",
1421 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1422 .bus_num = 0,
1423 .chip_select = 5, /* CS, change it for your board */
1424 .platform_data = NULL, /* No spi_driver specific config */
1425 .mode = SPI_MODE_3,
1426 .irq = IRQ_PF4,
1427 },
1428#endif
1429#if defined(CONFIG_ADIS16204) \
1430 || defined(CONFIG_ADIS16204_MODULE)
1431 {
1432 .modalias = "adis16204",
1433 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1434 .bus_num = 0,
1435 .chip_select = 5, /* CS, change it for your board */
1436 .platform_data = NULL, /* No spi_driver specific config */
1437 .mode = SPI_MODE_3,
1438 .irq = IRQ_PF4,
1439 },
1440#endif
1441#if defined(CONFIG_ADIS16209) \
1442 || defined(CONFIG_ADIS16209_MODULE)
1443 {
1444 .modalias = "adis16209",
1445 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1446 .bus_num = 0,
1447 .chip_select = 5, /* CS, change it for your board */
1448 .platform_data = NULL, /* No spi_driver specific config */
1449 .mode = SPI_MODE_3,
1450 .irq = IRQ_PF4,
1451 },
1452#endif
1453#if defined(CONFIG_ADIS16220) \
1454 || defined(CONFIG_ADIS16220_MODULE)
1455 {
1456 .modalias = "adis16220",
1457 .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
1458 .bus_num = 0,
1459 .chip_select = 5, /* CS, change it for your board */
1460 .platform_data = NULL, /* No spi_driver specific config */
1461 .mode = SPI_MODE_3,
1462 .irq = IRQ_PF4,
1463 },
1464#endif
1465#if defined(CONFIG_ADIS16240) \
1466 || defined(CONFIG_ADIS16240_MODULE)
1467 {
1468 .modalias = "adis16240",
1469 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1470 .bus_num = 0,
1471 .chip_select = 5, /* CS, change it for your board */
1472 .platform_data = NULL, /* No spi_driver specific config */
1473 .mode = SPI_MODE_3,
1474 .irq = IRQ_PF4,
1475 },
1476#endif
1477#if defined(CONFIG_ADIS16260) \
1478 || defined(CONFIG_ADIS16260_MODULE)
1479 {
1480 .modalias = "adis16260",
1481 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1482 .bus_num = 0,
1483 .chip_select = 5, /* CS, change it for your board */
1484 .platform_data = NULL, /* No spi_driver specific config */
1485 .mode = SPI_MODE_3,
1486 .irq = IRQ_PF4,
1487 },
1488#endif
1489#if defined(CONFIG_ADIS16261) \
1490 || defined(CONFIG_ADIS16261_MODULE)
1491 {
1492 .modalias = "adis16261",
1493 .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
1494 .bus_num = 0,
1495 .chip_select = 1, /* CS, change it for your board */
1496 .platform_data = NULL, /* No spi_driver specific config */
1497 .mode = SPI_MODE_3,
1498 },
1499#endif
1500#if defined(CONFIG_ADIS16300) \
1501 || defined(CONFIG_ADIS16300_MODULE)
1502 {
1503 .modalias = "adis16300",
1504 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1505 .bus_num = 0,
1506 .chip_select = 5, /* CS, change it for your board */
1507 .platform_data = NULL, /* No spi_driver specific config */
1508 .mode = SPI_MODE_3,
1509 .irq = IRQ_PF4,
1510 },
1511#endif
1512#if defined(CONFIG_ADIS16350) \
1513 || defined(CONFIG_ADIS16350_MODULE)
1514 {
1515 .modalias = "adis16364",
1516 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1517 .bus_num = 0,
1518 .chip_select = 5, /* CS, change it for your board */
1519 .platform_data = NULL, /* No spi_driver specific config */
1520 .mode = SPI_MODE_3,
1521 .irq = IRQ_PF4,
1522 },
1523#endif
1524#if defined(CONFIG_ADIS16400) \
1525 || defined(CONFIG_ADIS16400_MODULE)
1526 {
1527 .modalias = "adis16400",
1528 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1529 .bus_num = 0,
1530 .chip_select = 1, /* CS, change it for your board */
1531 .platform_data = NULL, /* No spi_driver specific config */
1532 .mode = SPI_MODE_3,
1533 },
1534#endif
1146}; 1535};
1147 1536
1148#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 1537#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1149/* SPI controller data */ 1538/* SPI controller data */
1150static struct bfin5xx_spi_master bfin_spi0_info = { 1539static struct bfin5xx_spi_master bfin_spi0_info = {
1151 .num_chipselect = 8, 1540 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1152 .enable_dma = 1, /* master has the ability to do dma transfer */ 1541 .enable_dma = 1, /* master has the ability to do dma transfer */
1153 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1542 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1154}; 1543};
@@ -1325,7 +1714,7 @@ static struct resource bfin_uart0_resources[] = {
1325#endif 1714#endif
1326}; 1715};
1327 1716
1328unsigned short bfin_uart0_peripherals[] = { 1717static unsigned short bfin_uart0_peripherals[] = {
1329 P_UART0_TX, P_UART0_RX, 0 1718 P_UART0_TX, P_UART0_RX, 0
1330}; 1719};
1331 1720
@@ -1368,7 +1757,7 @@ static struct resource bfin_uart1_resources[] = {
1368 }, 1757 },
1369}; 1758};
1370 1759
1371unsigned short bfin_uart1_peripherals[] = { 1760static unsigned short bfin_uart1_peripherals[] = {
1372 P_UART1_TX, P_UART1_RX, 0 1761 P_UART1_TX, P_UART1_RX, 0
1373}; 1762};
1374 1763
@@ -1645,7 +2034,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = {
1645}; 2034};
1646 2035
1647 /* 2036 /*
1648 * ADP5520/5501 Multifuction Device Init Data 2037 * ADP5520/5501 Multifunction Device Init Data
1649 */ 2038 */
1650 2039
1651static struct adp5520_platform_data adp5520_pdev_data = { 2040static struct adp5520_platform_data adp5520_pdev_data = {
@@ -1773,12 +2162,6 @@ static struct regulator_init_data ad5398_regulator_data = {
1773 .consumer_supplies = &ad5398_consumer, 2162 .consumer_supplies = &ad5398_consumer,
1774}; 2163};
1775 2164
1776static struct ad5398_platform_data ad5398_i2c_platform_data = {
1777 .current_bits = 10,
1778 .current_offset = 4,
1779 .regulator_data = &ad5398_regulator_data,
1780};
1781
1782#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ 2165#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
1783 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) 2166 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
1784static struct platform_device ad5398_virt_consumer_device = { 2167static struct platform_device ad5398_virt_consumer_device = {
@@ -1811,7 +2194,34 @@ static struct platform_device ad5398_userspace_consumer_device = {
1811#endif 2194#endif
1812#endif 2195#endif
1813 2196
2197#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2198/* INT bound temperature alarm event. line 1 */
2199static unsigned long adt7410_platform_data[2] = {
2200 IRQ_PG4, IRQF_TRIGGER_LOW,
2201};
2202#endif
2203
2204#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2205/* INT bound temperature alarm event. line 1 */
2206static unsigned long adt7316_i2c_data[2] = {
2207 IRQF_TRIGGER_LOW, /* interrupt flags */
2208 GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
2209};
2210#endif
2211
1814static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 2212static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
2213#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
2214 {
2215 I2C_BOARD_INFO("ad1937", 0x04),
2216 },
2217#endif
2218
2219#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
2220 {
2221 I2C_BOARD_INFO("adav803", 0x10),
2222 },
2223#endif
2224
1815#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) 2225#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
1816 { 2226 {
1817 I2C_BOARD_INFO("ad7142_captouch", 0x2C), 2227 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
@@ -1843,12 +2253,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1843 { 2253 {
1844 I2C_BOARD_INFO("ad7414", 0x9), 2254 I2C_BOARD_INFO("ad7414", 0x9),
1845 .irq = IRQ_PG5, 2255 .irq = IRQ_PG5,
1846 /* 2256 .irq_flags = IRQF_TRIGGER_LOW,
1847 * platform_data pointer is borrwoed by the driver to
1848 * store custimer defined IRQ ALART level mode.
1849 * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid.
1850 */
1851 .platform_data = (void *)IRQF_TRIGGER_LOW,
1852 }, 2257 },
1853#endif 2258#endif
1854 2259
@@ -1856,12 +2261,56 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1856 { 2261 {
1857 I2C_BOARD_INFO("ad7417", 0xb), 2262 I2C_BOARD_INFO("ad7417", 0xb),
1858 .irq = IRQ_PG5, 2263 .irq = IRQ_PG5,
1859 /* 2264 .irq_flags = IRQF_TRIGGER_LOW,
1860 * platform_data pointer is borrwoed by the driver to 2265 .platform_data = (void *)GPIO_PF4,
1861 * store custimer defined IRQ ALART level mode. 2266 },
1862 * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. 2267#endif
1863 */ 2268
1864 .platform_data = (void *)IRQF_TRIGGER_LOW, 2269#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE)
2270 {
2271 I2C_BOARD_INFO("ade7854", 0x38),
2272 },
2273#endif
2274
2275#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE)
2276 {
2277 I2C_BOARD_INFO("adt75", 0x9),
2278 .irq = IRQ_PG5,
2279 .irq_flags = IRQF_TRIGGER_LOW,
2280 },
2281#endif
2282
2283#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE)
2284 {
2285 I2C_BOARD_INFO("adt7408", 0x18),
2286 .irq = IRQ_PG5,
2287 .irq_flags = IRQF_TRIGGER_LOW,
2288 },
2289#endif
2290
2291#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2292 {
2293 I2C_BOARD_INFO("adt7410", 0x48),
2294 /* CT critical temperature event. line 0 */
2295 .irq = IRQ_PG5,
2296 .irq_flags = IRQF_TRIGGER_LOW,
2297 .platform_data = (void *)&adt7410_platform_data,
2298 },
2299#endif
2300
2301#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE)
2302 {
2303 I2C_BOARD_INFO("ad7291", 0x20),
2304 .irq = IRQ_PG5,
2305 .irq_flags = IRQF_TRIGGER_LOW,
2306 },
2307#endif
2308
2309#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2310 {
2311 I2C_BOARD_INFO("adt7316", 0x48),
2312 .irq = IRQ_PG6,
2313 .platform_data = (void *)&adt7316_i2c_data,
1865 }, 2314 },
1866#endif 2315#endif
1867 2316
@@ -1917,7 +2366,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1917#endif 2366#endif
1918#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) 2367#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1919 { 2368 {
1920 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), 2369 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
1921 }, 2370 },
1922#endif 2371#endif
1923#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) 2372#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
@@ -1954,7 +2403,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1954#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) 2403#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
1955 { 2404 {
1956 I2C_BOARD_INFO("ad5398", 0xC), 2405 I2C_BOARD_INFO("ad5398", 0xC),
1957 .platform_data = (void *)&ad5398_i2c_platform_data, 2406 .platform_data = (void *)&ad5398_regulator_data,
1958 }, 2407 },
1959#endif 2408#endif
1960#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE) 2409#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
@@ -1963,6 +2412,16 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1963 .platform_data = (void *)&adp8860_pdata, 2412 .platform_data = (void *)&adp8860_pdata,
1964 }, 2413 },
1965#endif 2414#endif
2415#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
2416 {
2417 I2C_BOARD_INFO("adau1373", 0x1A),
2418 },
2419#endif
2420#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
2421 {
2422 I2C_BOARD_INFO("ad5252", 0x2e),
2423 },
2424#endif
1966}; 2425};
1967 2426
1968#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 2427#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -1985,9 +2444,9 @@ static struct resource bfin_sport0_uart_resources[] = {
1985 }, 2444 },
1986}; 2445};
1987 2446
1988unsigned short bfin_sport0_peripherals[] = { 2447static unsigned short bfin_sport0_peripherals[] = {
1989 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 2448 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
1990 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 2449 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
1991}; 2450};
1992 2451
1993static struct platform_device bfin_sport0_uart_device = { 2452static struct platform_device bfin_sport0_uart_device = {
@@ -2019,9 +2478,9 @@ static struct resource bfin_sport1_uart_resources[] = {
2019 }, 2478 },
2020}; 2479};
2021 2480
2022unsigned short bfin_sport1_peripherals[] = { 2481static unsigned short bfin_sport1_peripherals[] = {
2023 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 2482 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
2024 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 2483 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
2025}; 2484};
2026 2485
2027static struct platform_device bfin_sport1_uart_device = { 2486static struct platform_device bfin_sport1_uart_device = {
@@ -2068,7 +2527,7 @@ static struct resource bfin_pata_resources[] = {
2068static struct pata_platform_info bfin_pata_platform_data = { 2527static struct pata_platform_info bfin_pata_platform_data = {
2069 .ioport_shift = 0, 2528 .ioport_shift = 0,
2070}; 2529};
2071/* CompactFlash Storage Card Memory Mapped Adressing 2530/* CompactFlash Storage Card Memory Mapped Addressing
2072 * /REG = A11 = 1 2531 * /REG = A11 = 1
2073 */ 2532 */
2074static struct resource bfin_pata_resources[] = { 2533static struct resource bfin_pata_resources[] = {
@@ -2123,74 +2582,138 @@ static struct platform_device bfin_dpmc = {
2123 }, 2582 },
2124}; 2583};
2125 2584
2126#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 2585#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2586 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2587 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2588
2589#define SPORT_REQ(x) \
2590 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
2591 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
2592
2593static const u16 bfin_snd_pin[][7] = {
2594 SPORT_REQ(0),
2595 SPORT_REQ(1),
2596};
2597
2598static struct bfin_snd_platform_data bfin_snd_data[] = {
2599 {
2600 .pin_req = &bfin_snd_pin[0][0],
2601 },
2602 {
2603 .pin_req = &bfin_snd_pin[1][0],
2604 },
2605};
2606
2607#define BFIN_SND_RES(x) \
2608 [x] = { \
2609 { \
2610 .start = SPORT##x##_TCR1, \
2611 .end = SPORT##x##_TCR1, \
2612 .flags = IORESOURCE_MEM \
2613 }, \
2614 { \
2615 .start = CH_SPORT##x##_RX, \
2616 .end = CH_SPORT##x##_RX, \
2617 .flags = IORESOURCE_DMA, \
2618 }, \
2619 { \
2620 .start = CH_SPORT##x##_TX, \
2621 .end = CH_SPORT##x##_TX, \
2622 .flags = IORESOURCE_DMA, \
2623 }, \
2624 { \
2625 .start = IRQ_SPORT##x##_ERROR, \
2626 .end = IRQ_SPORT##x##_ERROR, \
2627 .flags = IORESOURCE_IRQ, \
2628 } \
2629 }
2630
2631static struct resource bfin_snd_resources[][4] = {
2632 BFIN_SND_RES(0),
2633 BFIN_SND_RES(1),
2634};
2635
2636static struct platform_device bfin_pcm = {
2637 .name = "bfin-pcm-audio",
2638 .id = -1,
2639};
2640#endif
2641
2642#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2643static struct platform_device bfin_ad73311_codec_device = {
2644 .name = "ad73311",
2645 .id = -1,
2646};
2647#endif
2648
2649#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
2127static struct platform_device bfin_i2s = { 2650static struct platform_device bfin_i2s = {
2128 .name = "bfin-i2s", 2651 .name = "bfin-i2s",
2129 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2652 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2130 /* TODO: add platform data here */ 2653 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2654 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2655 .dev = {
2656 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2657 },
2131}; 2658};
2132#endif 2659#endif
2133 2660
2134#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 2661#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
2135static struct platform_device bfin_tdm = { 2662static struct platform_device bfin_tdm = {
2136 .name = "bfin-tdm", 2663 .name = "bfin-tdm",
2137 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2664 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2138 /* TODO: add platform data here */ 2665 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2666 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2667 .dev = {
2668 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2669 },
2139}; 2670};
2140#endif 2671#endif
2141 2672
2142#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 2673#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
2143static struct platform_device bfin_ac97 = { 2674static struct platform_device bfin_ac97 = {
2144 .name = "bfin-ac97", 2675 .name = "bfin-ac97",
2145 .id = CONFIG_SND_BF5XX_SPORT_NUM, 2676 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2146 /* TODO: add platform data here */ 2677 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2678 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2679 .dev = {
2680 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2681 },
2147}; 2682};
2148#endif 2683#endif
2149 2684
2150#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) 2685#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
2151#define REGULATOR_ADP122 "adp122" 2686#define REGULATOR_ADP122 "adp122"
2152#define REGULATOR_ADP150 "adp150" 2687#define REGULATOR_ADP122_UV 2500000
2153 2688
2154static struct regulator_consumer_supply adp122_consumers = { 2689static struct regulator_consumer_supply adp122_consumers = {
2155 .supply = REGULATOR_ADP122, 2690 .supply = REGULATOR_ADP122,
2156}; 2691};
2157 2692
2158static struct regulator_consumer_supply adp150_consumers = { 2693static struct regulator_init_data adp_switch_regulator_data = {
2159 .supply = REGULATOR_ADP150, 2694 .constraints = {
2160}; 2695 .name = REGULATOR_ADP122,
2161 2696 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2162static struct regulator_init_data adp_switch_regulator_data[] = { 2697 .min_uV = REGULATOR_ADP122_UV,
2163 { 2698 .max_uV = REGULATOR_ADP122_UV,
2164 .constraints = { 2699 .min_uA = 0,
2165 .name = REGULATOR_ADP122, 2700 .max_uA = 300000,
2166 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2167 .min_uA = 0,
2168 .max_uA = 300000,
2169 },
2170 .num_consumer_supplies = 1, /* only 1 */
2171 .consumer_supplies = &adp122_consumers,
2172 .driver_data = (void *)GPIO_PF2, /* gpio port only */
2173 },
2174 {
2175 .constraints = {
2176 .name = REGULATOR_ADP150,
2177 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2178 .min_uA = 0,
2179 .max_uA = 150000,
2180 },
2181 .num_consumer_supplies = 1, /* only 1 */
2182 .consumer_supplies = &adp150_consumers,
2183 .driver_data = (void *)GPIO_PF3, /* gpio port only */
2184 }, 2701 },
2702 .num_consumer_supplies = 1, /* only 1 */
2703 .consumer_supplies = &adp122_consumers,
2185}; 2704};
2186 2705
2187static struct adp_switch_platform_data adp_switch_pdata = { 2706static struct fixed_voltage_config adp_switch_pdata = {
2188 .regulator_num = ARRAY_SIZE(adp_switch_regulator_data), 2707 .supply_name = REGULATOR_ADP122,
2189 .regulator_data = adp_switch_regulator_data, 2708 .microvolts = REGULATOR_ADP122_UV,
2709 .gpio = GPIO_PF2,
2710 .enable_high = 1,
2711 .enabled_at_boot = 0,
2712 .init_data = &adp_switch_regulator_data,
2190}; 2713};
2191 2714
2192static struct platform_device adp_switch_device = { 2715static struct platform_device adp_switch_device = {
2193 .name = "adp_switch", 2716 .name = "reg-fixed-voltage",
2194 .id = 0, 2717 .id = 0,
2195 .dev = { 2718 .dev = {
2196 .platform_data = &adp_switch_pdata, 2719 .platform_data = &adp_switch_pdata,
@@ -2216,27 +2739,26 @@ static struct platform_device adp122_userspace_consumer_device = {
2216 .platform_data = &adp122_userspace_comsumer_data, 2739 .platform_data = &adp122_userspace_comsumer_data,
2217 }, 2740 },
2218}; 2741};
2742#endif
2743#endif
2219 2744
2220static struct regulator_bulk_data adp150_bulk_data = { 2745#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2221 .supply = REGULATOR_ADP150, 2746 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2222};
2223 2747
2224static struct regulator_userspace_consumer_data adp150_userspace_comsumer_data = { 2748static struct resource iio_gpio_trigger_resources[] = {
2225 .name = REGULATOR_ADP150, 2749 [0] = {
2226 .num_supplies = 1, 2750 .start = IRQ_PF5,
2227 .supplies = &adp150_bulk_data, 2751 .end = IRQ_PF5,
2752 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
2753 },
2228}; 2754};
2229 2755
2230static struct platform_device adp150_userspace_consumer_device = { 2756static struct platform_device iio_gpio_trigger = {
2231 .name = "reg-userspace-consumer", 2757 .name = "iio_gpio_trigger",
2232 .id = 1, 2758 .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
2233 .dev = { 2759 .resource = iio_gpio_trigger_resources,
2234 .platform_data = &adp150_userspace_comsumer_data,
2235 },
2236}; 2760};
2237#endif 2761#endif
2238#endif
2239
2240 2762
2241static struct platform_device *stamp_devices[] __initdata = { 2763static struct platform_device *stamp_devices[] __initdata = {
2242 2764
@@ -2347,17 +2869,28 @@ static struct platform_device *stamp_devices[] __initdata = {
2347 &stamp_flash_device, 2869 &stamp_flash_device,
2348#endif 2870#endif
2349 2871
2350#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 2872#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2873 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2874 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2875 &bfin_pcm,
2876#endif
2877
2878#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2879 &bfin_ad73311_codec_device,
2880#endif
2881
2882#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
2351 &bfin_i2s, 2883 &bfin_i2s,
2352#endif 2884#endif
2353 2885
2354#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 2886#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
2355 &bfin_tdm, 2887 &bfin_tdm,
2356#endif 2888#endif
2357 2889
2358#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 2890#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
2359 &bfin_ac97, 2891 &bfin_ac97,
2360#endif 2892#endif
2893
2361#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) 2894#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
2362#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ 2895#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
2363 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) 2896 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
@@ -2369,14 +2902,18 @@ static struct platform_device *stamp_devices[] __initdata = {
2369#endif 2902#endif
2370#endif 2903#endif
2371 2904
2372#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) 2905#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
2373 &adp_switch_device, 2906 &adp_switch_device,
2374#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \ 2907#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2375 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE) 2908 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2376 &adp122_userspace_consumer_device, 2909 &adp122_userspace_consumer_device,
2377 &adp150_userspace_consumer_device,
2378#endif 2910#endif
2379#endif 2911#endif
2912
2913#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2914 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2915 &iio_gpio_trigger,
2916#endif
2380}; 2917};
2381 2918
2382static int __init stamp_init(void) 2919static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 4f0a2e72ce4c..164a7e02c022 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
74}; 74};
75#endif 75#endif
76 76
77#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0, 79 .enable_dma = 0,
80 .bits_per_word = 16, 80 .bits_per_word = 16,
@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
113 }, 113 },
114#endif 114#endif
115 115
116#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 117 {
118 .modalias = "ad1836", 118 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 120 .bus_num = 0,
121 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 121 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info, 122 .controller_data = &ad1836_spi_chip_info,
123 }, 123 },
124#endif 124#endif
@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
230 }, { 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
234 }, 234 },
235}; 235};
236 236
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
512 }, 512 },
513}; 513};
514 514
515unsigned short bfin_sport0_peripherals[] = { 515static unsigned short bfin_sport0_peripherals[] = {
516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
518}; 518};
519 519
520static struct platform_device bfin_sport0_uart_device = { 520static struct platform_device bfin_sport0_uart_device = {
@@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
546 }, 546 },
547}; 547};
548 548
549unsigned short bfin_sport1_peripherals[] = { 549static unsigned short bfin_sport1_peripherals[] = {
550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
552}; 552};
553 553
554static struct platform_device bfin_sport1_uart_device = { 554static struct platform_device bfin_sport1_uart_device = {
@@ -564,13 +564,35 @@ static struct platform_device bfin_sport1_uart_device = {
564#endif 564#endif
565 565
566#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 566#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
567#include <linux/bfin_mac.h>
568static const unsigned short bfin_mac_peripherals[] = P_MII0;
569
570static struct bfin_phydev_platform_data bfin_phydev_data[] = {
571 {
572 .addr = 1,
573 .irq = IRQ_MAC_PHYINT,
574 },
575};
576
577static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
578 .phydev_number = 1,
579 .phydev_data = bfin_phydev_data,
580 .phy_mode = PHY_INTERFACE_MODE_MII,
581 .mac_peripherals = bfin_mac_peripherals,
582};
583
567static struct platform_device bfin_mii_bus = { 584static struct platform_device bfin_mii_bus = {
568 .name = "bfin_mii_bus", 585 .name = "bfin_mii_bus",
586 .dev = {
587 .platform_data = &bfin_mii_bus_data,
588 }
569}; 589};
570 590
571static struct platform_device bfin_mac_device = { 591static struct platform_device bfin_mac_device = {
572 .name = "bfin_mac", 592 .name = "bfin_mac",
573 .dev.platform_data = &bfin_mii_bus, 593 .dev = {
594 .platform_data = &bfin_mii_bus,
595 }
574}; 596};
575#endif 597#endif
576 598
@@ -720,7 +742,7 @@ static int __init tcm_bf537_init(void)
720#endif 742#endif
721 743
722#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 744#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
723 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 745 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
724#endif 746#endif
725 return 0; 747 return 0;
726} 748}
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 5c8c4ed517bb..5c62e99c9fac 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 43df6afd22ad..7f8e5a9f5db6 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,13 +5,13 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 14 * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -160,12 +160,16 @@
160#define ANOMALY_05000443 (1) 160#define ANOMALY_05000443 (1)
161/* False Hardware Error when RETI Points to Invalid Memory */ 161/* False Hardware Error when RETI Points to Invalid Memory */
162#define ANOMALY_05000461 (1) 162#define ANOMALY_05000461 (1)
163/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
164#define ANOMALY_05000462 (1)
163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 165/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
164#define ANOMALY_05000473 (1) 166#define ANOMALY_05000473 (1)
165/* Possible Lockup Condition whem Modifying PLL from External Memory */ 167/* Possible Lockup Condition whem Modifying PLL from External Memory */
166#define ANOMALY_05000475 (1) 168#define ANOMALY_05000475 (1)
167/* TESTSET Instruction Cannot Be Interrupted */ 169/* TESTSET Instruction Cannot Be Interrupted */
168#define ANOMALY_05000477 (1) 170#define ANOMALY_05000477 (1)
171/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
172#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
169/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 173/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
170#define ANOMALY_05000481 (1) 174#define ANOMALY_05000481 (1)
171/* IFLUSH sucks at life */ 175/* IFLUSH sucks at life */
@@ -204,6 +208,7 @@
204#define ANOMALY_05000363 (0) 208#define ANOMALY_05000363 (0)
205#define ANOMALY_05000364 (0) 209#define ANOMALY_05000364 (0)
206#define ANOMALY_05000380 (0) 210#define ANOMALY_05000380 (0)
211#define ANOMALY_05000383 (0)
207#define ANOMALY_05000386 (1) 212#define ANOMALY_05000386 (1)
208#define ANOMALY_05000389 (0) 213#define ANOMALY_05000389 (0)
209#define ANOMALY_05000400 (0) 214#define ANOMALY_05000400 (0)
@@ -211,6 +216,7 @@
211#define ANOMALY_05000430 (0) 216#define ANOMALY_05000430 (0)
212#define ANOMALY_05000432 (0) 217#define ANOMALY_05000432 (0)
213#define ANOMALY_05000435 (0) 218#define ANOMALY_05000435 (0)
219#define ANOMALY_05000440 (0)
214#define ANOMALY_05000447 (0) 220#define ANOMALY_05000447 (0)
215#define ANOMALY_05000448 (0) 221#define ANOMALY_05000448 (0)
216#define ANOMALY_05000456 (0) 222#define ANOMALY_05000456 (0)
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 635c91c526a3..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * Copyright 2006-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#include <linux/serial.h>
8#include <asm/dma.h>
9#include <asm/portmux.h>
10
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS
39
40# ifndef CONFIG_UART0_CTS_PIN
41# define CONFIG_UART0_CTS_PIN -1
42# endif
43
44# ifndef CONFIG_UART0_RTS_PIN
45# define CONFIG_UART0_RTS_PIN -1
46# endif
47
48# ifndef CONFIG_UART1_CTS_PIN
49# define CONFIG_UART1_CTS_PIN -1
50# endif
51
52# ifndef CONFIG_UART1_RTS_PIN
53# define CONFIG_UART1_RTS_PIN -1
54# endif
55#endif
56
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 int cts_pin;
79 int rts_pin;
80#endif
81};
82
83/* The hardware clears the LSR bits upon read, so we need to cache
84 * some of the more fun bits in software so they don't get lost
85 * when checking the LSR in other code paths (TX).
86 */
87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
88{
89 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
90 uart->lsr |= (lsr & (BI|FE|PE|OE));
91 return lsr | uart->lsr;
92}
93
94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
95{
96 uart->lsr = 0;
97 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
98}
99
100struct bfin_serial_res {
101 unsigned long uart_base_addr;
102 int uart_irq;
103 int uart_status_irq;
104#ifdef CONFIG_SERIAL_BFIN_DMA
105 unsigned int uart_tx_dma_channel;
106 unsigned int uart_rx_dma_channel;
107#endif
108#ifdef CONFIG_SERIAL_BFIN_CTSRTS
109 int uart_cts_pin;
110 int uart_rts_pin;
111#endif
112};
113
114struct bfin_serial_res bfin_serial_resource[] = {
115#ifdef CONFIG_SERIAL_BFIN_UART0
116 {
117 0xFFC00400,
118 IRQ_UART0_RX,
119 IRQ_UART0_ERROR,
120#ifdef CONFIG_SERIAL_BFIN_DMA
121 CH_UART0_TX,
122 CH_UART0_RX,
123#endif
124#ifdef CONFIG_SERIAL_BFIN_CTSRTS
125 CONFIG_UART0_CTS_PIN,
126 CONFIG_UART0_RTS_PIN,
127#endif
128 },
129#endif
130#ifdef CONFIG_SERIAL_BFIN_UART1
131 {
132 0xFFC02000,
133 IRQ_UART1_RX,
134 IRQ_UART1_ERROR,
135#ifdef CONFIG_SERIAL_BFIN_DMA
136 CH_UART1_TX,
137 CH_UART1_RX,
138#endif
139#ifdef CONFIG_SERIAL_BFIN_CTSRTS
140 CONFIG_UART1_CTS_PIN,
141 CONFIG_UART1_RTS_PIN,
142#endif
143 },
144#endif
145};
146
147#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
10#define BF537_FAMILY 10#define BF537_FAMILY
11 11
12#include "bf537.h" 12#include "bf537.h"
13#include "defBF534.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
15#include <asm/def_LPBlackfin.h>
16#ifdef CONFIG_BF534
17# include "defBF534.h"
18#endif
16#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 19#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
17#include "defBF537.h" 20# include "defBF537.h"
18#endif 21#endif
19 22
20#if !defined(__ASSEMBLY__) 23#if !defined(__ASSEMBLY__)
21#include "cdefBF534.h" 24# include <asm/cdef_LPBlackfin.h>
22 25# ifdef CONFIG_BF534
23#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 26# include "cdefBF534.h"
24#include "cdefBF537.h" 27# endif
28# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
29# include "cdefBF537.h"
30# endif
25#endif 31#endif
26#endif
27
28#define BFIN_UART_NR_PORTS 2
29
30#define OFFSET_THR 0x00 /* Transmit Holding register */
31#define OFFSET_RBR 0x00 /* Receive Buffer register */
32#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
33#define OFFSET_IER 0x04 /* Interrupt Enable Register */
34#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
35#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
36#define OFFSET_LCR 0x0C /* Line Control Register */
37#define OFFSET_MCR 0x10 /* Modem Control Register */
38#define OFFSET_LSR 0x14 /* Line Status Register */
39#define OFFSET_MSR 0x18 /* Modem Status Register */
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 32
43#endif 33#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index 91825c9bd226..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF534_H 7#ifndef _CDEF_BF534_H
8#define _CDEF_BF534_H 8#define _CDEF_BF534_H
9 9
10#include <asm/blackfin.h>
11
12/* Include all Core registers and bit definitions */
13#include "defBF534.h"
14
15/* Include core specific register pointer definitions */
16#include <asm/cdef_LPBlackfin.h>
17
18/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
19#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
20#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
355#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 347#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
356 348
357/* DMA Traffic Control Registers */ 349/* DMA Traffic Control Registers */
358#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 350#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
359#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) 351#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
360#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 352#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
361#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) 353#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
362
363/* Alternate deprecated register names (below) provided for backwards code compatibility */
364#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
365#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
366#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
367#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
368 354
369/* DMA Controller */ 355/* DMA Controller */
370#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 356#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
@@ -1747,51 +1733,4 @@
1747#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1733#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1748#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) 1734#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1749 1735
1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h>
1752
1753/* Writing to PLL_CTL initiates a PLL relock sequence. */
1754static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1755{
1756 unsigned long flags, iwr;
1757
1758 if (val == bfin_read_PLL_CTL())
1759 return;
1760
1761 local_irq_save_hw(flags);
1762 /* Enable the PLL Wakeup bit in SIC IWR */
1763 iwr = bfin_read32(SIC_IWR);
1764 /* Only allow PPL Wakeup) */
1765 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1766
1767 bfin_write16(PLL_CTL, val);
1768 SSYNC();
1769 asm("IDLE;");
1770
1771 bfin_write32(SIC_IWR, iwr);
1772 local_irq_restore_hw(flags);
1773}
1774
1775/* Writing to VR_CTL initiates a PLL relock sequence. */
1776static __inline__ void bfin_write_VR_CTL(unsigned int val)
1777{
1778 unsigned long flags, iwr;
1779
1780 if (val == bfin_read_VR_CTL())
1781 return;
1782
1783 local_irq_save_hw(flags);
1784 /* Enable the PLL Wakeup bit in SIC IWR */
1785 iwr = bfin_read32(SIC_IWR);
1786 /* Only allow PPL Wakeup) */
1787 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1788
1789 bfin_write16(VR_CTL, val);
1790 SSYNC();
1791 asm("IDLE;");
1792
1793 bfin_write32(SIC_IWR, iwr);
1794 local_irq_restore_hw(flags);
1795}
1796
1797#endif /* _CDEF_BF534_H */ 1736#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -10,9 +10,6 @@
10/* Include MMRs Common to BF534 */ 10/* Include MMRs Common to BF534 */
11#include "cdefBF534.h" 11#include "cdefBF534.h"
12 12
13/* Include all Core registers and bit definitions */
14#include "defBF537.h"
15
16/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ 13/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
17/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
18#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) 15#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 6f56907a18c0..4a031dde173f 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF534_H 7#ifndef _DEF_BF534_H
8#define _DEF_BF534_H 8#define _DEF_BF534_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/************************************************************************************ 10/************************************************************************************
14** System MMR Register Map 11** System MMR Register Map
15*************************************************************************************/ 12*************************************************************************************/
@@ -193,12 +190,8 @@
193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 190#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
194 191
195/* DMA Traffic Control Registers */ 192/* DMA Traffic Control Registers */
196#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 193#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 194#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
198
199/* Alternate deprecated register names (below) provided for backwards code compatibility */
200#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
202 195
203/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 196/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 197#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -1029,92 +1022,6 @@
1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1022#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1023#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031 1024
1032/* ************** UART CONTROLLER MASKS *************************/
1033/* UARTx_LCR Masks */
1034#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035#define STB 0x04 /* Stop Bits */
1036#define PEN 0x08 /* Parity Enable */
1037#define EPS 0x10 /* Even Parity Select */
1038#define STP 0x20 /* Stick Parity */
1039#define SB 0x40 /* Set Break */
1040#define DLAB 0x80 /* Divisor Latch Access */
1041
1042/* UARTx_MCR Mask */
1043#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044#define LOOP_ENA_P 0x04
1045/* UARTx_LSR Masks */
1046#define DR 0x01 /* Data Ready */
1047#define OE 0x02 /* Overrun Error */
1048#define PE 0x04 /* Parity Error */
1049#define FE 0x08 /* Framing Error */
1050#define BI 0x10 /* Break Interrupt */
1051#define THRE 0x20 /* THR Empty */
1052#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054/* UARTx_IER Masks */
1055#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059/* UARTx_IIR Masks */
1060#define NINT 0x01 /* Pending Interrupt */
1061#define IIR_TX_READY 0x02 /* UART_THR empty */
1062#define IIR_RX_READY 0x04 /* Receive data ready */
1063#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064#define IIR_STATUS 0x06
1065
1066/* UARTx_GCTL Masks */
1067#define UCEN 0x01 /* Enable UARTx Clocks */
1068#define IREN 0x02 /* Enable IrDA Mode */
1069#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1075/* SPI_CTL Masks */
1076#define TIMOD 0x0003 /* Transfer Initiate Mode */
1077#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1078#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1079#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1080#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1081#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1082#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1083#define PSSE 0x0010 /* Slave-Select Input Enable */
1084#define EMISO 0x0020 /* Enable MISO As Output */
1085#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1086#define LSBF 0x0200 /* LSB First */
1087#define CPHA 0x0400 /* Clock Phase */
1088#define CPOL 0x0800 /* Clock Polarity */
1089#define MSTR 0x1000 /* Master/Slave* */
1090#define WOM 0x2000 /* Write Open Drain Master */
1091#define SPE 0x4000 /* SPI Enable */
1092
1093/* SPI_FLG Masks */
1094#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1095#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1096#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1097#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1098#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1099#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1100#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1101#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1102#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1103#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1104#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1105#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1106#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1107#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1108
1109/* SPI_STAT Masks */
1110#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1111#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1112#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1113#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1114#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1115#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1116#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1117
1118/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1025/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1119/* TIMER_ENABLE Masks */ 1026/* TIMER_ENABLE Masks */
1120#define TIMEN0 0x0001 /* Enable Timer 0 */ 1027#define TIMEN0 0x0001 /* Enable Timer 0 */
@@ -1185,62 +1092,6 @@
1185#define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1092#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1186#define ERR_TYP 0xC000 /* Error Type */ 1093#define ERR_TYP 0xC000 /* Error Type */
1187 1094
1188/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1189/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1190/* Port F Masks */
1191#define PF0 0x0001
1192#define PF1 0x0002
1193#define PF2 0x0004
1194#define PF3 0x0008
1195#define PF4 0x0010
1196#define PF5 0x0020
1197#define PF6 0x0040
1198#define PF7 0x0080
1199#define PF8 0x0100
1200#define PF9 0x0200
1201#define PF10 0x0400
1202#define PF11 0x0800
1203#define PF12 0x1000
1204#define PF13 0x2000
1205#define PF14 0x4000
1206#define PF15 0x8000
1207
1208/* Port G Masks */
1209#define PG0 0x0001
1210#define PG1 0x0002
1211#define PG2 0x0004
1212#define PG3 0x0008
1213#define PG4 0x0010
1214#define PG5 0x0020
1215#define PG6 0x0040
1216#define PG7 0x0080
1217#define PG8 0x0100
1218#define PG9 0x0200
1219#define PG10 0x0400
1220#define PG11 0x0800
1221#define PG12 0x1000
1222#define PG13 0x2000
1223#define PG14 0x4000
1224#define PG15 0x8000
1225
1226/* Port H Masks */
1227#define PH0 0x0001
1228#define PH1 0x0002
1229#define PH2 0x0004
1230#define PH3 0x0008
1231#define PH4 0x0010
1232#define PH5 0x0020
1233#define PH6 0x0040
1234#define PH7 0x0080
1235#define PH8 0x0100
1236#define PH9 0x0200
1237#define PH10 0x0400
1238#define PH11 0x0800
1239#define PH12 0x1000
1240#define PH13 0x2000
1241#define PH14 0x4000
1242#define PH15 0x8000
1243
1244/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1095/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1245/* EBIU_AMGCTL Masks */ 1096/* EBIU_AMGCTL Masks */
1246#define AMCKEN 0x0001 /* Enable CLKOUT */ 1097#define AMCKEN 0x0001 /* Enable CLKOUT */
@@ -1567,7 +1418,7 @@
1567#define SADD_LEN 0x0002 /* Slave Address Length */ 1418#define SADD_LEN 0x0002 /* Slave Address Length */
1568#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1419#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1569#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 1420#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1570#define GEN 0x0010 /* General Call Adrress Matching Enabled */ 1421#define GEN 0x0010 /* General Call Address Matching Enabled */
1571 1422
1572/* TWI_SLAVE_STAT Masks */ 1423/* TWI_SLAVE_STAT Masks */
1573#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1424#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
@@ -1669,24 +1520,6 @@
1669#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ 1520#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1670#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ 1521#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1671 1522
1672/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1673/* HDMAx_CTL Masks */
1674#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1675#define REP 0x0002 /* HDMA Request Polarity */
1676#define UTE 0x0004 /* Urgency Threshold Enable */
1677#define OIE 0x0010 /* Overflow Interrupt Enable */
1678#define BDIE 0x0020 /* Block Done Interrupt Enable */
1679#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1680#define DRQ 0x0300 /* HDMA Request Type */
1681#define DRQ_NONE 0x0000 /* No Request */
1682#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1683#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1684#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1685#define RBC 0x1000 /* Reload BCNT With IBCNT */
1686#define PS 0x2000 /* HDMA Pin Status */
1687#define OI 0x4000 /* Overflow Interrupt Generated */
1688#define BDI 0x8000 /* Block Done Interrupt Generated */
1689
1690/* entry addresses of the user-callable Boot ROM functions */ 1523/* entry addresses of the user-callable Boot ROM functions */
1691 1524
1692#define _BOOTROM_RESET 0xEF000000 1525#define _BOOTROM_RESET 0xEF000000
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF537_H 7#ifndef _DEF_BF537_H
8#define _DEF_BF537_H 8#define _DEF_BF537_H
9 9
10/* Include all Core registers and bit definitions*/
11#include <asm/cdef_LPBlackfin.h>
12
13/* Include all MMR and bit defines common to BF534 */ 10/* Include all MMR and bit defines common to BF534 */
14#include "defBF534.h" 11#include "defBF534.h"
15 12
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 1a6d617c5fcf..b6ed8235bda4 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -7,193 +7,178 @@
7#ifndef _BF537_IRQ_H_ 7#ifndef _BF537_IRQ_H_
8#define _BF537_IRQ_H_ 8#define _BF537_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 * Event Source Core Event Name 12#define NR_PERI_INTS 32
13 * Core Emulation ** 13
14 * Events (highest priority) EMU 0 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 * Reset RST 1 15#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
16 * NMI NMI 2 16#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
17 * Exception EVX 3 17#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
18 * Reserved -- 4 18#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
19 * Hardware Error IVHW 5 19#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
20 * Core Timer IVTMR 6 20#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
21 * ..... 21#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
22 * 22#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
23 * Softirq IVG14 23#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
24 * System Call -- 24#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
25 * (lowest priority) IVG15 25#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
26 */ 26#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
27 27#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
28#define SYS_IRQS 39 28#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
29#define NR_PERI_INTS 32 29#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
30 30#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
31/* The ABSTRACT IRQ definitions */ 31#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
32/** the first seven of the following are fixed, the rest you change if you need to **/ 32#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
33#define IRQ_EMU 0 /*Emulation */ 33#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
34#define IRQ_RST 1 /*reset */ 34#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
35#define IRQ_NMI 2 /*Non Maskable */ 35#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
36#define IRQ_EVX 3 /*Exception */ 36#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
37#define IRQ_UNUSED 4 /*- unused interrupt*/ 37#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
38#define IRQ_HWERR 5 /*Hardware Error */ 38#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
39#define IRQ_CORETMR 6 /*Core timer */ 39#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
40 40#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
41#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 41#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
42#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 42#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
43#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ 43#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
44#define IRQ_RTC 10 /*RTC Interrupt */ 44#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
45#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */ 45#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
46#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */ 46
47#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */ 47#define SYS_IRQS 39
48#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */ 48
49#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */ 49#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
50#define IRQ_TWI 16 /*TWI Interrupt */ 50#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
51#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */ 51#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
52#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */ 52#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
53#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */ 53#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
54#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */ 54#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
55#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */ 55#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
56#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */ 56#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
57#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 57
58#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 58#define IRQ_PF0 50
59#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 59#define IRQ_PF1 51
60#define IRQ_TIMER0 26 /*Timer 0 */ 60#define IRQ_PF2 52
61#define IRQ_TIMER1 27 /*Timer 1 */ 61#define IRQ_PF3 53
62#define IRQ_TIMER2 28 /*Timer 2 */ 62#define IRQ_PF4 54
63#define IRQ_TIMER3 29 /*Timer 3 */ 63#define IRQ_PF5 55
64#define IRQ_TIMER4 30 /*Timer 4 */ 64#define IRQ_PF6 56
65#define IRQ_TIMER5 31 /*Timer 5 */ 65#define IRQ_PF7 57
66#define IRQ_TIMER6 32 /*Timer 6 */ 66#define IRQ_PF8 58
67#define IRQ_TIMER7 33 /*Timer 7 */ 67#define IRQ_PF9 59
68#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 68#define IRQ_PF10 60
69#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 69#define IRQ_PF11 61
70#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 70#define IRQ_PF12 62
71#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 71#define IRQ_PF13 63
72#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 72#define IRQ_PF14 64
73#define IRQ_WATCH 38 /*Watch Dog Timer */ 73#define IRQ_PF15 65
74 74
75#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 75#define IRQ_PG0 66
76#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 76#define IRQ_PG1 67
77#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */ 77#define IRQ_PG2 68
78#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ 78#define IRQ_PG3 69
79#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ 79#define IRQ_PG4 70
80#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ 80#define IRQ_PG5 71
81#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */ 81#define IRQ_PG6 72
82#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */ 82#define IRQ_PG7 73
83 83#define IRQ_PG8 74
84#define IRQ_PF0 50 84#define IRQ_PG9 75
85#define IRQ_PF1 51 85#define IRQ_PG10 76
86#define IRQ_PF2 52 86#define IRQ_PG11 77
87#define IRQ_PF3 53 87#define IRQ_PG12 78
88#define IRQ_PF4 54 88#define IRQ_PG13 79
89#define IRQ_PF5 55 89#define IRQ_PG14 80
90#define IRQ_PF6 56 90#define IRQ_PG15 81
91#define IRQ_PF7 57 91
92#define IRQ_PF8 58 92#define IRQ_PH0 82
93#define IRQ_PF9 59 93#define IRQ_PH1 83
94#define IRQ_PF10 60 94#define IRQ_PH2 84
95#define IRQ_PF11 61 95#define IRQ_PH3 85
96#define IRQ_PF12 62 96#define IRQ_PH4 86
97#define IRQ_PF13 63 97#define IRQ_PH5 87
98#define IRQ_PF14 64 98#define IRQ_PH6 88
99#define IRQ_PF15 65 99#define IRQ_PH7 89
100 100#define IRQ_PH8 90
101#define IRQ_PG0 66 101#define IRQ_PH9 91
102#define IRQ_PG1 67 102#define IRQ_PH10 92
103#define IRQ_PG2 68 103#define IRQ_PH11 93
104#define IRQ_PG3 69 104#define IRQ_PH12 94
105#define IRQ_PG4 70 105#define IRQ_PH13 95
106#define IRQ_PG5 71 106#define IRQ_PH14 96
107#define IRQ_PG6 72 107#define IRQ_PH15 97
108#define IRQ_PG7 73 108
109#define IRQ_PG8 74 109#define GPIO_IRQ_BASE IRQ_PF0
110#define IRQ_PG9 75 110
111#define IRQ_PG10 76 111#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
112#define IRQ_PG11 77 112#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
113#define IRQ_PG12 78 113#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
114#define IRQ_PG13 79 114#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
115#define IRQ_PG14 80 115#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
116#define IRQ_PG15 81 116#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
117 117#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
118#define IRQ_PH0 82 118#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
119#define IRQ_PH1 83 119
120#define IRQ_PH2 84 120#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
121#define IRQ_PH3 85 121#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
122#define IRQ_PH4 86 122
123#define IRQ_PH5 87 123#if 0 /* No Interrupt B support (yet) */
124#define IRQ_PH6 88 124#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
125#define IRQ_PH7 89 125#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
126#define IRQ_PH8 90 126#else
127#define IRQ_PH9 91 127#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
128#define IRQ_PH10 92 128#endif
129#define IRQ_PH11 93 129
130#define IRQ_PH12 94 130#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
131#define IRQ_PH13 95 131#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
132#define IRQ_PH14 96 132
133#define IRQ_PH15 97 133#if 0 /* No Interrupt B support (yet) */
134 134#define IRQ_WATCH 112 /* Watchdog Timer */
135#define GPIO_IRQ_BASE IRQ_PF0 135#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
136 136#else
137#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ 137#define IRQ_WATCH IRQ_PF_INTB_WATCH
138#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ 138#endif
139#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ 139
140#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ 140#define NR_MACH_IRQS (113 + 1)
141#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ 141
142#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ 142/* IAR0 BIT FIELDS */
143#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ 143#define IRQ_PLL_WAKEUP_POS 0
144#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 144#define IRQ_DMA_ERROR_POS 4
145 145#define IRQ_ERROR_POS 8
146#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 146#define IRQ_RTC_POS 12
147#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 147#define IRQ_PPI_POS 16
148 148#define IRQ_SPORT0_RX_POS 20
149#define IVG7 7 149#define IRQ_SPORT0_TX_POS 24
150#define IVG8 8 150#define IRQ_SPORT1_RX_POS 28
151#define IVG9 9 151
152#define IVG10 10 152/* IAR1 BIT FIELDS */
153#define IVG11 11 153#define IRQ_SPORT1_TX_POS 0
154#define IVG12 12 154#define IRQ_TWI_POS 4
155#define IVG13 13 155#define IRQ_SPI_POS 8
156#define IVG14 14 156#define IRQ_UART0_RX_POS 12
157#define IVG15 15 157#define IRQ_UART0_TX_POS 16
158 158#define IRQ_UART1_RX_POS 20
159/* IAR0 BIT FIELDS*/ 159#define IRQ_UART1_TX_POS 24
160#define IRQ_PLL_WAKEUP_POS 0 160#define IRQ_CAN_RX_POS 28
161#define IRQ_DMA_ERROR_POS 4 161
162#define IRQ_ERROR_POS 8 162/* IAR2 BIT FIELDS */
163#define IRQ_RTC_POS 12 163#define IRQ_CAN_TX_POS 0
164#define IRQ_PPI_POS 16 164#define IRQ_MAC_RX_POS 4
165#define IRQ_SPORT0_RX_POS 20 165#define IRQ_MAC_TX_POS 8
166#define IRQ_SPORT0_TX_POS 24 166#define IRQ_TIMER0_POS 12
167#define IRQ_SPORT1_RX_POS 28 167#define IRQ_TIMER1_POS 16
168 168#define IRQ_TIMER2_POS 20
169/* IAR1 BIT FIELDS*/ 169#define IRQ_TIMER3_POS 24
170#define IRQ_SPORT1_TX_POS 0 170#define IRQ_TIMER4_POS 28
171#define IRQ_TWI_POS 4 171
172#define IRQ_SPI_POS 8 172/* IAR3 BIT FIELDS */
173#define IRQ_UART0_RX_POS 12 173#define IRQ_TIMER5_POS 0
174#define IRQ_UART0_TX_POS 16 174#define IRQ_TIMER6_POS 4
175#define IRQ_UART1_RX_POS 20 175#define IRQ_TIMER7_POS 8
176#define IRQ_UART1_TX_POS 24 176#define IRQ_PROG_INTA_POS 12
177#define IRQ_CAN_RX_POS 28 177#define IRQ_PORTG_INTB_POS 16
178 178#define IRQ_MEM_DMA0_POS 20
179/* IAR2 BIT FIELDS*/ 179#define IRQ_MEM_DMA1_POS 24
180#define IRQ_CAN_TX_POS 0 180#define IRQ_WATCH_POS 28
181#define IRQ_MAC_RX_POS 4 181
182#define IRQ_MAC_TX_POS 8 182#define init_mach_irq init_mach_irq
183#define IRQ_TIMER0_POS 12 183
184#define IRQ_TIMER1_POS 16 184#endif
185#define IRQ_TIMER2_POS 20
186#define IRQ_TIMER3_POS 24
187#define IRQ_TIMER4_POS 28
188
189/* IAR3 BIT FIELDS*/
190#define IRQ_TIMER5_POS 0
191#define IRQ_TIMER6_POS 4
192#define IRQ_TIMER7_POS 8
193#define IRQ_PROG_INTA_POS 12
194#define IRQ_PORTG_INTB_POS 16
195#define IRQ_MEM_DMA0_POS 20
196#define IRQ_MEM_DMA1_POS 24
197#define IRQ_WATCH_POS 28
198
199#endif /* _BF537_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
new file mode 100644
index 000000000000..94cca674d835
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -0,0 +1 @@
#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index f6500622b35d..2137a209a22b 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -10,6 +10,13 @@
10#include <linux/irq.h> 10#include <linux/irq.h>
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12 12
13#include <asm/irq_handler.h>
14#include <asm/bfin5xx_spi.h>
15#include <asm/bfin_sport.h>
16#include <asm/bfin_can.h>
17#include <asm/bfin_dma.h>
18#include <asm/dpmc.h>
19
13void __init program_IAR(void) 20void __init program_IAR(void)
14{ 21{
15 /* Program the IAR0 Register with the configured priority */ 22 /* Program the IAR0 Register with the configured priority */
@@ -51,3 +58,159 @@ void __init program_IAR(void)
51 58
52 SSYNC(); 59 SSYNC();
53} 60}
61
62#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
63#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
64#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
65#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
66#define UART_ERR_MASK (0x6) /* UART_IIR */
67#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
68
69static int error_int_mask;
70
71static void bf537_generic_error_mask_irq(struct irq_data *d)
72{
73 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
74 if (!error_int_mask)
75 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
76}
77
78static void bf537_generic_error_unmask_irq(struct irq_data *d)
79{
80 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
81 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
82}
83
84static struct irq_chip bf537_generic_error_irqchip = {
85 .name = "ERROR",
86 .irq_ack = bfin_ack_noop,
87 .irq_mask_ack = bf537_generic_error_mask_irq,
88 .irq_mask = bf537_generic_error_mask_irq,
89 .irq_unmask = bf537_generic_error_unmask_irq,
90};
91
92static void bf537_demux_error_irq(unsigned int int_err_irq,
93 struct irq_desc *inta_desc)
94{
95 int irq = 0;
96
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
98 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
99 irq = IRQ_MAC_ERROR;
100 else
101#endif
102 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
103 irq = IRQ_SPORT0_ERROR;
104 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
105 irq = IRQ_SPORT1_ERROR;
106 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
107 irq = IRQ_PPI_ERROR;
108 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
109 irq = IRQ_CAN_ERROR;
110 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
111 irq = IRQ_SPI_ERROR;
112 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
113 irq = IRQ_UART0_ERROR;
114 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
115 irq = IRQ_UART1_ERROR;
116
117 if (irq) {
118 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
119 bfin_handle_irq(irq);
120 else {
121
122 switch (irq) {
123 case IRQ_PPI_ERROR:
124 bfin_write_PPI_STATUS(PPI_ERR_MASK);
125 break;
126#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
127 case IRQ_MAC_ERROR:
128 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
129 break;
130#endif
131 case IRQ_SPORT0_ERROR:
132 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
133 break;
134
135 case IRQ_SPORT1_ERROR:
136 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
137 break;
138
139 case IRQ_CAN_ERROR:
140 bfin_write_CAN_GIS(CAN_ERR_MASK);
141 break;
142
143 case IRQ_SPI_ERROR:
144 bfin_write_SPI_STAT(SPI_ERR_MASK);
145 break;
146
147 default:
148 break;
149 }
150
151 pr_debug("IRQ %d:"
152 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
153 irq);
154 }
155 } else
156 pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
157 __func__);
158
159}
160
161#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
162static int mac_rx_int_mask;
163
164static void bf537_mac_rx_mask_irq(struct irq_data *d)
165{
166 mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
167 if (!mac_rx_int_mask)
168 bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
169}
170
171static void bf537_mac_rx_unmask_irq(struct irq_data *d)
172{
173 bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
174 mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
175}
176
177static struct irq_chip bf537_mac_rx_irqchip = {
178 .name = "ERROR",
179 .irq_ack = bfin_ack_noop,
180 .irq_mask_ack = bf537_mac_rx_mask_irq,
181 .irq_mask = bf537_mac_rx_mask_irq,
182 .irq_unmask = bf537_mac_rx_unmask_irq,
183};
184
185static void bf537_demux_mac_rx_irq(unsigned int int_irq,
186 struct irq_desc *desc)
187{
188 if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
189 bfin_handle_irq(IRQ_MAC_RX);
190 else
191 bfin_demux_gpio_irq(int_irq, desc);
192}
193#endif
194
195void __init init_mach_irq(void)
196{
197 int irq;
198
199#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
200 /* Clear EMAC Interrupt Status bits so we can demux it later */
201 bfin_write_EMAC_SYSTAT(-1);
202#endif
203
204 irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
205 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
206 irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
207 handle_level_irq);
208
209#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
210 irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
211 irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
212 irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
213
214 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
215#endif
216}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 06:14:02 -0400