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authorMike Frysinger <vapier@gentoo.org>2011-03-30 03:59:00 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:42 -0400
commit3dd666067d2b285724c828946e83100ea4c43d4b (patch)
treebb0e0c060013e12a7d6674f8139a5fec59cf6fbc /arch/blackfin/mach-bf537/include
parent6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff)
Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h303
1 files changed, 152 insertions, 151 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2a8194eadb4c..09234b75aa77 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -9,154 +9,155 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define SYS_IRQS 39 12#define NR_PERI_INTS 32
13#define NR_PERI_INTS 32 13
14 14#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 15#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 16#define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */
17#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ 17#define IRQ_RTC 10 /* RTC Interrupt */
18#define IRQ_RTC 10 /*RTC Interrupt */ 18#define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */
19#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */ 19#define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */
20#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */ 20#define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */
21#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */ 21#define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */
22#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */ 22#define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */
23#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */ 23#define IRQ_TWI 16 /* TWI Interrupt */
24#define IRQ_TWI 16 /*TWI Interrupt */ 24#define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */
25#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */ 25#define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */
26#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */ 26#define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */
27#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */ 27#define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */
28#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */ 28#define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */
29#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */ 29#define IRQ_CAN_RX 22 /* CAN Receive Interrupt */
30#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */ 30#define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */
31#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 31#define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */
32#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 32#define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */
33#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 33#define IRQ_TIMER0 26 /* Timer 0 */
34#define IRQ_TIMER0 26 /*Timer 0 */ 34#define IRQ_TIMER1 27 /* Timer 1 */
35#define IRQ_TIMER1 27 /*Timer 1 */ 35#define IRQ_TIMER2 28 /* Timer 2 */
36#define IRQ_TIMER2 28 /*Timer 2 */ 36#define IRQ_TIMER3 29 /* Timer 3 */
37#define IRQ_TIMER3 29 /*Timer 3 */ 37#define IRQ_TIMER4 30 /* Timer 4 */
38#define IRQ_TIMER4 30 /*Timer 4 */ 38#define IRQ_TIMER5 31 /* Timer 5 */
39#define IRQ_TIMER5 31 /*Timer 5 */ 39#define IRQ_TIMER6 32 /* Timer 6 */
40#define IRQ_TIMER6 32 /*Timer 6 */ 40#define IRQ_TIMER7 33 /* Timer 7 */
41#define IRQ_TIMER7 33 /*Timer 7 */ 41#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
42#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 42#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
43#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 43#define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */
44#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 44#define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */
45#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 45#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
46#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 46#define IRQ_WATCH 38 /* Watch Dog Timer */
47#define IRQ_WATCH 38 /*Watch Dog Timer */ 47
48 48#define SYS_IRQS 39
49#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 49
50#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 50#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
51#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */ 51#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
52#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ 52#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
53#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ 53#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
54#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ 54#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
55#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */ 55#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
56#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */ 56#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
57 57#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
58#define IRQ_PF0 50 58
59#define IRQ_PF1 51 59#define IRQ_PF0 50
60#define IRQ_PF2 52 60#define IRQ_PF1 51
61#define IRQ_PF3 53 61#define IRQ_PF2 52
62#define IRQ_PF4 54 62#define IRQ_PF3 53
63#define IRQ_PF5 55 63#define IRQ_PF4 54
64#define IRQ_PF6 56 64#define IRQ_PF5 55
65#define IRQ_PF7 57 65#define IRQ_PF6 56
66#define IRQ_PF8 58 66#define IRQ_PF7 57
67#define IRQ_PF9 59 67#define IRQ_PF8 58
68#define IRQ_PF10 60 68#define IRQ_PF9 59
69#define IRQ_PF11 61 69#define IRQ_PF10 60
70#define IRQ_PF12 62 70#define IRQ_PF11 61
71#define IRQ_PF13 63 71#define IRQ_PF12 62
72#define IRQ_PF14 64 72#define IRQ_PF13 63
73#define IRQ_PF15 65 73#define IRQ_PF14 64
74 74#define IRQ_PF15 65
75#define IRQ_PG0 66 75
76#define IRQ_PG1 67 76#define IRQ_PG0 66
77#define IRQ_PG2 68 77#define IRQ_PG1 67
78#define IRQ_PG3 69 78#define IRQ_PG2 68
79#define IRQ_PG4 70 79#define IRQ_PG3 69
80#define IRQ_PG5 71 80#define IRQ_PG4 70
81#define IRQ_PG6 72 81#define IRQ_PG5 71
82#define IRQ_PG7 73 82#define IRQ_PG6 72
83#define IRQ_PG8 74 83#define IRQ_PG7 73
84#define IRQ_PG9 75 84#define IRQ_PG8 74
85#define IRQ_PG10 76 85#define IRQ_PG9 75
86#define IRQ_PG11 77 86#define IRQ_PG10 76
87#define IRQ_PG12 78 87#define IRQ_PG11 77
88#define IRQ_PG13 79 88#define IRQ_PG12 78
89#define IRQ_PG14 80 89#define IRQ_PG13 79
90#define IRQ_PG15 81 90#define IRQ_PG14 80
91 91#define IRQ_PG15 81
92#define IRQ_PH0 82 92
93#define IRQ_PH1 83 93#define IRQ_PH0 82
94#define IRQ_PH2 84 94#define IRQ_PH1 83
95#define IRQ_PH3 85 95#define IRQ_PH2 84
96#define IRQ_PH4 86 96#define IRQ_PH3 85
97#define IRQ_PH5 87 97#define IRQ_PH4 86
98#define IRQ_PH6 88 98#define IRQ_PH5 87
99#define IRQ_PH7 89 99#define IRQ_PH6 88
100#define IRQ_PH8 90 100#define IRQ_PH7 89
101#define IRQ_PH9 91 101#define IRQ_PH8 90
102#define IRQ_PH10 92 102#define IRQ_PH9 91
103#define IRQ_PH11 93 103#define IRQ_PH10 92
104#define IRQ_PH12 94 104#define IRQ_PH11 93
105#define IRQ_PH13 95 105#define IRQ_PH12 94
106#define IRQ_PH14 96 106#define IRQ_PH13 95
107#define IRQ_PH15 97 107#define IRQ_PH14 96
108 108#define IRQ_PH15 97
109#define GPIO_IRQ_BASE IRQ_PF0 109
110 110#define GPIO_IRQ_BASE IRQ_PF0
111#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ 111
112#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ 112#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
113#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ 113#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
114#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ 114#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
115#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ 115#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
116#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ 116#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
117#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ 117#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
118#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 118#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
119 119#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
120#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 120
121 121#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
122/* IAR0 BIT FIELDS*/ 122
123#define IRQ_PLL_WAKEUP_POS 0 123/* IAR0 BIT FIELDS */
124#define IRQ_DMA_ERROR_POS 4 124#define IRQ_PLL_WAKEUP_POS 0
125#define IRQ_ERROR_POS 8 125#define IRQ_DMA_ERROR_POS 4
126#define IRQ_RTC_POS 12 126#define IRQ_ERROR_POS 8
127#define IRQ_PPI_POS 16 127#define IRQ_RTC_POS 12
128#define IRQ_SPORT0_RX_POS 20 128#define IRQ_PPI_POS 16
129#define IRQ_SPORT0_TX_POS 24 129#define IRQ_SPORT0_RX_POS 20
130#define IRQ_SPORT1_RX_POS 28 130#define IRQ_SPORT0_TX_POS 24
131 131#define IRQ_SPORT1_RX_POS 28
132/* IAR1 BIT FIELDS*/ 132
133#define IRQ_SPORT1_TX_POS 0 133/* IAR1 BIT FIELDS */
134#define IRQ_TWI_POS 4 134#define IRQ_SPORT1_TX_POS 0
135#define IRQ_SPI_POS 8 135#define IRQ_TWI_POS 4
136#define IRQ_UART0_RX_POS 12 136#define IRQ_SPI_POS 8
137#define IRQ_UART0_TX_POS 16 137#define IRQ_UART0_RX_POS 12
138#define IRQ_UART1_RX_POS 20 138#define IRQ_UART0_TX_POS 16
139#define IRQ_UART1_TX_POS 24 139#define IRQ_UART1_RX_POS 20
140#define IRQ_CAN_RX_POS 28 140#define IRQ_UART1_TX_POS 24
141 141#define IRQ_CAN_RX_POS 28
142/* IAR2 BIT FIELDS*/ 142
143#define IRQ_CAN_TX_POS 0 143/* IAR2 BIT FIELDS */
144#define IRQ_MAC_RX_POS 4 144#define IRQ_CAN_TX_POS 0
145#define IRQ_MAC_TX_POS 8 145#define IRQ_MAC_RX_POS 4
146#define IRQ_TIMER0_POS 12 146#define IRQ_MAC_TX_POS 8
147#define IRQ_TIMER1_POS 16 147#define IRQ_TIMER0_POS 12
148#define IRQ_TIMER2_POS 20 148#define IRQ_TIMER1_POS 16
149#define IRQ_TIMER3_POS 24 149#define IRQ_TIMER2_POS 20
150#define IRQ_TIMER4_POS 28 150#define IRQ_TIMER3_POS 24
151 151#define IRQ_TIMER4_POS 28
152/* IAR3 BIT FIELDS*/ 152
153#define IRQ_TIMER5_POS 0 153/* IAR3 BIT FIELDS */
154#define IRQ_TIMER6_POS 4 154#define IRQ_TIMER5_POS 0
155#define IRQ_TIMER7_POS 8 155#define IRQ_TIMER6_POS 4
156#define IRQ_PROG_INTA_POS 12 156#define IRQ_TIMER7_POS 8
157#define IRQ_PORTG_INTB_POS 16 157#define IRQ_PROG_INTA_POS 12
158#define IRQ_MEM_DMA0_POS 20 158#define IRQ_PORTG_INTB_POS 16
159#define IRQ_MEM_DMA1_POS 24 159#define IRQ_MEM_DMA0_POS 20
160#define IRQ_WATCH_POS 28 160#define IRQ_MEM_DMA1_POS 24
161 161#define IRQ_WATCH_POS 28
162#endif /* _BF537_IRQ_H_ */ 162
163#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 19:47:43 -0500