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authorDavid Woodhouse <David.Woodhouse@intel.com>2010-10-30 07:35:11 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-10-30 07:35:11 -0400
commit67577927e8d7a1f4b09b4992df640eadc6aacb36 (patch)
tree2e9efe6b5745965faf0dcc084d4613d9356263f9 /arch/blackfin/mach-bf527
parent6fe4c590313133ebd5dadb769031489ff178ece1 (diff)
parent51f00a471ce8f359627dd99aeac322947a0e491b (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Conflicts: drivers/mtd/mtd_blkdevs.c Merge Grant's device-tree bits so that we can apply the subsequent fixes. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig10
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile2
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c870
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c12
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c6
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c25
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c986
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h82
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h45
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h63
10 files changed, 1975 insertions, 126 deletions
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
index b14c28810a44..1cc2667c10f1 100644
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ b/arch/blackfin/mach-bf527/boards/Kconfig
@@ -24,4 +24,14 @@ config BFIN526_EZBRD
24 help 24 help
25 BF526-EZBRD/EZKIT Lite board support. 25 BF526-EZBRD/EZKIT Lite board support.
26 26
27config BFIN527_AD7160EVAL
28 bool "BF527-AD7160-EVAL"
29 help
30 BF527-AD7160-EVAL board support.
31
32config BFIN527_TLL6527M
33 bool "The Learning Labs TLL6527M"
34 help
35 TLL6527M V1.0 platform support
36
27endchoice 37endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
index 51a5817c4a90..1d67da9f05ac 100644
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o 6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o 7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o 8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
9obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
10obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
new file mode 100644
index 000000000000..fc767ac76381
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -0,0 +1,870 @@
1/*
2 * Copyright 2004-20010 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/i2c.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <linux/leds.h>
21#include <linux/input.h>
22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },
51 [2] = { /* DMA IRQ */
52 .start = IRQ_USB_DMA,
53 .end = IRQ_USB_DMA,
54 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
55 },
56};
57
58static struct musb_hdrc_config musb_config = {
59 .multipoint = 0,
60 .dyn_fifo = 0,
61 .soft_con = 1,
62 .dma = 1,
63 .num_eps = 8,
64 .dma_channels = 8,
65 .gpio_vrsel = GPIO_PG13,
66 /* Some custom boards need to be active low, just set it to "0"
67 * if it is the case.
68 */
69 .gpio_vrsel_active = 1,
70};
71
72static struct musb_hdrc_platform_data musb_plat = {
73#if defined(CONFIG_USB_MUSB_OTG)
74 .mode = MUSB_OTG,
75#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
76 .mode = MUSB_HOST,
77#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
78 .mode = MUSB_PERIPHERAL,
79#endif
80 .config = &musb_config,
81};
82
83static u64 musb_dmamask = ~(u32)0;
84
85static struct platform_device musb_device = {
86 .name = "musb_hdrc",
87 .id = 0,
88 .dev = {
89 .dma_mask = &musb_dmamask,
90 .coherent_dma_mask = 0xffffffff,
91 .platform_data = &musb_plat,
92 },
93 .num_resources = ARRAY_SIZE(musb_resources),
94 .resource = musb_resources,
95};
96#endif
97
98#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
99static struct resource bf52x_ra158z_resources[] = {
100 {
101 .start = IRQ_PPI_ERROR,
102 .end = IRQ_PPI_ERROR,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device bf52x_ra158z_device = {
108 .name = "bfin-ra158z",
109 .id = -1,
110 .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
111 .resource = bf52x_ra158z_resources,
112};
113#endif
114
115#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
116static struct mtd_partition ad7160eval_partitions[] = {
117 {
118 .name = "bootloader(nor)",
119 .size = 0x40000,
120 .offset = 0,
121 }, {
122 .name = "linux kernel(nor)",
123 .size = 0x1C0000,
124 .offset = MTDPART_OFS_APPEND,
125 }, {
126 .name = "file system(nor)",
127 .size = MTDPART_SIZ_FULL,
128 .offset = MTDPART_OFS_APPEND,
129 }
130};
131
132static struct physmap_flash_data ad7160eval_flash_data = {
133 .width = 2,
134 .parts = ad7160eval_partitions,
135 .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
136};
137
138static struct resource ad7160eval_flash_resource = {
139 .start = 0x20000000,
140 .end = 0x203fffff,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct platform_device ad7160eval_flash_device = {
145 .name = "physmap-flash",
146 .id = 0,
147 .dev = {
148 .platform_data = &ad7160eval_flash_data,
149 },
150 .num_resources = 1,
151 .resource = &ad7160eval_flash_resource,
152};
153#endif
154
155#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
156static struct mtd_partition partition_info[] = {
157 {
158 .name = "linux kernel(nand)",
159 .offset = 0,
160 .size = 4 * 1024 * 1024,
161 },
162 {
163 .name = "file system(nand)",
164 .offset = MTDPART_OFS_APPEND,
165 .size = MTDPART_SIZ_FULL,
166 },
167};
168
169static struct bf5xx_nand_platform bf5xx_nand_platform = {
170 .data_width = NFC_NWIDTH_8,
171 .partitions = partition_info,
172 .nr_partitions = ARRAY_SIZE(partition_info),
173 .rd_dly = 3,
174 .wr_dly = 3,
175};
176
177static struct resource bf5xx_nand_resources[] = {
178 {
179 .start = NFC_CTL,
180 .end = NFC_DATA_RD + 2,
181 .flags = IORESOURCE_MEM,
182 },
183 {
184 .start = CH_NFC,
185 .end = CH_NFC,
186 .flags = IORESOURCE_IRQ,
187 },
188};
189
190static struct platform_device bf5xx_nand_device = {
191 .name = "bf5xx-nand",
192 .id = 0,
193 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
194 .resource = bf5xx_nand_resources,
195 .dev = {
196 .platform_data = &bf5xx_nand_platform,
197 },
198};
199#endif
200
201#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
208#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
209#include <linux/bfin_mac.h>
210static const unsigned short bfin_mac_peripherals[] = P_RMII0;
211
212static struct bfin_phydev_platform_data bfin_phydev_data[] = {
213 {
214 .addr = 1,
215 .irq = IRQ_MAC_PHYINT,
216 },
217};
218
219static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
220 .phydev_number = 1,
221 .phydev_data = bfin_phydev_data,
222 .phy_mode = PHY_INTERFACE_MODE_RMII,
223 .mac_peripherals = bfin_mac_peripherals,
224};
225
226static struct platform_device bfin_mii_bus = {
227 .name = "bfin_mii_bus",
228 .dev = {
229 .platform_data = &bfin_mii_bus_data,
230 }
231};
232
233static struct platform_device bfin_mac_device = {
234 .name = "bfin_mac",
235 .dev = {
236 .platform_data = &bfin_mii_bus,
237 }
238};
239#endif
240
241
242#if defined(CONFIG_MTD_M25P80) \
243 || defined(CONFIG_MTD_M25P80_MODULE)
244static struct mtd_partition bfin_spi_flash_partitions[] = {
245 {
246 .name = "bootloader(spi)",
247 .size = 0x00040000,
248 .offset = 0,
249 .mask_flags = MTD_CAP_ROM
250 }, {
251 .name = "linux kernel(spi)",
252 .size = MTDPART_SIZ_FULL,
253 .offset = MTDPART_OFS_APPEND,
254 }
255};
256
257static struct flash_platform_data bfin_spi_flash_data = {
258 .name = "m25p80",
259 .parts = bfin_spi_flash_partitions,
260 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
261 .type = "m25p16",
262};
263
264/* SPI flash chip (m25p64) */
265static struct bfin5xx_spi_chip spi_flash_chip_info = {
266 .enable_dma = 0, /* use dma transfer with this chip*/
267 .bits_per_word = 8,
268};
269#endif
270
271#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
272 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
273static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
274 .enable_dma = 0,
275 .bits_per_word = 16,
276};
277#endif
278
279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
280static struct bfin5xx_spi_chip mmc_spi_chip_info = {
281 .enable_dma = 0,
282 .bits_per_word = 8,
283};
284#endif
285
286#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
287static struct bfin5xx_spi_chip spidev_chip_info = {
288 .enable_dma = 0,
289 .bits_per_word = 8,
290};
291#endif
292
293#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
294static struct platform_device bfin_i2s = {
295 .name = "bfin-i2s",
296 .id = CONFIG_SND_BF5XX_SPORT_NUM,
297 /* TODO: add platform data here */
298};
299#endif
300
301#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
302static struct platform_device bfin_tdm = {
303 .name = "bfin-tdm",
304 .id = CONFIG_SND_BF5XX_SPORT_NUM,
305 /* TODO: add platform data here */
306};
307#endif
308
309static struct spi_board_info bfin_spi_board_info[] __initdata = {
310#if defined(CONFIG_MTD_M25P80) \
311 || defined(CONFIG_MTD_M25P80_MODULE)
312 {
313 /* the modalias must be the same as spi device driver name */
314 .modalias = "m25p80", /* Name of spi_driver for this device */
315 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
316 .bus_num = 0, /* Framework bus number */
317 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
318 .platform_data = &bfin_spi_flash_data,
319 .controller_data = &spi_flash_chip_info,
320 .mode = SPI_MODE_3,
321 },
322#endif
323#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
324 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
325 {
326 .modalias = "ad183x",
327 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
328 .bus_num = 0,
329 .chip_select = 4,
330 .controller_data = &ad1836_spi_chip_info,
331 },
332#endif
333#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
334 {
335 .modalias = "mmc_spi",
336 .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
337 .bus_num = 0,
338 .chip_select = GPIO_PH3 + MAX_CTRL_CS,
339 .controller_data = &mmc_spi_chip_info,
340 .mode = SPI_MODE_3,
341 },
342#endif
343#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
344 {
345 .modalias = "spidev",
346 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
347 .bus_num = 0,
348 .chip_select = 1,
349 .controller_data = &spidev_chip_info,
350 },
351#endif
352};
353
354#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
355/* SPI controller data */
356static struct bfin5xx_spi_master bfin_spi0_info = {
357 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
358 .enable_dma = 1, /* master has the ability to do dma transfer */
359 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
360};
361
362/* SPI (0) */
363static struct resource bfin_spi0_resource[] = {
364 [0] = {
365 .start = SPI0_REGBASE,
366 .end = SPI0_REGBASE + 0xFF,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = CH_SPI,
371 .end = CH_SPI,
372 .flags = IORESOURCE_DMA,
373 },
374 [2] = {
375 .start = IRQ_SPI,
376 .end = IRQ_SPI,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device bfin_spi0_device = {
382 .name = "bfin-spi",
383 .id = 0, /* Bus number */
384 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
385 .resource = bfin_spi0_resource,
386 .dev = {
387 .platform_data = &bfin_spi0_info, /* Passed to driver */
388 },
389};
390#endif /* spi master and devices */
391
392#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
393#ifdef CONFIG_SERIAL_BFIN_UART0
394static struct resource bfin_uart0_resources[] = {
395 {
396 .start = UART0_THR,
397 .end = UART0_GCTL+2,
398 .flags = IORESOURCE_MEM,
399 },
400 {
401 .start = IRQ_UART0_RX,
402 .end = IRQ_UART0_RX+1,
403 .flags = IORESOURCE_IRQ,
404 },
405 {
406 .start = IRQ_UART0_ERROR,
407 .end = IRQ_UART0_ERROR,
408 .flags = IORESOURCE_IRQ,
409 },
410 {
411 .start = CH_UART0_TX,
412 .end = CH_UART0_TX,
413 .flags = IORESOURCE_DMA,
414 },
415 {
416 .start = CH_UART0_RX,
417 .end = CH_UART0_RX,
418 .flags = IORESOURCE_DMA,
419 },
420};
421
422unsigned short bfin_uart0_peripherals[] = {
423 P_UART0_TX, P_UART0_RX, 0
424};
425
426static struct platform_device bfin_uart0_device = {
427 .name = "bfin-uart",
428 .id = 0,
429 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
430 .resource = bfin_uart0_resources,
431 .dev = {
432 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
433 },
434};
435#endif
436#ifdef CONFIG_SERIAL_BFIN_UART1
437static struct resource bfin_uart1_resources[] = {
438 {
439 .start = UART1_THR,
440 .end = UART1_GCTL+2,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .start = IRQ_UART1_RX,
445 .end = IRQ_UART1_RX+1,
446 .flags = IORESOURCE_IRQ,
447 },
448 {
449 .start = IRQ_UART1_ERROR,
450 .end = IRQ_UART1_ERROR,
451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 .start = CH_UART1_TX,
455 .end = CH_UART1_TX,
456 .flags = IORESOURCE_DMA,
457 },
458 {
459 .start = CH_UART1_RX,
460 .end = CH_UART1_RX,
461 .flags = IORESOURCE_DMA,
462 },
463#ifdef CONFIG_BFIN_UART1_CTSRTS
464 { /* CTS pin */
465 .start = GPIO_PF9,
466 .end = GPIO_PF9,
467 .flags = IORESOURCE_IO,
468 },
469 { /* RTS pin */
470 .start = GPIO_PF10,
471 .end = GPIO_PF10,
472 .flags = IORESOURCE_IO,
473 },
474#endif
475};
476
477unsigned short bfin_uart1_peripherals[] = {
478 P_UART1_TX, P_UART1_RX, 0
479};
480
481static struct platform_device bfin_uart1_device = {
482 .name = "bfin-uart",
483 .id = 1,
484 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
485 .resource = bfin_uart1_resources,
486 .dev = {
487 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
488 },
489};
490#endif
491#endif
492
493#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
494#ifdef CONFIG_BFIN_SIR0
495static struct resource bfin_sir0_resources[] = {
496 {
497 .start = 0xFFC00400,
498 .end = 0xFFC004FF,
499 .flags = IORESOURCE_MEM,
500 },
501 {
502 .start = IRQ_UART0_RX,
503 .end = IRQ_UART0_RX+1,
504 .flags = IORESOURCE_IRQ,
505 },
506 {
507 .start = CH_UART0_RX,
508 .end = CH_UART0_RX+1,
509 .flags = IORESOURCE_DMA,
510 },
511};
512
513static struct platform_device bfin_sir0_device = {
514 .name = "bfin_sir",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
517 .resource = bfin_sir0_resources,
518};
519#endif
520#ifdef CONFIG_BFIN_SIR1
521static struct resource bfin_sir1_resources[] = {
522 {
523 .start = 0xFFC02000,
524 .end = 0xFFC020FF,
525 .flags = IORESOURCE_MEM,
526 },
527 {
528 .start = IRQ_UART1_RX,
529 .end = IRQ_UART1_RX+1,
530 .flags = IORESOURCE_IRQ,
531 },
532 {
533 .start = CH_UART1_RX,
534 .end = CH_UART1_RX+1,
535 .flags = IORESOURCE_DMA,
536 },
537};
538
539static struct platform_device bfin_sir1_device = {
540 .name = "bfin_sir",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
543 .resource = bfin_sir1_resources,
544};
545#endif
546#endif
547
548#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
549#include <linux/input/ad7160.h>
550static const struct ad7160_platform_data bfin_ad7160_ts_info = {
551 .sensor_x_res = 854,
552 .sensor_y_res = 480,
553 .pressure = 100,
554 .filter_coef = 3,
555 .coord_pref = AD7160_ORIG_TOP_LEFT,
556 .first_touch_window = 5,
557 .move_window = 3,
558 .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
559 AD7160_EMIT_ABS_MT_PRESSURE |
560 AD7160_TRACKING_ID_ASCENDING,
561 .finger_act_ctrl = 0x64,
562 .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
563 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
564 AD7160_HAPTIC_SLOT_B(60) |
565 AD7160_HAPTIC_SLOT_B_LVL_LOW,
566
567 .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
568 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
569 AD7160_HAPTIC_SLOT_B(80) |
570 AD7160_HAPTIC_SLOT_B_LVL_LOW |
571 AD7160_HAPTIC_SLOT_C(120) |
572 AD7160_HAPTIC_SLOT_C_LVL_HIGH |
573 AD7160_HAPTIC_SLOT_D(30) |
574 AD7160_HAPTIC_SLOT_D_LVL_LOW,
575};
576#endif
577
578#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
579static struct resource bfin_twi0_resource[] = {
580 [0] = {
581 .start = TWI0_REGBASE,
582 .end = TWI0_REGBASE,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 .start = IRQ_TWI,
587 .end = IRQ_TWI,
588 .flags = IORESOURCE_IRQ,
589 },
590};
591
592static struct platform_device i2c_bfin_twi_device = {
593 .name = "i2c-bfin-twi",
594 .id = 0,
595 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
596 .resource = bfin_twi0_resource,
597};
598#endif
599
600static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
601#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
602 {
603 I2C_BOARD_INFO("ad7160", 0x33),
604 .irq = IRQ_PH1,
605 .platform_data = (void *)&bfin_ad7160_ts_info,
606 },
607#endif
608};
609
610#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
611#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
612static struct resource bfin_sport0_uart_resources[] = {
613 {
614 .start = SPORT0_TCR1,
615 .end = SPORT0_MRCS3+4,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .start = IRQ_SPORT0_RX,
620 .end = IRQ_SPORT0_RX+1,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = IRQ_SPORT0_ERROR,
625 .end = IRQ_SPORT0_ERROR,
626 .flags = IORESOURCE_IRQ,
627 },
628};
629
630unsigned short bfin_sport0_peripherals[] = {
631 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
632 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
633};
634
635static struct platform_device bfin_sport0_uart_device = {
636 .name = "bfin-sport-uart",
637 .id = 0,
638 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
639 .resource = bfin_sport0_uart_resources,
640 .dev = {
641 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
642 },
643};
644#endif
645#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
646static struct resource bfin_sport1_uart_resources[] = {
647 {
648 .start = SPORT1_TCR1,
649 .end = SPORT1_MRCS3+4,
650 .flags = IORESOURCE_MEM,
651 },
652 {
653 .start = IRQ_SPORT1_RX,
654 .end = IRQ_SPORT1_RX+1,
655 .flags = IORESOURCE_IRQ,
656 },
657 {
658 .start = IRQ_SPORT1_ERROR,
659 .end = IRQ_SPORT1_ERROR,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664unsigned short bfin_sport1_peripherals[] = {
665 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
666 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
667};
668
669static struct platform_device bfin_sport1_uart_device = {
670 .name = "bfin-sport-uart",
671 .id = 1,
672 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
673 .resource = bfin_sport1_uart_resources,
674 .dev = {
675 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
676 },
677};
678#endif
679#endif
680
681#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
682#include <asm/bfin_rotary.h>
683
684static struct bfin_rotary_platform_data bfin_rotary_data = {
685 /*.rotary_up_key = KEY_UP,*/
686 /*.rotary_down_key = KEY_DOWN,*/
687 .rotary_rel_code = REL_WHEEL,
688 .rotary_button_key = KEY_ENTER,
689 .debounce = 10, /* 0..17 */
690 .mode = ROT_QUAD_ENC | ROT_DEBE,
691};
692
693static struct resource bfin_rotary_resources[] = {
694 {
695 .start = IRQ_CNT,
696 .end = IRQ_CNT,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device bfin_rotary_device = {
702 .name = "bfin-rotary",
703 .id = -1,
704 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
705 .resource = bfin_rotary_resources,
706 .dev = {
707 .platform_data = &bfin_rotary_data,
708 },
709};
710#endif
711
712static const unsigned int cclk_vlev_datasheet[] = {
713 VRPAIR(VLEV_100, 400000000),
714 VRPAIR(VLEV_105, 426000000),
715 VRPAIR(VLEV_110, 500000000),
716 VRPAIR(VLEV_115, 533000000),
717 VRPAIR(VLEV_120, 600000000),
718};
719
720static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
721 .tuple_tab = cclk_vlev_datasheet,
722 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
723 .vr_settling_time = 25 /* us */,
724};
725
726static struct platform_device bfin_dpmc = {
727 .name = "bfin dpmc",
728 .dev = {
729 .platform_data = &bfin_dmpc_vreg_data,
730 },
731};
732
733static struct platform_device *stamp_devices[] __initdata = {
734
735 &bfin_dpmc,
736
737#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
738 &bf5xx_nand_device,
739#endif
740
741#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
742 &rtc_device,
743#endif
744
745#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
746 &musb_device,
747#endif
748
749#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
750 &bfin_mii_bus,
751 &bfin_mac_device,
752#endif
753
754#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
755 &bfin_spi0_device,
756#endif
757
758#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
759#ifdef CONFIG_SERIAL_BFIN_UART0
760 &bfin_uart0_device,
761#endif
762#ifdef CONFIG_SERIAL_BFIN_UART1
763 &bfin_uart1_device,
764#endif
765#endif
766
767#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
768 &bf52x_ra158z_device,
769#endif
770
771#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
772#ifdef CONFIG_BFIN_SIR0
773 &bfin_sir0_device,
774#endif
775#ifdef CONFIG_BFIN_SIR1
776 &bfin_sir1_device,
777#endif
778#endif
779
780#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
781 &i2c_bfin_twi_device,
782#endif
783
784#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
785#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
786 &bfin_sport0_uart_device,
787#endif
788#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
789 &bfin_sport1_uart_device,
790#endif
791#endif
792
793#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
794 &bfin_rotary_device,
795#endif
796
797#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
798 &ad7160eval_flash_device,
799#endif
800
801#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
802 &bfin_i2s,
803#endif
804
805#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
806 &bfin_tdm,
807#endif
808};
809
810static int __init ad7160eval_init(void)
811{
812 printk(KERN_INFO "%s(): registering device resources\n", __func__);
813 i2c_register_board_info(0, bfin_i2c_board_info,
814 ARRAY_SIZE(bfin_i2c_board_info));
815 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
816 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
817 return 0;
818}
819
820arch_initcall(ad7160eval_init);
821
822static struct platform_device *ad7160eval_early_devices[] __initdata = {
823#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
824#ifdef CONFIG_SERIAL_BFIN_UART0
825 &bfin_uart0_device,
826#endif
827#ifdef CONFIG_SERIAL_BFIN_UART1
828 &bfin_uart1_device,
829#endif
830#endif
831
832#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
833#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
834 &bfin_sport0_uart_device,
835#endif
836#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
837 &bfin_sport1_uart_device,
838#endif
839#endif
840};
841
842void __init native_machine_early_platform_add_devices(void)
843{
844 printk(KERN_INFO "register early platform devices\n");
845 early_platform_add_devices(ad7160eval_early_devices,
846 ARRAY_SIZE(ad7160eval_early_devices));
847}
848
849void native_machine_restart(char *cmd)
850{
851 /* workaround reboot hang when booting from SPI */
852 if ((bfin_read_SYSCR() & 0x7) == 0x3)
853 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
854}
855
856void bfin_get_ether_addr(char *addr)
857{
858 /* the MAC is stored in OTP memory page 0xDF */
859 u32 ret;
860 u64 otp_mac;
861 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
862
863 ret = otp_read(0xDF, 0x00, &otp_mac);
864 if (!(ret & 0x1)) {
865 char *otp_mac_p = (char *)&otp_mac;
866 for (ret = 0; ret < 6; ++ret)
867 addr[ret] = otp_mac_p[5 - ret];
868 }
869}
870EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 645ba5c8077b..38037c7e125a 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -342,8 +342,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
342}; 342};
343#endif 343#endif
344 344
345#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 345#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
346 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 346 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 347static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0, 348 .enable_dma = 0,
349 .bits_per_word = 16, 349 .bits_per_word = 16,
@@ -420,13 +420,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
420 }, 420 },
421#endif 421#endif
422 422
423#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 423#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
424 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 424 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
425 { 425 {
426 .modalias = "ad1836", 426 .modalias = "ad183x",
427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
428 .bus_num = 0, 428 .bus_num = 0,
429 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 429 .chip_select = 4,
430 .controller_data = &ad1836_spi_chip_info, 430 .controller_data = &ad1836_spi_chip_info,
431 }, 431 },
432#endif 432#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index c975fe88eba3..6cc64a1e78b9 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -137,8 +137,12 @@ static struct platform_device ezbrd_flash_device = {
137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
138static struct mtd_partition partition_info[] = { 138static struct mtd_partition partition_info[] = {
139 { 139 {
140 .name = "linux kernel(nand)", 140 .name = "bootloader(nand)",
141 .offset = 0, 141 .offset = 0,
142 .size = 0x40000,
143 }, {
144 .name = "linux kernel(nand)",
145 .offset = MTDPART_OFS_APPEND,
142 .size = 4 * 1024 * 1024, 146 .size = 4 * 1024 * 1024,
143 }, 147 },
144 { 148 {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 87b41e994ba3..df82723fb504 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -222,8 +222,12 @@ static struct platform_device ezkit_flash_device = {
222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
223static struct mtd_partition partition_info[] = { 223static struct mtd_partition partition_info[] = {
224 { 224 {
225 .name = "linux kernel(nand)", 225 .name = "bootloader(nand)",
226 .offset = 0, 226 .offset = 0,
227 .size = 0x40000,
228 }, {
229 .name = "linux kernel(nand)",
230 .offset = MTDPART_OFS_APPEND,
227 .size = 4 * 1024 * 1024, 231 .size = 4 * 1024 * 1024,
228 }, 232 },
229 { 233 {
@@ -431,8 +435,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
431}; 435};
432#endif 436#endif
433 437
434#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 438#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
435 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 439 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
436static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 440static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
437 .enable_dma = 0, 441 .enable_dma = 0,
438 .bits_per_word = 16, 442 .bits_per_word = 16,
@@ -547,13 +551,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
547 }, 551 },
548#endif 552#endif
549 553
550#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 554#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
551 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 555 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
552 { 556 {
553 .modalias = "ad1836", 557 .modalias = "ad183x",
554 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 558 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
555 .bus_num = 0, 559 .bus_num = 0,
556 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 560 .chip_select = 4,
557 .controller_data = &ad1836_spi_chip_info, 561 .controller_data = &ad1836_spi_chip_info,
558 }, 562 },
559#endif 563#endif
@@ -883,7 +887,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = {
883}; 887};
884 888
885 /* 889 /*
886 * ADP5520/5501 Multifuction Device Init Data 890 * ADP5520/5501 Multifunction Device Init Data
887 */ 891 */
888 892
889static struct adp5520_platform_data adp5520_pdev_data = { 893static struct adp5520_platform_data adp5520_pdev_data = {
@@ -929,6 +933,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
929 I2C_BOARD_INFO("ssm2602", 0x1b), 933 I2C_BOARD_INFO("ssm2602", 0x1b),
930 }, 934 },
931#endif 935#endif
936#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
937 {
938 I2C_BOARD_INFO("ad5252", 0x2f),
939 },
940#endif
932}; 941};
933 942
934#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 943#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
new file mode 100644
index 000000000000..ae4130e97c01
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -0,0 +1,986 @@
1/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
2 * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Author: Ashish Gupta
4 *
5 * Copyright: 2010 - The Learning Labs Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/usb/musb.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29
30#if defined(CONFIG_TOUCHSCREEN_AD7879) \
31 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
32#include <linux/spi/ad7879.h>
33#define LCD_BACKLIGHT_GPIO 0x40
34/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
35 * LCD Backlight Enable
36 */
37#endif
38
39/*
40 * Name the Board for the /proc/cpuinfo
41 */
42const char bfin_board_name[] = "TLL6527M";
43/*
44 * Driver needs to know address, irq and flag pin.
45 */
46
47#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
48static struct resource musb_resources[] = {
49 [0] = {
50 .start = 0xffc03800,
51 .end = 0xffc03cff,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = { /* general IRQ */
55 .start = IRQ_USB_INT0,
56 .end = IRQ_USB_INT0,
57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
58 },
59 [2] = { /* DMA IRQ */
60 .start = IRQ_USB_DMA,
61 .end = IRQ_USB_DMA,
62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
63 },
64};
65
66static struct musb_hdrc_config musb_config = {
67 .multipoint = 0,
68 .dyn_fifo = 0,
69 .soft_con = 1,
70 .dma = 1,
71 .num_eps = 8,
72 .dma_channels = 8,
73 /*.gpio_vrsel = GPIO_PG13,*/
74 /* Some custom boards need to be active low, just set it to "0"
75 * if it is the case.
76 */
77 .gpio_vrsel_active = 1,
78};
79
80static struct musb_hdrc_platform_data musb_plat = {
81#if defined(CONFIG_USB_MUSB_OTG)
82 .mode = MUSB_OTG,
83#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
84 .mode = MUSB_HOST,
85#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
86 .mode = MUSB_PERIPHERAL,
87#endif
88 .config = &musb_config,
89};
90
91static u64 musb_dmamask = ~(u32)0;
92
93static struct platform_device musb_device = {
94 .name = "musb_hdrc",
95 .id = 0,
96 .dev = {
97 .dma_mask = &musb_dmamask,
98 .coherent_dma_mask = 0xffffffff,
99 .platform_data = &musb_plat,
100 },
101 .num_resources = ARRAY_SIZE(musb_resources),
102 .resource = musb_resources,
103};
104#endif
105
106#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
107#include <asm/bfin-lq035q1.h>
108
109static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
110 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
111 .ppi_mode = USE_RGB565_16_BIT_PPI,
112 .use_bl = 1,
113 .gpio_bl = LCD_BACKLIGHT_GPIO,
114};
115
116static struct resource bfin_lq035q1_resources[] = {
117 {
118 .start = IRQ_PPI_ERROR,
119 .end = IRQ_PPI_ERROR,
120 .flags = IORESOURCE_IRQ,
121 },
122};
123
124static struct platform_device bfin_lq035q1_device = {
125 .name = "bfin-lq035q1",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
128 .resource = bfin_lq035q1_resources,
129 .dev = {
130 .platform_data = &bfin_lq035q1_data,
131 },
132};
133#endif
134
135#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
136static struct mtd_partition tll6527m_partitions[] = {
137 {
138 .name = "bootloader(nor)",
139 .size = 0xA0000,
140 .offset = 0,
141 }, {
142 .name = "linux kernel(nor)",
143 .size = 0xD00000,
144 .offset = MTDPART_OFS_APPEND,
145 }, {
146 .name = "file system(nor)",
147 .size = MTDPART_SIZ_FULL,
148 .offset = MTDPART_OFS_APPEND,
149 }
150};
151
152static struct physmap_flash_data tll6527m_flash_data = {
153 .width = 2,
154 .parts = tll6527m_partitions,
155 .nr_parts = ARRAY_SIZE(tll6527m_partitions),
156};
157
158static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
159
160static struct resource tll6527m_flash_resource[] = {
161 {
162 .name = "cfi_probe",
163 .start = 0x20000000,
164 .end = 0x201fffff,
165 .flags = IORESOURCE_MEM,
166 }, {
167 .start = (unsigned long)tll6527m_flash_gpios,
168 .end = ARRAY_SIZE(tll6527m_flash_gpios),
169 .flags = IORESOURCE_IRQ,
170 }
171};
172
173static struct platform_device tll6527m_flash_device = {
174 .name = "gpio-addr-flash",
175 .id = 0,
176 .dev = {
177 .platform_data = &tll6527m_flash_data,
178 },
179 .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
180 .resource = tll6527m_flash_resource,
181};
182#endif
183
184#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
185/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
187 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
189 */
190#include <linux/gpio-decoder.h>
191#define EXP_GPIO_SPISEL_BASE 0x64
192static unsigned gpio_addr_inputs[] = {
193 GPIO_PG1, GPIO_PH9, GPIO_PH10
194};
195
196static struct gpio_decoder_platfrom_data spi_decoded_cs = {
197 .base = EXP_GPIO_SPISEL_BASE,
198 .input_addrs = gpio_addr_inputs,
199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
200 .default_output = 0,
201/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
202};
203
204static struct platform_device spi_decoded_gpio = {
205 .name = "gpio-decoder",
206 .id = 0,
207 .dev = {
208 .platform_data = &spi_decoded_cs,
209 },
210};
211
212#else
213#define EXP_GPIO_SPISEL_BASE 0x0
214
215#endif
216
217#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
218#include <linux/input/adxl34x.h>
219static const struct adxl34x_platform_data adxl345_info = {
220 .x_axis_offset = 0,
221 .y_axis_offset = 0,
222 .z_axis_offset = 0,
223 .tap_threshold = 0x31,
224 .tap_duration = 0x10,
225 .tap_latency = 0x60,
226 .tap_window = 0xF0,
227 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
228 .act_axis_control = 0xFF,
229 .activity_threshold = 5,
230 .inactivity_threshold = 2,
231 .inactivity_time = 2,
232 .free_fall_threshold = 0x7,
233 .free_fall_time = 0x20,
234 .data_rate = 0x8,
235 .data_range = ADXL_FULL_RES,
236
237 .ev_type = EV_ABS,
238 .ev_code_x = ABS_X, /* EV_REL */
239 .ev_code_y = ABS_Y, /* EV_REL */
240 .ev_code_z = ABS_Z, /* EV_REL */
241
242 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
243
244/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
245 .ev_code_act_inactivity = KEY_A, /* EV_KEY */
246 .use_int2 = 1,
247 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
248 .fifo_mode = ADXL_FIFO_STREAM,
249};
250#endif
251
252#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
253static struct platform_device rtc_device = {
254 .name = "rtc-bfin",
255 .id = -1,
256};
257#endif
258
259#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
260static struct platform_device bfin_mii_bus = {
261 .name = "bfin_mii_bus",
262};
263
264static struct platform_device bfin_mac_device = {
265 .name = "bfin_mac",
266 .dev.platform_data = &bfin_mii_bus,
267};
268#endif
269
270#if defined(CONFIG_MTD_M25P80) \
271 || defined(CONFIG_MTD_M25P80_MODULE)
272static struct mtd_partition bfin_spi_flash_partitions[] = {
273 {
274 .name = "bootloader(spi)",
275 .size = 0x00040000,
276 .offset = 0,
277 .mask_flags = MTD_CAP_ROM
278 }, {
279 .name = "linux kernel(spi)",
280 .size = MTDPART_SIZ_FULL,
281 .offset = MTDPART_OFS_APPEND,
282 }
283};
284
285static struct flash_platform_data bfin_spi_flash_data = {
286 .name = "m25p80",
287 .parts = bfin_spi_flash_partitions,
288 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
289 .type = "m25p16",
290};
291
292/* SPI flash chip (m25p64) */
293static struct bfin5xx_spi_chip spi_flash_chip_info = {
294 .enable_dma = 0, /* use dma transfer with this chip*/
295 .bits_per_word = 8,
296};
297#endif
298
299#if defined(CONFIG_BFIN_SPI_ADC) \
300 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
301/* SPI ADC chip */
302static struct bfin5xx_spi_chip spi_adc_chip_info = {
303 .enable_dma = 0, /* use dma transfer with this chip*/
304/*
305 * tll6527m V1.0 does not support native spi slave selects
306 * hence DMA mode will not be useful since the ADC needs
307 * CS to toggle for each sample and cs_change_per_word
308 * seems to be removed from spi_bfin5xx.c
309 */
310 .bits_per_word = 16,
311};
312#endif
313
314#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
315static struct bfin5xx_spi_chip mmc_spi_chip_info = {
316 .enable_dma = 0,
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_TOUCHSCREEN_AD7879) \
322 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
323static const struct ad7879_platform_data bfin_ad7879_ts_info = {
324 .model = 7879, /* Model = AD7879 */
325 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
326 .pressure_max = 10000,
327 .pressure_min = 0,
328 .first_conversion_delay = 3,
329 /* wait 512us before do a first conversion */
330 .acquisition_time = 1, /* 4us acquisition time per sample */
331 .median = 2, /* do 8 measurements */
332 .averaging = 1,
333 /* take the average of 4 middle samples */
334 .pen_down_acc_interval = 255, /* 9.4 ms */
335 .gpio_export = 1, /* configure AUX as GPIO output*/
336 .gpio_base = LCD_BACKLIGHT_GPIO,
337};
338#endif
339
340#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
341 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
342static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
343 .enable_dma = 0,
344 .bits_per_word = 16,
345};
346#endif
347
348#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
349static struct bfin5xx_spi_chip spidev_chip_info = {
350 .enable_dma = 0,
351 .bits_per_word = 8,
352};
353#endif
354
355#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
356static struct platform_device bfin_i2s = {
357 .name = "bfin-i2s",
358 .id = CONFIG_SND_BF5XX_SPORT_NUM,
359 /* TODO: add platform data here */
360};
361#endif
362
363#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
364static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 8,
367};
368#endif
369
370#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
371static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375
376static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
377 .enable_dma = 0,
378 .bits_per_word = 8,
379};
380
381#include <linux/spi/mcp23s08.h>
382static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
383 .chip[0].is_present = true,
384 .base = 0x30,
385};
386static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
387 .chip[2].is_present = true,
388 .base = 0x38,
389};
390#endif
391
392static struct spi_board_info bfin_spi_board_info[] __initdata = {
393#if defined(CONFIG_MTD_M25P80) \
394 || defined(CONFIG_MTD_M25P80_MODULE)
395 {
396 /* the modalias must be the same as spi device driver name */
397 .modalias = "m25p80", /* Name of spi_driver for this device */
398 .max_speed_hz = 25000000,
399 /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
402 /* Can be connected to TLL6527M GPIO connector */
403 /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
404 .platform_data = &bfin_spi_flash_data,
405 .controller_data = &spi_flash_chip_info,
406 .mode = SPI_MODE_3,
407 },
408#endif
409
410#if defined(CONFIG_BFIN_SPI_ADC)
411 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
412 {
413 .modalias = "bfin_spi_adc",
414 /* Name of spi_driver for this device */
415 .max_speed_hz = 10000000,
416 /* max spi clock (SCK) speed in HZ */
417 .bus_num = 0, /* Framework bus number */
418 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
419 /* Framework chip select. */
420 .platform_data = NULL, /* No spi_driver specific config */
421 .controller_data = &spi_adc_chip_info,
422 .mode = SPI_MODE_0,
423 },
424#endif
425
426#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
427 {
428 .modalias = "mmc_spi",
429/*
430 * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
431 * SPI buffer limitations
432 */
433 .max_speed_hz = 10000000,
434 /* max spi clock (SCK) speed in HZ */
435 .bus_num = 0,
436 .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
437 .controller_data = &mmc_spi_chip_info,
438 .mode = SPI_MODE_0,
439 },
440#endif
441#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
442 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
443 {
444 .modalias = "ad7879",
445 .platform_data = &bfin_ad7879_ts_info,
446 .irq = IRQ_PH14,
447 .max_speed_hz = 5000000,
448 /* max spi clock (SCK) speed in HZ */
449 .bus_num = 0,
450 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
451 .controller_data = &spi_ad7879_chip_info,
452 .mode = SPI_CPHA | SPI_CPOL,
453 },
454#endif
455#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
456 {
457 .modalias = "spidev",
458 .max_speed_hz = 10000000,
459 /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
460 .bus_num = 0,
461 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
462 .mode = SPI_CPHA | SPI_CPOL,
463 .controller_data = &spidev_chip_info,
464 },
465#endif
466#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
467 {
468 .modalias = "bfin-lq035q1-spi",
469 .max_speed_hz = 20000000,
470 .bus_num = 0,
471 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
472 .controller_data = &lq035q1_spi_chip_info,
473 .mode = SPI_CPHA | SPI_CPOL,
474 },
475#endif
476#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
477 {
478 .modalias = "mcp23s08",
479 .platform_data = &bfin_mcp23s08_sys_gpio_info,
480 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
481 .bus_num = 0,
482 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
483 .controller_data = &spi_mcp23s08_sys_chip_info,
484 .mode = SPI_CPHA | SPI_CPOL,
485 },
486 {
487 .modalias = "mcp23s08",
488 .platform_data = &bfin_mcp23s08_usr_gpio_info,
489 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
490 .bus_num = 0,
491 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
492 .controller_data = &spi_mcp23s08_usr_chip_info,
493 .mode = SPI_CPHA | SPI_CPOL,
494 },
495#endif
496};
497
498#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
499/* SPI controller data */
500static struct bfin5xx_spi_master bfin_spi0_info = {
501 .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
502 /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
503 .enable_dma = 1, /* master has the ability to do dma transfer */
504 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
505};
506
507/* SPI (0) */
508static struct resource bfin_spi0_resource[] = {
509 [0] = {
510 .start = SPI0_REGBASE,
511 .end = SPI0_REGBASE + 0xFF,
512 .flags = IORESOURCE_MEM,
513 },
514 [1] = {
515 .start = CH_SPI,
516 .end = CH_SPI,
517 .flags = IORESOURCE_DMA,
518 },
519 [2] = {
520 .start = IRQ_SPI,
521 .end = IRQ_SPI,
522 .flags = IORESOURCE_IRQ,
523 },
524};
525
526static struct platform_device bfin_spi0_device = {
527 .name = "bfin-spi",
528 .id = 0, /* Bus number */
529 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
530 .resource = bfin_spi0_resource,
531 .dev = {
532 .platform_data = &bfin_spi0_info, /* Passed to driver */
533 },
534};
535#endif /* spi master and devices */
536
537#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
538#ifdef CONFIG_SERIAL_BFIN_UART0
539static struct resource bfin_uart0_resources[] = {
540 {
541 .start = UART0_THR,
542 .end = UART0_GCTL+2,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 .start = IRQ_UART0_RX,
547 .end = IRQ_UART0_RX+1,
548 .flags = IORESOURCE_IRQ,
549 },
550 {
551 .start = IRQ_UART0_ERROR,
552 .end = IRQ_UART0_ERROR,
553 .flags = IORESOURCE_IRQ,
554 },
555 {
556 .start = CH_UART0_TX,
557 .end = CH_UART0_TX,
558 .flags = IORESOURCE_DMA,
559 },
560 {
561 .start = CH_UART0_RX,
562 .end = CH_UART0_RX,
563 .flags = IORESOURCE_DMA,
564 },
565};
566
567unsigned short bfin_uart0_peripherals[] = {
568 P_UART0_TX, P_UART0_RX, 0
569};
570
571static struct platform_device bfin_uart0_device = {
572 .name = "bfin-uart",
573 .id = 0,
574 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
575 .resource = bfin_uart0_resources,
576 .dev = {
577 .platform_data = &bfin_uart0_peripherals,
578 /* Passed to driver */
579 },
580};
581#endif
582#ifdef CONFIG_SERIAL_BFIN_UART1
583static struct resource bfin_uart1_resources[] = {
584 {
585 .start = UART1_THR,
586 .end = UART1_GCTL+2,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_UART1_RX,
591 .end = IRQ_UART1_RX+1,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_UART1_ERROR,
596 .end = IRQ_UART1_ERROR,
597 .flags = IORESOURCE_IRQ,
598 },
599 {
600 .start = CH_UART1_TX,
601 .end = CH_UART1_TX,
602 .flags = IORESOURCE_DMA,
603 },
604 {
605 .start = CH_UART1_RX,
606 .end = CH_UART1_RX,
607 .flags = IORESOURCE_DMA,
608 },
609#ifdef CONFIG_BFIN_UART1_CTSRTS
610 { /* CTS pin */
611 .start = GPIO_PF9,
612 .end = GPIO_PF9,
613 .flags = IORESOURCE_IO,
614 },
615 { /* RTS pin */
616 .start = GPIO_PF10,
617 .end = GPIO_PF10,
618 .flags = IORESOURCE_IO,
619 },
620#endif
621};
622
623unsigned short bfin_uart1_peripherals[] = {
624 P_UART1_TX, P_UART1_RX, 0
625};
626
627static struct platform_device bfin_uart1_device = {
628 .name = "bfin-uart",
629 .id = 1,
630 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
631 .resource = bfin_uart1_resources,
632 .dev = {
633 .platform_data = &bfin_uart1_peripherals,
634 /* Passed to driver */
635 },
636};
637#endif
638#endif
639
640#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
641#ifdef CONFIG_BFIN_SIR0
642static struct resource bfin_sir0_resources[] = {
643 {
644 .start = 0xFFC00400,
645 .end = 0xFFC004FF,
646 .flags = IORESOURCE_MEM,
647 },
648 {
649 .start = IRQ_UART0_RX,
650 .end = IRQ_UART0_RX+1,
651 .flags = IORESOURCE_IRQ,
652 },
653 {
654 .start = CH_UART0_RX,
655 .end = CH_UART0_RX+1,
656 .flags = IORESOURCE_DMA,
657 },
658};
659
660static struct platform_device bfin_sir0_device = {
661 .name = "bfin_sir",
662 .id = 0,
663 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
664 .resource = bfin_sir0_resources,
665};
666#endif
667#ifdef CONFIG_BFIN_SIR1
668static struct resource bfin_sir1_resources[] = {
669 {
670 .start = 0xFFC02000,
671 .end = 0xFFC020FF,
672 .flags = IORESOURCE_MEM,
673 },
674 {
675 .start = IRQ_UART1_RX,
676 .end = IRQ_UART1_RX+1,
677 .flags = IORESOURCE_IRQ,
678 },
679 {
680 .start = CH_UART1_RX,
681 .end = CH_UART1_RX+1,
682 .flags = IORESOURCE_DMA,
683 },
684};
685
686static struct platform_device bfin_sir1_device = {
687 .name = "bfin_sir",
688 .id = 1,
689 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
690 .resource = bfin_sir1_resources,
691};
692#endif
693#endif
694
695#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
696static struct resource bfin_twi0_resource[] = {
697 [0] = {
698 .start = TWI0_REGBASE,
699 .end = TWI0_REGBASE,
700 .flags = IORESOURCE_MEM,
701 },
702 [1] = {
703 .start = IRQ_TWI,
704 .end = IRQ_TWI,
705 .flags = IORESOURCE_IRQ,
706 },
707};
708
709static struct platform_device i2c_bfin_twi_device = {
710 .name = "i2c-bfin-twi",
711 .id = 0,
712 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
713 .resource = bfin_twi0_resource,
714};
715#endif
716
717static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
718#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
719 {
720 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
721 },
722#endif
723
724#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
725 {
726 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
727 },
728#endif
729#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
730 || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
731 {
732 I2C_BOARD_INFO("ad7879", 0x2C),
733 .irq = IRQ_PH14,
734 .platform_data = (void *)&bfin_ad7879_ts_info,
735 },
736#endif
737#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
738 {
739 I2C_BOARD_INFO("ssm2602", 0x1b),
740 },
741#endif
742 {
743 I2C_BOARD_INFO("adm1192", 0x2e),
744 },
745
746 {
747 I2C_BOARD_INFO("ltc3576", 0x09),
748 },
749#if defined(CONFIG_INPUT_ADXL34X_I2C) \
750 || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
751 {
752 I2C_BOARD_INFO("adxl34x", 0x53),
753 .irq = IRQ_PH13,
754 .platform_data = (void *)&adxl345_info,
755 },
756#endif
757};
758
759#if defined(CONFIG_SERIAL_BFIN_SPORT) \
760 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
761#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
762static struct resource bfin_sport0_uart_resources[] = {
763 {
764 .start = SPORT0_TCR1,
765 .end = SPORT0_MRCS3+4,
766 .flags = IORESOURCE_MEM,
767 },
768 {
769 .start = IRQ_SPORT0_RX,
770 .end = IRQ_SPORT0_RX+1,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .start = IRQ_SPORT0_ERROR,
775 .end = IRQ_SPORT0_ERROR,
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780unsigned short bfin_sport0_peripherals[] = {
781 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
782 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
783};
784
785static struct platform_device bfin_sport0_uart_device = {
786 .name = "bfin-sport-uart",
787 .id = 0,
788 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
789 .resource = bfin_sport0_uart_resources,
790 .dev = {
791 .platform_data = &bfin_sport0_peripherals,
792 /* Passed to driver */
793 },
794};
795#endif
796#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
797static struct resource bfin_sport1_uart_resources[] = {
798 {
799 .start = SPORT1_TCR1,
800 .end = SPORT1_MRCS3+4,
801 .flags = IORESOURCE_MEM,
802 },
803 {
804 .start = IRQ_SPORT1_RX,
805 .end = IRQ_SPORT1_RX+1,
806 .flags = IORESOURCE_IRQ,
807 },
808 {
809 .start = IRQ_SPORT1_ERROR,
810 .end = IRQ_SPORT1_ERROR,
811 .flags = IORESOURCE_IRQ,
812 },
813};
814
815unsigned short bfin_sport1_peripherals[] = {
816 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
817 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
818};
819
820static struct platform_device bfin_sport1_uart_device = {
821 .name = "bfin-sport-uart",
822 .id = 1,
823 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
824 .resource = bfin_sport1_uart_resources,
825 .dev = {
826 .platform_data = &bfin_sport1_peripherals,
827 /* Passed to driver */
828 },
829};
830#endif
831#endif
832
833static const unsigned int cclk_vlev_datasheet[] = {
834 VRPAIR(VLEV_100, 400000000),
835 VRPAIR(VLEV_105, 426000000),
836 VRPAIR(VLEV_110, 500000000),
837 VRPAIR(VLEV_115, 533000000),
838 VRPAIR(VLEV_120, 600000000),
839};
840
841static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
842 .tuple_tab = cclk_vlev_datasheet,
843 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
844 .vr_settling_time = 25 /* us */,
845};
846
847static struct platform_device bfin_dpmc = {
848 .name = "bfin dpmc",
849 .dev = {
850 .platform_data = &bfin_dmpc_vreg_data,
851 },
852};
853
854static struct platform_device *tll6527m_devices[] __initdata = {
855
856 &bfin_dpmc,
857
858#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
859 &rtc_device,
860#endif
861
862#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
863 &musb_device,
864#endif
865
866#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
867 &bfin_mii_bus,
868 &bfin_mac_device,
869#endif
870
871#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
872 &bfin_spi0_device,
873#endif
874
875#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
876 &bfin_lq035q1_device,
877#endif
878
879#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
880#ifdef CONFIG_SERIAL_BFIN_UART0
881 &bfin_uart0_device,
882#endif
883#ifdef CONFIG_SERIAL_BFIN_UART1
884 &bfin_uart1_device,
885#endif
886#endif
887
888#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
889#ifdef CONFIG_BFIN_SIR0
890 &bfin_sir0_device,
891#endif
892#ifdef CONFIG_BFIN_SIR1
893 &bfin_sir1_device,
894#endif
895#endif
896
897#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
898 &i2c_bfin_twi_device,
899#endif
900
901#if defined(CONFIG_SERIAL_BFIN_SPORT) \
902 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
903#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
904 &bfin_sport0_uart_device,
905#endif
906#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
907 &bfin_sport1_uart_device,
908#endif
909#endif
910
911#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
912 &tll6527m_flash_device,
913#endif
914
915#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
916 &bfin_i2s,
917#endif
918
919#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
920 &spi_decoded_gpio,
921#endif
922};
923
924static int __init tll6527m_init(void)
925{
926 printk(KERN_INFO "%s(): registering device resources\n", __func__);
927 i2c_register_board_info(0, bfin_i2c_board_info,
928 ARRAY_SIZE(bfin_i2c_board_info));
929 platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
930 spi_register_board_info(bfin_spi_board_info,
931 ARRAY_SIZE(bfin_spi_board_info));
932 return 0;
933}
934
935arch_initcall(tll6527m_init);
936
937static struct platform_device *tll6527m_early_devices[] __initdata = {
938#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
939#ifdef CONFIG_SERIAL_BFIN_UART0
940 &bfin_uart0_device,
941#endif
942#ifdef CONFIG_SERIAL_BFIN_UART1
943 &bfin_uart1_device,
944#endif
945#endif
946
947#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
948#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
949 &bfin_sport0_uart_device,
950#endif
951#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
952 &bfin_sport1_uart_device,
953#endif
954#endif
955};
956
957void __init native_machine_early_platform_add_devices(void)
958{
959 printk(KERN_INFO "register early platform devices\n");
960 early_platform_add_devices(tll6527m_early_devices,
961 ARRAY_SIZE(tll6527m_early_devices));
962}
963
964void native_machine_restart(char *cmd)
965{
966 /* workaround reboot hang when booting from SPI */
967 if ((bfin_read_SYSCR() & 0x7) == 0x3)
968 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
969}
970
971void bfin_get_ether_addr(char *addr)
972{
973 /* the MAC is stored in OTP memory page 0xDF */
974 u32 ret;
975 u64 otp_mac;
976 u32 (*otp_read)(u32 page, u32 flags,
977 u64 *page_content) = (void *)0xEF00001A;
978
979 ret = otp_read(0xDF, 0x00, &otp_mac);
980 if (!(ret & 0x1)) {
981 char *otp_mac_p = (char *)&otp_mac;
982 for (ret = 0; ret < 6; ++ret)
983 addr[ret] = otp_mac_p[5 - ret];
984 }
985}
986EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 12f2ad45314e..3048b52bf46a 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -279,14 +279,14 @@
279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) 282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) 283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) 284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) 285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) 286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) 287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) 288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) 289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
@@ -334,14 +334,14 @@
334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) 337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) 338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) 339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) 340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) 341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) 342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) 343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) 344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
@@ -1110,54 +1110,4 @@
1110/* These need to be last due to the cdef/linux inter-dependencies */ 1110/* These need to be last due to the cdef/linux inter-dependencies */
1111#include <asm/irq.h> 1111#include <asm/irq.h>
1112 1112
1113/* Writing to PLL_CTL initiates a PLL relock sequence. */
1114static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1115{
1116 unsigned long flags, iwr0, iwr1;
1117
1118 if (val == bfin_read_PLL_CTL())
1119 return;
1120
1121 local_irq_save_hw(flags);
1122 /* Enable the PLL Wakeup bit in SIC IWR */
1123 iwr0 = bfin_read32(SIC_IWR0);
1124 iwr1 = bfin_read32(SIC_IWR1);
1125 /* Only allow PPL Wakeup) */
1126 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1127 bfin_write32(SIC_IWR1, 0);
1128
1129 bfin_write16(PLL_CTL, val);
1130 SSYNC();
1131 asm("IDLE;");
1132
1133 bfin_write32(SIC_IWR0, iwr0);
1134 bfin_write32(SIC_IWR1, iwr1);
1135 local_irq_restore_hw(flags);
1136}
1137
1138/* Writing to VR_CTL initiates a PLL relock sequence. */
1139static __inline__ void bfin_write_VR_CTL(unsigned int val)
1140{
1141 unsigned long flags, iwr0, iwr1;
1142
1143 if (val == bfin_read_VR_CTL())
1144 return;
1145
1146 local_irq_save_hw(flags);
1147 /* Enable the PLL Wakeup bit in SIC IWR */
1148 iwr0 = bfin_read32(SIC_IWR0);
1149 iwr1 = bfin_read32(SIC_IWR1);
1150 /* Only allow PPL Wakeup) */
1151 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1152 bfin_write32(SIC_IWR1, 0);
1153
1154 bfin_write16(VR_CTL, val);
1155 SSYNC();
1156 asm("IDLE;");
1157
1158 bfin_write32(SIC_IWR0, iwr0);
1159 bfin_write32(SIC_IWR1, iwr1);
1160 local_irq_restore_hw(flags);
1161}
1162
1163#endif /* _CDEF_BF52X_H */ 1113#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 3e000756aacd..09475034c6a1 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -749,51 +749,6 @@
749#define FFE 0x20 /* Force Framing Error On Transmit */ 749#define FFE 0x20 /* Force Framing Error On Transmit */
750 750
751 751
752/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
753/* SPI_CTL Masks */
754#define TIMOD 0x0003 /* Transfer Initiate Mode */
755#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
756#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
757#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
758#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
759#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
760#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
761#define PSSE 0x0010 /* Slave-Select Input Enable */
762#define EMISO 0x0020 /* Enable MISO As Output */
763#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
764#define LSBF 0x0200 /* LSB First */
765#define CPHA 0x0400 /* Clock Phase */
766#define CPOL 0x0800 /* Clock Polarity */
767#define MSTR 0x1000 /* Master/Slave* */
768#define WOM 0x2000 /* Write Open Drain Master */
769#define SPE 0x4000 /* SPI Enable */
770
771/* SPI_FLG Masks */
772#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
773#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
774#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
775#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
776#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
777#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
778#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
779#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
780#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
781#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
782#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
783#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
784#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
785#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
786
787/* SPI_STAT Masks */
788#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
789#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
790#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
791#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
792#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
793#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
794#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
795
796
797/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 752/* **************** GENERAL PURPOSE TIMER MASKS **********************/
798/* TIMER_ENABLE Masks */ 753/* TIMER_ENABLE Masks */
799#define TIMEN0 0x0001 /* Enable Timer 0 */ 754#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
new file mode 100644
index 000000000000..24f1d7c02325
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 hard_local_irq_restore(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 flags = hard_local_irq_save();
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 hard_local_irq_restore(flags);
61}
62
63#endif /* _MACH_PLL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:42:21 -0500