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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/blackfin/mach-bf527
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig10
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile2
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c871
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c53
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c47
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c145
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c1008
-rw-r--r--arch/blackfin/mach-bf527/dma.c2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h8
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h148
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h48
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h1092
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF525.h7
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h7
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h1163
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h1374
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h1551
-rw-r--r--arch/blackfin/mach-bf527/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h266
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h1
23 files changed, 4711 insertions, 3118 deletions
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
index b14c28810a44..1cc2667c10f1 100644
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ b/arch/blackfin/mach-bf527/boards/Kconfig
@@ -24,4 +24,14 @@ config BFIN526_EZBRD
24 help 24 help
25 BF526-EZBRD/EZKIT Lite board support. 25 BF526-EZBRD/EZKIT Lite board support.
26 26
27config BFIN527_AD7160EVAL
28 bool "BF527-AD7160-EVAL"
29 help
30 BF527-AD7160-EVAL board support.
31
32config BFIN527_TLL6527M
33 bool "The Learning Labs TLL6527M"
34 help
35 TLL6527M V1.0 platform support
36
27endchoice 37endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
index 51a5817c4a90..1d67da9f05ac 100644
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o 6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o 7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o 8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
9obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
10obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
new file mode 100644
index 000000000000..ccab4c689dc3
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -0,0 +1,871 @@
1/*
2 * Copyright 2004-20010 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/i2c.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <linux/leds.h>
21#include <linux/input.h>
22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },
51 [2] = { /* DMA IRQ */
52 .start = IRQ_USB_DMA,
53 .end = IRQ_USB_DMA,
54 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
55 },
56};
57
58static struct musb_hdrc_config musb_config = {
59 .multipoint = 0,
60 .dyn_fifo = 0,
61 .soft_con = 1,
62 .dma = 1,
63 .num_eps = 8,
64 .dma_channels = 8,
65 .gpio_vrsel = GPIO_PG13,
66 /* Some custom boards need to be active low, just set it to "0"
67 * if it is the case.
68 */
69 .gpio_vrsel_active = 1,
70 .clkin = 24, /* musb CLKIN in MHZ */
71};
72
73static struct musb_hdrc_platform_data musb_plat = {
74#if defined(CONFIG_USB_MUSB_OTG)
75 .mode = MUSB_OTG,
76#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
77 .mode = MUSB_HOST,
78#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
79 .mode = MUSB_PERIPHERAL,
80#endif
81 .config = &musb_config,
82};
83
84static u64 musb_dmamask = ~(u32)0;
85
86static struct platform_device musb_device = {
87 .name = "musb-blackfin",
88 .id = 0,
89 .dev = {
90 .dma_mask = &musb_dmamask,
91 .coherent_dma_mask = 0xffffffff,
92 .platform_data = &musb_plat,
93 },
94 .num_resources = ARRAY_SIZE(musb_resources),
95 .resource = musb_resources,
96};
97#endif
98
99#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
100static struct resource bf52x_ra158z_resources[] = {
101 {
102 .start = IRQ_PPI_ERROR,
103 .end = IRQ_PPI_ERROR,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct platform_device bf52x_ra158z_device = {
109 .name = "bfin-ra158z",
110 .id = -1,
111 .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
112 .resource = bf52x_ra158z_resources,
113};
114#endif
115
116#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
117static struct mtd_partition ad7160eval_partitions[] = {
118 {
119 .name = "bootloader(nor)",
120 .size = 0x40000,
121 .offset = 0,
122 }, {
123 .name = "linux kernel(nor)",
124 .size = 0x1C0000,
125 .offset = MTDPART_OFS_APPEND,
126 }, {
127 .name = "file system(nor)",
128 .size = MTDPART_SIZ_FULL,
129 .offset = MTDPART_OFS_APPEND,
130 }
131};
132
133static struct physmap_flash_data ad7160eval_flash_data = {
134 .width = 2,
135 .parts = ad7160eval_partitions,
136 .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
137};
138
139static struct resource ad7160eval_flash_resource = {
140 .start = 0x20000000,
141 .end = 0x203fffff,
142 .flags = IORESOURCE_MEM,
143};
144
145static struct platform_device ad7160eval_flash_device = {
146 .name = "physmap-flash",
147 .id = 0,
148 .dev = {
149 .platform_data = &ad7160eval_flash_data,
150 },
151 .num_resources = 1,
152 .resource = &ad7160eval_flash_resource,
153};
154#endif
155
156#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
157static struct mtd_partition partition_info[] = {
158 {
159 .name = "linux kernel(nand)",
160 .offset = 0,
161 .size = 4 * 1024 * 1024,
162 },
163 {
164 .name = "file system(nand)",
165 .offset = MTDPART_OFS_APPEND,
166 .size = MTDPART_SIZ_FULL,
167 },
168};
169
170static struct bf5xx_nand_platform bf5xx_nand_platform = {
171 .data_width = NFC_NWIDTH_8,
172 .partitions = partition_info,
173 .nr_partitions = ARRAY_SIZE(partition_info),
174 .rd_dly = 3,
175 .wr_dly = 3,
176};
177
178static struct resource bf5xx_nand_resources[] = {
179 {
180 .start = NFC_CTL,
181 .end = NFC_DATA_RD + 2,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .start = CH_NFC,
186 .end = CH_NFC,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device bf5xx_nand_device = {
192 .name = "bf5xx-nand",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
195 .resource = bf5xx_nand_resources,
196 .dev = {
197 .platform_data = &bf5xx_nand_platform,
198 },
199};
200#endif
201
202#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
203static struct platform_device rtc_device = {
204 .name = "rtc-bfin",
205 .id = -1,
206};
207#endif
208
209#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
210#include <linux/bfin_mac.h>
211static const unsigned short bfin_mac_peripherals[] = P_RMII0;
212
213static struct bfin_phydev_platform_data bfin_phydev_data[] = {
214 {
215 .addr = 1,
216 .irq = IRQ_MAC_PHYINT,
217 },
218};
219
220static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
221 .phydev_number = 1,
222 .phydev_data = bfin_phydev_data,
223 .phy_mode = PHY_INTERFACE_MODE_RMII,
224 .mac_peripherals = bfin_mac_peripherals,
225};
226
227static struct platform_device bfin_mii_bus = {
228 .name = "bfin_mii_bus",
229 .dev = {
230 .platform_data = &bfin_mii_bus_data,
231 }
232};
233
234static struct platform_device bfin_mac_device = {
235 .name = "bfin_mac",
236 .dev = {
237 .platform_data = &bfin_mii_bus,
238 }
239};
240#endif
241
242
243#if defined(CONFIG_MTD_M25P80) \
244 || defined(CONFIG_MTD_M25P80_MODULE)
245static struct mtd_partition bfin_spi_flash_partitions[] = {
246 {
247 .name = "bootloader(spi)",
248 .size = 0x00040000,
249 .offset = 0,
250 .mask_flags = MTD_CAP_ROM
251 }, {
252 .name = "linux kernel(spi)",
253 .size = MTDPART_SIZ_FULL,
254 .offset = MTDPART_OFS_APPEND,
255 }
256};
257
258static struct flash_platform_data bfin_spi_flash_data = {
259 .name = "m25p80",
260 .parts = bfin_spi_flash_partitions,
261 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
262 .type = "m25p16",
263};
264
265/* SPI flash chip (m25p64) */
266static struct bfin5xx_spi_chip spi_flash_chip_info = {
267 .enable_dma = 0, /* use dma transfer with this chip*/
268 .bits_per_word = 8,
269};
270#endif
271
272#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
273 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
274static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
275 .enable_dma = 0,
276 .bits_per_word = 16,
277};
278#endif
279
280#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
281static struct bfin5xx_spi_chip mmc_spi_chip_info = {
282 .enable_dma = 0,
283 .bits_per_word = 8,
284};
285#endif
286
287#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
288static struct bfin5xx_spi_chip spidev_chip_info = {
289 .enable_dma = 0,
290 .bits_per_word = 8,
291};
292#endif
293
294#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
295static struct platform_device bfin_i2s = {
296 .name = "bfin-i2s",
297 .id = CONFIG_SND_BF5XX_SPORT_NUM,
298 /* TODO: add platform data here */
299};
300#endif
301
302#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
303static struct platform_device bfin_tdm = {
304 .name = "bfin-tdm",
305 .id = CONFIG_SND_BF5XX_SPORT_NUM,
306 /* TODO: add platform data here */
307};
308#endif
309
310static struct spi_board_info bfin_spi_board_info[] __initdata = {
311#if defined(CONFIG_MTD_M25P80) \
312 || defined(CONFIG_MTD_M25P80_MODULE)
313 {
314 /* the modalias must be the same as spi device driver name */
315 .modalias = "m25p80", /* Name of spi_driver for this device */
316 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
317 .bus_num = 0, /* Framework bus number */
318 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
319 .platform_data = &bfin_spi_flash_data,
320 .controller_data = &spi_flash_chip_info,
321 .mode = SPI_MODE_3,
322 },
323#endif
324#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
325 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
326 {
327 .modalias = "ad183x",
328 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
329 .bus_num = 0,
330 .chip_select = 4,
331 .controller_data = &ad1836_spi_chip_info,
332 },
333#endif
334#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
335 {
336 .modalias = "mmc_spi",
337 .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
338 .bus_num = 0,
339 .chip_select = GPIO_PH3 + MAX_CTRL_CS,
340 .controller_data = &mmc_spi_chip_info,
341 .mode = SPI_MODE_3,
342 },
343#endif
344#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
345 {
346 .modalias = "spidev",
347 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
348 .bus_num = 0,
349 .chip_select = 1,
350 .controller_data = &spidev_chip_info,
351 },
352#endif
353};
354
355#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
356/* SPI controller data */
357static struct bfin5xx_spi_master bfin_spi0_info = {
358 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
359 .enable_dma = 1, /* master has the ability to do dma transfer */
360 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
361};
362
363/* SPI (0) */
364static struct resource bfin_spi0_resource[] = {
365 [0] = {
366 .start = SPI0_REGBASE,
367 .end = SPI0_REGBASE + 0xFF,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = CH_SPI,
372 .end = CH_SPI,
373 .flags = IORESOURCE_DMA,
374 },
375 [2] = {
376 .start = IRQ_SPI,
377 .end = IRQ_SPI,
378 .flags = IORESOURCE_IRQ,
379 },
380};
381
382static struct platform_device bfin_spi0_device = {
383 .name = "bfin-spi",
384 .id = 0, /* Bus number */
385 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
386 .resource = bfin_spi0_resource,
387 .dev = {
388 .platform_data = &bfin_spi0_info, /* Passed to driver */
389 },
390};
391#endif /* spi master and devices */
392
393#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
394#ifdef CONFIG_SERIAL_BFIN_UART0
395static struct resource bfin_uart0_resources[] = {
396 {
397 .start = UART0_THR,
398 .end = UART0_GCTL+2,
399 .flags = IORESOURCE_MEM,
400 },
401 {
402 .start = IRQ_UART0_RX,
403 .end = IRQ_UART0_RX+1,
404 .flags = IORESOURCE_IRQ,
405 },
406 {
407 .start = IRQ_UART0_ERROR,
408 .end = IRQ_UART0_ERROR,
409 .flags = IORESOURCE_IRQ,
410 },
411 {
412 .start = CH_UART0_TX,
413 .end = CH_UART0_TX,
414 .flags = IORESOURCE_DMA,
415 },
416 {
417 .start = CH_UART0_RX,
418 .end = CH_UART0_RX,
419 .flags = IORESOURCE_DMA,
420 },
421};
422
423static unsigned short bfin_uart0_peripherals[] = {
424 P_UART0_TX, P_UART0_RX, 0
425};
426
427static struct platform_device bfin_uart0_device = {
428 .name = "bfin-uart",
429 .id = 0,
430 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
431 .resource = bfin_uart0_resources,
432 .dev = {
433 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
434 },
435};
436#endif
437#ifdef CONFIG_SERIAL_BFIN_UART1
438static struct resource bfin_uart1_resources[] = {
439 {
440 .start = UART1_THR,
441 .end = UART1_GCTL+2,
442 .flags = IORESOURCE_MEM,
443 },
444 {
445 .start = IRQ_UART1_RX,
446 .end = IRQ_UART1_RX+1,
447 .flags = IORESOURCE_IRQ,
448 },
449 {
450 .start = IRQ_UART1_ERROR,
451 .end = IRQ_UART1_ERROR,
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = CH_UART1_TX,
456 .end = CH_UART1_TX,
457 .flags = IORESOURCE_DMA,
458 },
459 {
460 .start = CH_UART1_RX,
461 .end = CH_UART1_RX,
462 .flags = IORESOURCE_DMA,
463 },
464#ifdef CONFIG_BFIN_UART1_CTSRTS
465 { /* CTS pin */
466 .start = GPIO_PF9,
467 .end = GPIO_PF9,
468 .flags = IORESOURCE_IO,
469 },
470 { /* RTS pin */
471 .start = GPIO_PF10,
472 .end = GPIO_PF10,
473 .flags = IORESOURCE_IO,
474 },
475#endif
476};
477
478static unsigned short bfin_uart1_peripherals[] = {
479 P_UART1_TX, P_UART1_RX, 0
480};
481
482static struct platform_device bfin_uart1_device = {
483 .name = "bfin-uart",
484 .id = 1,
485 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
486 .resource = bfin_uart1_resources,
487 .dev = {
488 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
489 },
490};
491#endif
492#endif
493
494#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
495#ifdef CONFIG_BFIN_SIR0
496static struct resource bfin_sir0_resources[] = {
497 {
498 .start = 0xFFC00400,
499 .end = 0xFFC004FF,
500 .flags = IORESOURCE_MEM,
501 },
502 {
503 .start = IRQ_UART0_RX,
504 .end = IRQ_UART0_RX+1,
505 .flags = IORESOURCE_IRQ,
506 },
507 {
508 .start = CH_UART0_RX,
509 .end = CH_UART0_RX+1,
510 .flags = IORESOURCE_DMA,
511 },
512};
513
514static struct platform_device bfin_sir0_device = {
515 .name = "bfin_sir",
516 .id = 0,
517 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
518 .resource = bfin_sir0_resources,
519};
520#endif
521#ifdef CONFIG_BFIN_SIR1
522static struct resource bfin_sir1_resources[] = {
523 {
524 .start = 0xFFC02000,
525 .end = 0xFFC020FF,
526 .flags = IORESOURCE_MEM,
527 },
528 {
529 .start = IRQ_UART1_RX,
530 .end = IRQ_UART1_RX+1,
531 .flags = IORESOURCE_IRQ,
532 },
533 {
534 .start = CH_UART1_RX,
535 .end = CH_UART1_RX+1,
536 .flags = IORESOURCE_DMA,
537 },
538};
539
540static struct platform_device bfin_sir1_device = {
541 .name = "bfin_sir",
542 .id = 1,
543 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
544 .resource = bfin_sir1_resources,
545};
546#endif
547#endif
548
549#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
550#include <linux/input/ad7160.h>
551static const struct ad7160_platform_data bfin_ad7160_ts_info = {
552 .sensor_x_res = 854,
553 .sensor_y_res = 480,
554 .pressure = 100,
555 .filter_coef = 3,
556 .coord_pref = AD7160_ORIG_TOP_LEFT,
557 .first_touch_window = 5,
558 .move_window = 3,
559 .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
560 AD7160_EMIT_ABS_MT_PRESSURE |
561 AD7160_TRACKING_ID_ASCENDING,
562 .finger_act_ctrl = 0x64,
563 .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
564 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
565 AD7160_HAPTIC_SLOT_B(60) |
566 AD7160_HAPTIC_SLOT_B_LVL_LOW,
567
568 .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
569 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
570 AD7160_HAPTIC_SLOT_B(80) |
571 AD7160_HAPTIC_SLOT_B_LVL_LOW |
572 AD7160_HAPTIC_SLOT_C(120) |
573 AD7160_HAPTIC_SLOT_C_LVL_HIGH |
574 AD7160_HAPTIC_SLOT_D(30) |
575 AD7160_HAPTIC_SLOT_D_LVL_LOW,
576};
577#endif
578
579#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
580static struct resource bfin_twi0_resource[] = {
581 [0] = {
582 .start = TWI0_REGBASE,
583 .end = TWI0_REGBASE,
584 .flags = IORESOURCE_MEM,
585 },
586 [1] = {
587 .start = IRQ_TWI,
588 .end = IRQ_TWI,
589 .flags = IORESOURCE_IRQ,
590 },
591};
592
593static struct platform_device i2c_bfin_twi_device = {
594 .name = "i2c-bfin-twi",
595 .id = 0,
596 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
597 .resource = bfin_twi0_resource,
598};
599#endif
600
601static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
602#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
603 {
604 I2C_BOARD_INFO("ad7160", 0x33),
605 .irq = IRQ_PH1,
606 .platform_data = (void *)&bfin_ad7160_ts_info,
607 },
608#endif
609};
610
611#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
612#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
613static struct resource bfin_sport0_uart_resources[] = {
614 {
615 .start = SPORT0_TCR1,
616 .end = SPORT0_MRCS3+4,
617 .flags = IORESOURCE_MEM,
618 },
619 {
620 .start = IRQ_SPORT0_RX,
621 .end = IRQ_SPORT0_RX+1,
622 .flags = IORESOURCE_IRQ,
623 },
624 {
625 .start = IRQ_SPORT0_ERROR,
626 .end = IRQ_SPORT0_ERROR,
627 .flags = IORESOURCE_IRQ,
628 },
629};
630
631static unsigned short bfin_sport0_peripherals[] = {
632 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
633 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
634};
635
636static struct platform_device bfin_sport0_uart_device = {
637 .name = "bfin-sport-uart",
638 .id = 0,
639 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
640 .resource = bfin_sport0_uart_resources,
641 .dev = {
642 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
643 },
644};
645#endif
646#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
647static struct resource bfin_sport1_uart_resources[] = {
648 {
649 .start = SPORT1_TCR1,
650 .end = SPORT1_MRCS3+4,
651 .flags = IORESOURCE_MEM,
652 },
653 {
654 .start = IRQ_SPORT1_RX,
655 .end = IRQ_SPORT1_RX+1,
656 .flags = IORESOURCE_IRQ,
657 },
658 {
659 .start = IRQ_SPORT1_ERROR,
660 .end = IRQ_SPORT1_ERROR,
661 .flags = IORESOURCE_IRQ,
662 },
663};
664
665static unsigned short bfin_sport1_peripherals[] = {
666 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
667 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
668};
669
670static struct platform_device bfin_sport1_uart_device = {
671 .name = "bfin-sport-uart",
672 .id = 1,
673 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
674 .resource = bfin_sport1_uart_resources,
675 .dev = {
676 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
677 },
678};
679#endif
680#endif
681
682#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
683#include <asm/bfin_rotary.h>
684
685static struct bfin_rotary_platform_data bfin_rotary_data = {
686 /*.rotary_up_key = KEY_UP,*/
687 /*.rotary_down_key = KEY_DOWN,*/
688 .rotary_rel_code = REL_WHEEL,
689 .rotary_button_key = KEY_ENTER,
690 .debounce = 10, /* 0..17 */
691 .mode = ROT_QUAD_ENC | ROT_DEBE,
692};
693
694static struct resource bfin_rotary_resources[] = {
695 {
696 .start = IRQ_CNT,
697 .end = IRQ_CNT,
698 .flags = IORESOURCE_IRQ,
699 },
700};
701
702static struct platform_device bfin_rotary_device = {
703 .name = "bfin-rotary",
704 .id = -1,
705 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
706 .resource = bfin_rotary_resources,
707 .dev = {
708 .platform_data = &bfin_rotary_data,
709 },
710};
711#endif
712
713static const unsigned int cclk_vlev_datasheet[] = {
714 VRPAIR(VLEV_100, 400000000),
715 VRPAIR(VLEV_105, 426000000),
716 VRPAIR(VLEV_110, 500000000),
717 VRPAIR(VLEV_115, 533000000),
718 VRPAIR(VLEV_120, 600000000),
719};
720
721static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
722 .tuple_tab = cclk_vlev_datasheet,
723 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
724 .vr_settling_time = 25 /* us */,
725};
726
727static struct platform_device bfin_dpmc = {
728 .name = "bfin dpmc",
729 .dev = {
730 .platform_data = &bfin_dmpc_vreg_data,
731 },
732};
733
734static struct platform_device *stamp_devices[] __initdata = {
735
736 &bfin_dpmc,
737
738#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
739 &bf5xx_nand_device,
740#endif
741
742#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
743 &rtc_device,
744#endif
745
746#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
747 &musb_device,
748#endif
749
750#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
751 &bfin_mii_bus,
752 &bfin_mac_device,
753#endif
754
755#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
756 &bfin_spi0_device,
757#endif
758
759#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
760#ifdef CONFIG_SERIAL_BFIN_UART0
761 &bfin_uart0_device,
762#endif
763#ifdef CONFIG_SERIAL_BFIN_UART1
764 &bfin_uart1_device,
765#endif
766#endif
767
768#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
769 &bf52x_ra158z_device,
770#endif
771
772#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
773#ifdef CONFIG_BFIN_SIR0
774 &bfin_sir0_device,
775#endif
776#ifdef CONFIG_BFIN_SIR1
777 &bfin_sir1_device,
778#endif
779#endif
780
781#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
782 &i2c_bfin_twi_device,
783#endif
784
785#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
786#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
787 &bfin_sport0_uart_device,
788#endif
789#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
790 &bfin_sport1_uart_device,
791#endif
792#endif
793
794#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
795 &bfin_rotary_device,
796#endif
797
798#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
799 &ad7160eval_flash_device,
800#endif
801
802#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
803 &bfin_i2s,
804#endif
805
806#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
807 &bfin_tdm,
808#endif
809};
810
811static int __init ad7160eval_init(void)
812{
813 printk(KERN_INFO "%s(): registering device resources\n", __func__);
814 i2c_register_board_info(0, bfin_i2c_board_info,
815 ARRAY_SIZE(bfin_i2c_board_info));
816 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
817 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
818 return 0;
819}
820
821arch_initcall(ad7160eval_init);
822
823static struct platform_device *ad7160eval_early_devices[] __initdata = {
824#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
825#ifdef CONFIG_SERIAL_BFIN_UART0
826 &bfin_uart0_device,
827#endif
828#ifdef CONFIG_SERIAL_BFIN_UART1
829 &bfin_uart1_device,
830#endif
831#endif
832
833#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
834#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
835 &bfin_sport0_uart_device,
836#endif
837#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
838 &bfin_sport1_uart_device,
839#endif
840#endif
841};
842
843void __init native_machine_early_platform_add_devices(void)
844{
845 printk(KERN_INFO "register early platform devices\n");
846 early_platform_add_devices(ad7160eval_early_devices,
847 ARRAY_SIZE(ad7160eval_early_devices));
848}
849
850void native_machine_restart(char *cmd)
851{
852 /* workaround reboot hang when booting from SPI */
853 if ((bfin_read_SYSCR() & 0x7) == 0x3)
854 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
855}
856
857void bfin_get_ether_addr(char *addr)
858{
859 /* the MAC is stored in OTP memory page 0xDF */
860 u32 ret;
861 u64 otp_mac;
862 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
863
864 ret = otp_read(0xDF, 0x00, &otp_mac);
865 if (!(ret & 0x1)) {
866 char *otp_mac_p = (char *)&otp_mac;
867 for (ret = 0; ret < 6; ++ret)
868 addr[ret] = otp_mac_p[5 - ret];
869 }
870}
871EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 645ba5c8077b..c9d6dc88f0e6 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -82,11 +82,13 @@ static struct resource musb_resources[] = {
82 .start = IRQ_USB_INT0, 82 .start = IRQ_USB_INT0,
83 .end = IRQ_USB_INT0, 83 .end = IRQ_USB_INT0,
84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
85 .name = "mc"
85 }, 86 },
86 [2] = { /* DMA IRQ */ 87 [2] = { /* DMA IRQ */
87 .start = IRQ_USB_DMA, 88 .start = IRQ_USB_DMA,
88 .end = IRQ_USB_DMA, 89 .end = IRQ_USB_DMA,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 90 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
91 .name = "dma"
90 }, 92 },
91}; 93};
92 94
@@ -102,6 +104,7 @@ static struct musb_hdrc_config musb_config = {
102 * if it is the case. 104 * if it is the case.
103 */ 105 */
104 .gpio_vrsel_active = 1, 106 .gpio_vrsel_active = 1,
107 .clkin = 24, /* musb CLKIN in MHZ */
105}; 108};
106 109
107static struct musb_hdrc_platform_data musb_plat = { 110static struct musb_hdrc_platform_data musb_plat = {
@@ -118,7 +121,7 @@ static struct musb_hdrc_platform_data musb_plat = {
118static u64 musb_dmamask = ~(u32)0; 121static u64 musb_dmamask = ~(u32)0;
119 122
120static struct platform_device musb_device = { 123static struct platform_device musb_device = {
121 .name = "musb_hdrc", 124 .name = "musb-blackfin",
122 .id = 0, 125 .id = 0,
123 .dev = { 126 .dev = {
124 .dma_mask = &musb_dmamask, 127 .dma_mask = &musb_dmamask,
@@ -273,13 +276,35 @@ static struct platform_device dm9000_device = {
273#endif 276#endif
274 277
275#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 278#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
279#include <linux/bfin_mac.h>
280static const unsigned short bfin_mac_peripherals[] = P_RMII0;
281
282static struct bfin_phydev_platform_data bfin_phydev_data[] = {
283 {
284 .addr = 1,
285 .irq = IRQ_MAC_PHYINT,
286 },
287};
288
289static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
290 .phydev_number = 1,
291 .phydev_data = bfin_phydev_data,
292 .phy_mode = PHY_INTERFACE_MODE_RMII,
293 .mac_peripherals = bfin_mac_peripherals,
294};
295
276static struct platform_device bfin_mii_bus = { 296static struct platform_device bfin_mii_bus = {
277 .name = "bfin_mii_bus", 297 .name = "bfin_mii_bus",
298 .dev = {
299 .platform_data = &bfin_mii_bus_data,
300 }
278}; 301};
279 302
280static struct platform_device bfin_mac_device = { 303static struct platform_device bfin_mac_device = {
281 .name = "bfin_mac", 304 .name = "bfin_mac",
282 .dev.platform_data = &bfin_mii_bus, 305 .dev = {
306 .platform_data = &bfin_mii_bus,
307 }
283}; 308};
284#endif 309#endif
285 310
@@ -342,8 +367,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
342}; 367};
343#endif 368#endif
344 369
345#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 370#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
346 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 371 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 372static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0, 373 .enable_dma = 0,
349 .bits_per_word = 16, 374 .bits_per_word = 16,
@@ -420,13 +445,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
420 }, 445 },
421#endif 446#endif
422 447
423#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 448#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
424 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 449 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
425 { 450 {
426 .modalias = "ad1836", 451 .modalias = "ad183x",
427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 452 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
428 .bus_num = 0, 453 .bus_num = 0,
429 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 454 .chip_select = 4,
430 .controller_data = &ad1836_spi_chip_info, 455 .controller_data = &ad1836_spi_chip_info,
431 }, 456 },
432#endif 457#endif
@@ -590,7 +615,7 @@ static struct resource bfin_uart0_resources[] = {
590 }, 615 },
591}; 616};
592 617
593unsigned short bfin_uart0_peripherals[] = { 618static unsigned short bfin_uart0_peripherals[] = {
594 P_UART0_TX, P_UART0_RX, 0 619 P_UART0_TX, P_UART0_RX, 0
595}; 620};
596 621
@@ -645,7 +670,7 @@ static struct resource bfin_uart1_resources[] = {
645#endif 670#endif
646}; 671};
647 672
648unsigned short bfin_uart1_peripherals[] = { 673static unsigned short bfin_uart1_peripherals[] = {
649 P_UART1_TX, P_UART1_RX, 0 674 P_UART1_TX, P_UART1_RX, 0
650}; 675};
651 676
@@ -777,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = {
777 }, 802 },
778}; 803};
779 804
780unsigned short bfin_sport0_peripherals[] = { 805static unsigned short bfin_sport0_peripherals[] = {
781 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 806 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
782 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 807 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
783}; 808};
784 809
785static struct platform_device bfin_sport0_uart_device = { 810static struct platform_device bfin_sport0_uart_device = {
@@ -811,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = {
811 }, 836 },
812}; 837};
813 838
814unsigned short bfin_sport1_peripherals[] = { 839static unsigned short bfin_sport1_peripherals[] = {
815 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 840 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
816 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 841 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
817}; 842};
818 843
819static struct platform_device bfin_sport1_uart_device = { 844static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index c975fe88eba3..b7101aa6e3aa 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -46,11 +46,13 @@ static struct resource musb_resources[] = {
46 .start = IRQ_USB_INT0, 46 .start = IRQ_USB_INT0,
47 .end = IRQ_USB_INT0, 47 .end = IRQ_USB_INT0,
48 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 48 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
49 .name = "mc"
49 }, 50 },
50 [2] = { /* DMA IRQ */ 51 [2] = { /* DMA IRQ */
51 .start = IRQ_USB_DMA, 52 .start = IRQ_USB_DMA,
52 .end = IRQ_USB_DMA, 53 .end = IRQ_USB_DMA,
53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 54 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
55 .name = "dma"
54 }, 56 },
55}; 57};
56 58
@@ -66,6 +68,7 @@ static struct musb_hdrc_config musb_config = {
66 * if it is the case. 68 * if it is the case.
67 */ 69 */
68 .gpio_vrsel_active = 1, 70 .gpio_vrsel_active = 1,
71 .clkin = 24, /* musb CLKIN in MHZ */
69}; 72};
70 73
71static struct musb_hdrc_platform_data musb_plat = { 74static struct musb_hdrc_platform_data musb_plat = {
@@ -82,7 +85,7 @@ static struct musb_hdrc_platform_data musb_plat = {
82static u64 musb_dmamask = ~(u32)0; 85static u64 musb_dmamask = ~(u32)0;
83 86
84static struct platform_device musb_device = { 87static struct platform_device musb_device = {
85 .name = "musb_hdrc", 88 .name = "musb-blackfin",
86 .id = 0, 89 .id = 0,
87 .dev = { 90 .dev = {
88 .dma_mask = &musb_dmamask, 91 .dma_mask = &musb_dmamask,
@@ -137,8 +140,12 @@ static struct platform_device ezbrd_flash_device = {
137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 140#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
138static struct mtd_partition partition_info[] = { 141static struct mtd_partition partition_info[] = {
139 { 142 {
140 .name = "linux kernel(nand)", 143 .name = "bootloader(nand)",
141 .offset = 0, 144 .offset = 0,
145 .size = 0x40000,
146 }, {
147 .name = "linux kernel(nand)",
148 .offset = MTDPART_OFS_APPEND,
142 .size = 4 * 1024 * 1024, 149 .size = 4 * 1024 * 1024,
143 }, 150 },
144 { 151 {
@@ -189,13 +196,35 @@ static struct platform_device rtc_device = {
189 196
190 197
191#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 198#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
199#include <linux/bfin_mac.h>
200static const unsigned short bfin_mac_peripherals[] = P_RMII0;
201
202static struct bfin_phydev_platform_data bfin_phydev_data[] = {
203 {
204 .addr = 1,
205 .irq = IRQ_MAC_PHYINT,
206 },
207};
208
209static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
210 .phydev_number = 1,
211 .phydev_data = bfin_phydev_data,
212 .phy_mode = PHY_INTERFACE_MODE_RMII,
213 .mac_peripherals = bfin_mac_peripherals,
214};
215
192static struct platform_device bfin_mii_bus = { 216static struct platform_device bfin_mii_bus = {
193 .name = "bfin_mii_bus", 217 .name = "bfin_mii_bus",
218 .dev = {
219 .platform_data = &bfin_mii_bus_data,
220 }
194}; 221};
195 222
196static struct platform_device bfin_mac_device = { 223static struct platform_device bfin_mac_device = {
197 .name = "bfin_mac", 224 .name = "bfin_mac",
198 .dev.platform_data = &bfin_mii_bus, 225 .dev = {
226 .platform_data = &bfin_mii_bus,
227 }
199}; 228};
200#endif 229#endif
201 230
@@ -471,7 +500,7 @@ static struct resource bfin_uart0_resources[] = {
471 }, 500 },
472}; 501};
473 502
474unsigned short bfin_uart0_peripherals[] = { 503static unsigned short bfin_uart0_peripherals[] = {
475 P_UART0_TX, P_UART0_RX, 0 504 P_UART0_TX, P_UART0_RX, 0
476}; 505};
477 506
@@ -526,7 +555,7 @@ static struct resource bfin_uart1_resources[] = {
526#endif 555#endif
527}; 556};
528 557
529unsigned short bfin_uart1_peripherals[] = { 558static unsigned short bfin_uart1_peripherals[] = {
530 P_UART1_TX, P_UART1_RX, 0 559 P_UART1_TX, P_UART1_RX, 0
531}; 560};
532 561
@@ -653,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = {
653 }, 682 },
654}; 683};
655 684
656unsigned short bfin_sport0_peripherals[] = { 685static unsigned short bfin_sport0_peripherals[] = {
657 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 686 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
658 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 687 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
659}; 688};
660 689
661static struct platform_device bfin_sport0_uart_device = { 690static struct platform_device bfin_sport0_uart_device = {
@@ -687,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = {
687 }, 716 },
688}; 717};
689 718
690unsigned short bfin_sport1_peripherals[] = { 719static unsigned short bfin_sport1_peripherals[] = {
691 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 720 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
692 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 721 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
693}; 722};
694 723
695static struct platform_device bfin_sport1_uart_device = { 724static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 87b41e994ba3..e67ac7720668 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -26,6 +26,7 @@
26#include <asm/portmux.h> 26#include <asm/portmux.h>
27#include <asm/dpmc.h> 27#include <asm/dpmc.h>
28#include <linux/spi/ad7877.h> 28#include <linux/spi/ad7877.h>
29#include <asm/bfin_sport.h>
29 30
30/* 31/*
31 * Name the Board for the /proc/cpuinfo 32 * Name the Board for the /proc/cpuinfo
@@ -86,11 +87,13 @@ static struct resource musb_resources[] = {
86 .start = IRQ_USB_INT0, 87 .start = IRQ_USB_INT0,
87 .end = IRQ_USB_INT0, 88 .end = IRQ_USB_INT0,
88 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
90 .name = "mc"
89 }, 91 },
90 [2] = { /* DMA IRQ */ 92 [2] = { /* DMA IRQ */
91 .start = IRQ_USB_DMA, 93 .start = IRQ_USB_DMA,
92 .end = IRQ_USB_DMA, 94 .end = IRQ_USB_DMA,
93 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 95 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
96 .name = "dma"
94 }, 97 },
95}; 98};
96 99
@@ -106,6 +109,7 @@ static struct musb_hdrc_config musb_config = {
106 * if it is the case. 109 * if it is the case.
107 */ 110 */
108 .gpio_vrsel_active = 1, 111 .gpio_vrsel_active = 1,
112 .clkin = 24, /* musb CLKIN in MHZ */
109}; 113};
110 114
111static struct musb_hdrc_platform_data musb_plat = { 115static struct musb_hdrc_platform_data musb_plat = {
@@ -122,7 +126,7 @@ static struct musb_hdrc_platform_data musb_plat = {
122static u64 musb_dmamask = ~(u32)0; 126static u64 musb_dmamask = ~(u32)0;
123 127
124static struct platform_device musb_device = { 128static struct platform_device musb_device = {
125 .name = "musb_hdrc", 129 .name = "musb-blackfin",
126 .id = 0, 130 .id = 0,
127 .dev = { 131 .dev = {
128 .dma_mask = &musb_dmamask, 132 .dma_mask = &musb_dmamask,
@@ -222,8 +226,12 @@ static struct platform_device ezkit_flash_device = {
222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 226#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
223static struct mtd_partition partition_info[] = { 227static struct mtd_partition partition_info[] = {
224 { 228 {
225 .name = "linux kernel(nand)", 229 .name = "bootloader(nand)",
226 .offset = 0, 230 .offset = 0,
231 .size = 0x40000,
232 }, {
233 .name = "linux kernel(nand)",
234 .offset = MTDPART_OFS_APPEND,
227 .size = 4 * 1024 * 1024, 235 .size = 4 * 1024 * 1024,
228 }, 236 },
229 { 237 {
@@ -362,13 +370,35 @@ static struct platform_device dm9000_device = {
362#endif 370#endif
363 371
364#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 372#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
373#include <linux/bfin_mac.h>
374static const unsigned short bfin_mac_peripherals[] = P_RMII0;
375
376static struct bfin_phydev_platform_data bfin_phydev_data[] = {
377 {
378 .addr = 1,
379 .irq = IRQ_MAC_PHYINT,
380 },
381};
382
383static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
384 .phydev_number = 1,
385 .phydev_data = bfin_phydev_data,
386 .phy_mode = PHY_INTERFACE_MODE_RMII,
387 .mac_peripherals = bfin_mac_peripherals,
388};
389
365static struct platform_device bfin_mii_bus = { 390static struct platform_device bfin_mii_bus = {
366 .name = "bfin_mii_bus", 391 .name = "bfin_mii_bus",
392 .dev = {
393 .platform_data = &bfin_mii_bus_data,
394 }
367}; 395};
368 396
369static struct platform_device bfin_mac_device = { 397static struct platform_device bfin_mac_device = {
370 .name = "bfin_mac", 398 .name = "bfin_mac",
371 .dev.platform_data = &bfin_mii_bus, 399 .dev = {
400 .platform_data = &bfin_mii_bus,
401 }
372}; 402};
373#endif 403#endif
374 404
@@ -431,8 +461,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
431}; 461};
432#endif 462#endif
433 463
434#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 464#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
435 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 465 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
436static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 466static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
437 .enable_dma = 0, 467 .enable_dma = 0,
438 .bits_per_word = 16, 468 .bits_per_word = 16,
@@ -497,11 +527,69 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
497}; 527};
498#endif 528#endif
499 529
530#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
531 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
532
533static const u16 bfin_snd_pin[][7] = {
534 {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
535 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
536 {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
537 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
538};
539
540static struct bfin_snd_platform_data bfin_snd_data[] = {
541 {
542 .pin_req = &bfin_snd_pin[0][0],
543 },
544 {
545 .pin_req = &bfin_snd_pin[1][0],
546 },
547};
548
549#define BFIN_SND_RES(x) \
550 [x] = { \
551 { \
552 .start = SPORT##x##_TCR1, \
553 .end = SPORT##x##_TCR1, \
554 .flags = IORESOURCE_MEM \
555 }, \
556 { \
557 .start = CH_SPORT##x##_RX, \
558 .end = CH_SPORT##x##_RX, \
559 .flags = IORESOURCE_DMA, \
560 }, \
561 { \
562 .start = CH_SPORT##x##_TX, \
563 .end = CH_SPORT##x##_TX, \
564 .flags = IORESOURCE_DMA, \
565 }, \
566 { \
567 .start = IRQ_SPORT##x##_ERROR, \
568 .end = IRQ_SPORT##x##_ERROR, \
569 .flags = IORESOURCE_IRQ, \
570 } \
571 }
572
573static struct resource bfin_snd_resources[][4] = {
574 BFIN_SND_RES(0),
575 BFIN_SND_RES(1),
576};
577
578static struct platform_device bfin_pcm = {
579 .name = "bfin-pcm-audio",
580 .id = -1,
581};
582#endif
583
500#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 584#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
501static struct platform_device bfin_i2s = { 585static struct platform_device bfin_i2s = {
502 .name = "bfin-i2s", 586 .name = "bfin-i2s",
503 .id = CONFIG_SND_BF5XX_SPORT_NUM, 587 .id = CONFIG_SND_BF5XX_SPORT_NUM,
504 /* TODO: add platform data here */ 588 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
589 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
590 .dev = {
591 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
592 },
505}; 593};
506#endif 594#endif
507 595
@@ -509,7 +597,11 @@ static struct platform_device bfin_i2s = {
509static struct platform_device bfin_tdm = { 597static struct platform_device bfin_tdm = {
510 .name = "bfin-tdm", 598 .name = "bfin-tdm",
511 .id = CONFIG_SND_BF5XX_SPORT_NUM, 599 .id = CONFIG_SND_BF5XX_SPORT_NUM,
512 /* TODO: add platform data here */ 600 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
601 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
602 .dev = {
603 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
604 },
513}; 605};
514#endif 606#endif
515 607
@@ -547,14 +639,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
547 }, 639 },
548#endif 640#endif
549 641
550#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 642#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
551 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 643 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
552 { 644 {
553 .modalias = "ad1836", 645 .modalias = "ad183x",
554 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 646 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
555 .bus_num = 0, 647 .bus_num = 0,
556 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 648 .chip_select = 4,
649 .platform_data = "ad1836",
557 .controller_data = &ad1836_spi_chip_info, 650 .controller_data = &ad1836_spi_chip_info,
651 .mode = SPI_MODE_3,
558 }, 652 },
559#endif 653#endif
560#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 654#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -680,7 +774,7 @@ static struct resource bfin_uart0_resources[] = {
680 }, 774 },
681}; 775};
682 776
683unsigned short bfin_uart0_peripherals[] = { 777static unsigned short bfin_uart0_peripherals[] = {
684 P_UART0_TX, P_UART0_RX, 0 778 P_UART0_TX, P_UART0_RX, 0
685}; 779};
686 780
@@ -735,7 +829,7 @@ static struct resource bfin_uart1_resources[] = {
735#endif 829#endif
736}; 830};
737 831
738unsigned short bfin_uart1_peripherals[] = { 832static unsigned short bfin_uart1_peripherals[] = {
739 P_UART1_TX, P_UART1_RX, 0 833 P_UART1_TX, P_UART1_RX, 0
740}; 834};
741 835
@@ -883,7 +977,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = {
883}; 977};
884 978
885 /* 979 /*
886 * ADP5520/5501 Multifuction Device Init Data 980 * ADP5520/5501 Multifunction Device Init Data
887 */ 981 */
888 982
889static struct adp5520_platform_data adp5520_pdev_data = { 983static struct adp5520_platform_data adp5520_pdev_data = {
@@ -929,6 +1023,16 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
929 I2C_BOARD_INFO("ssm2602", 0x1b), 1023 I2C_BOARD_INFO("ssm2602", 0x1b),
930 }, 1024 },
931#endif 1025#endif
1026#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
1027 {
1028 I2C_BOARD_INFO("ad5252", 0x2f),
1029 },
1030#endif
1031#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
1032 {
1033 I2C_BOARD_INFO("adau1373", 0x1A),
1034 },
1035#endif
932}; 1036};
933 1037
934#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 1038#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -951,9 +1055,9 @@ static struct resource bfin_sport0_uart_resources[] = {
951 }, 1055 },
952}; 1056};
953 1057
954unsigned short bfin_sport0_peripherals[] = { 1058static unsigned short bfin_sport0_peripherals[] = {
955 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 1059 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
956 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 1060 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
957}; 1061};
958 1062
959static struct platform_device bfin_sport0_uart_device = { 1063static struct platform_device bfin_sport0_uart_device = {
@@ -985,9 +1089,9 @@ static struct resource bfin_sport1_uart_resources[] = {
985 }, 1089 },
986}; 1090};
987 1091
988unsigned short bfin_sport1_peripherals[] = { 1092static unsigned short bfin_sport1_peripherals[] = {
989 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 1093 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
990 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 1094 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
991}; 1095};
992 1096
993static struct platform_device bfin_sport1_uart_device = { 1097static struct platform_device bfin_sport1_uart_device = {
@@ -1172,6 +1276,11 @@ static struct platform_device *stamp_devices[] __initdata = {
1172 &ezkit_flash_device, 1276 &ezkit_flash_device,
1173#endif 1277#endif
1174 1278
1279#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1280 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1281 &bfin_pcm,
1282#endif
1283
1175#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1284#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1176 &bfin_i2s, 1285 &bfin_i2s,
1177#endif 1286#endif
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
new file mode 100644
index 000000000000..18d303dd5627
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -0,0 +1,1008 @@
1/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
2 * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Author: Ashish Gupta
4 *
5 * Copyright: 2010 - The Learning Labs Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/usb/musb.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29
30#if defined(CONFIG_TOUCHSCREEN_AD7879) \
31 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
32#include <linux/spi/ad7879.h>
33#define LCD_BACKLIGHT_GPIO 0x40
34/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
35 * LCD Backlight Enable
36 */
37#endif
38
39/*
40 * Name the Board for the /proc/cpuinfo
41 */
42const char bfin_board_name[] = "TLL6527M";
43/*
44 * Driver needs to know address, irq and flag pin.
45 */
46
47#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
48static struct resource musb_resources[] = {
49 [0] = {
50 .start = 0xffc03800,
51 .end = 0xffc03cff,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = { /* general IRQ */
55 .start = IRQ_USB_INT0,
56 .end = IRQ_USB_INT0,
57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
58 },
59 [2] = { /* DMA IRQ */
60 .start = IRQ_USB_DMA,
61 .end = IRQ_USB_DMA,
62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
63 },
64};
65
66static struct musb_hdrc_config musb_config = {
67 .multipoint = 0,
68 .dyn_fifo = 0,
69 .soft_con = 1,
70 .dma = 1,
71 .num_eps = 8,
72 .dma_channels = 8,
73 /*.gpio_vrsel = GPIO_PG13,*/
74 /* Some custom boards need to be active low, just set it to "0"
75 * if it is the case.
76 */
77 .gpio_vrsel_active = 1,
78};
79
80static struct musb_hdrc_platform_data musb_plat = {
81#if defined(CONFIG_USB_MUSB_OTG)
82 .mode = MUSB_OTG,
83#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
84 .mode = MUSB_HOST,
85#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
86 .mode = MUSB_PERIPHERAL,
87#endif
88 .config = &musb_config,
89};
90
91static u64 musb_dmamask = ~(u32)0;
92
93static struct platform_device musb_device = {
94 .name = "musb-blackfin",
95 .id = 0,
96 .dev = {
97 .dma_mask = &musb_dmamask,
98 .coherent_dma_mask = 0xffffffff,
99 .platform_data = &musb_plat,
100 },
101 .num_resources = ARRAY_SIZE(musb_resources),
102 .resource = musb_resources,
103};
104#endif
105
106#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
107#include <asm/bfin-lq035q1.h>
108
109static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
110 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
111 .ppi_mode = USE_RGB565_16_BIT_PPI,
112 .use_bl = 1,
113 .gpio_bl = LCD_BACKLIGHT_GPIO,
114};
115
116static struct resource bfin_lq035q1_resources[] = {
117 {
118 .start = IRQ_PPI_ERROR,
119 .end = IRQ_PPI_ERROR,
120 .flags = IORESOURCE_IRQ,
121 },
122};
123
124static struct platform_device bfin_lq035q1_device = {
125 .name = "bfin-lq035q1",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
128 .resource = bfin_lq035q1_resources,
129 .dev = {
130 .platform_data = &bfin_lq035q1_data,
131 },
132};
133#endif
134
135#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
136static struct mtd_partition tll6527m_partitions[] = {
137 {
138 .name = "bootloader(nor)",
139 .size = 0xA0000,
140 .offset = 0,
141 }, {
142 .name = "linux kernel(nor)",
143 .size = 0xD00000,
144 .offset = MTDPART_OFS_APPEND,
145 }, {
146 .name = "file system(nor)",
147 .size = MTDPART_SIZ_FULL,
148 .offset = MTDPART_OFS_APPEND,
149 }
150};
151
152static struct physmap_flash_data tll6527m_flash_data = {
153 .width = 2,
154 .parts = tll6527m_partitions,
155 .nr_parts = ARRAY_SIZE(tll6527m_partitions),
156};
157
158static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
159
160static struct resource tll6527m_flash_resource[] = {
161 {
162 .name = "cfi_probe",
163 .start = 0x20000000,
164 .end = 0x201fffff,
165 .flags = IORESOURCE_MEM,
166 }, {
167 .start = (unsigned long)tll6527m_flash_gpios,
168 .end = ARRAY_SIZE(tll6527m_flash_gpios),
169 .flags = IORESOURCE_IRQ,
170 }
171};
172
173static struct platform_device tll6527m_flash_device = {
174 .name = "gpio-addr-flash",
175 .id = 0,
176 .dev = {
177 .platform_data = &tll6527m_flash_data,
178 },
179 .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
180 .resource = tll6527m_flash_resource,
181};
182#endif
183
184#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
185/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
187 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
189 */
190#include <linux/gpio-decoder.h>
191#define EXP_GPIO_SPISEL_BASE 0x64
192static unsigned gpio_addr_inputs[] = {
193 GPIO_PG1, GPIO_PH9, GPIO_PH10
194};
195
196static struct gpio_decoder_platform_data spi_decoded_cs = {
197 .base = EXP_GPIO_SPISEL_BASE,
198 .input_addrs = gpio_addr_inputs,
199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
200 .default_output = 0,
201/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
202};
203
204static struct platform_device spi_decoded_gpio = {
205 .name = "gpio-decoder",
206 .id = 0,
207 .dev = {
208 .platform_data = &spi_decoded_cs,
209 },
210};
211
212#else
213#define EXP_GPIO_SPISEL_BASE 0x0
214
215#endif
216
217#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
218#include <linux/input/adxl34x.h>
219static const struct adxl34x_platform_data adxl345_info = {
220 .x_axis_offset = 0,
221 .y_axis_offset = 0,
222 .z_axis_offset = 0,
223 .tap_threshold = 0x31,
224 .tap_duration = 0x10,
225 .tap_latency = 0x60,
226 .tap_window = 0xF0,
227 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
228 .act_axis_control = 0xFF,
229 .activity_threshold = 5,
230 .inactivity_threshold = 2,
231 .inactivity_time = 2,
232 .free_fall_threshold = 0x7,
233 .free_fall_time = 0x20,
234 .data_rate = 0x8,
235 .data_range = ADXL_FULL_RES,
236
237 .ev_type = EV_ABS,
238 .ev_code_x = ABS_X, /* EV_REL */
239 .ev_code_y = ABS_Y, /* EV_REL */
240 .ev_code_z = ABS_Z, /* EV_REL */
241
242 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
243
244/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
245 .ev_code_act_inactivity = KEY_A, /* EV_KEY */
246 .use_int2 = 1,
247 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
248 .fifo_mode = ADXL_FIFO_STREAM,
249};
250#endif
251
252#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
253static struct platform_device rtc_device = {
254 .name = "rtc-bfin",
255 .id = -1,
256};
257#endif
258
259#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
260#include <linux/bfin_mac.h>
261static const unsigned short bfin_mac_peripherals[] = P_RMII0;
262
263static struct bfin_phydev_platform_data bfin_phydev_data[] = {
264 {
265 .addr = 1,
266 .irq = IRQ_MAC_PHYINT,
267 },
268};
269
270static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
271 .phydev_number = 1,
272 .phydev_data = bfin_phydev_data,
273 .phy_mode = PHY_INTERFACE_MODE_RMII,
274 .mac_peripherals = bfin_mac_peripherals,
275};
276
277static struct platform_device bfin_mii_bus = {
278 .name = "bfin_mii_bus",
279 .dev = {
280 .platform_data = &bfin_mii_bus_data,
281 }
282};
283
284static struct platform_device bfin_mac_device = {
285 .name = "bfin_mac",
286 .dev = {
287 .platform_data = &bfin_mii_bus,
288 }
289};
290#endif
291
292#if defined(CONFIG_MTD_M25P80) \
293 || defined(CONFIG_MTD_M25P80_MODULE)
294static struct mtd_partition bfin_spi_flash_partitions[] = {
295 {
296 .name = "bootloader(spi)",
297 .size = 0x00040000,
298 .offset = 0,
299 .mask_flags = MTD_CAP_ROM
300 }, {
301 .name = "linux kernel(spi)",
302 .size = MTDPART_SIZ_FULL,
303 .offset = MTDPART_OFS_APPEND,
304 }
305};
306
307static struct flash_platform_data bfin_spi_flash_data = {
308 .name = "m25p80",
309 .parts = bfin_spi_flash_partitions,
310 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
311 .type = "m25p16",
312};
313
314/* SPI flash chip (m25p64) */
315static struct bfin5xx_spi_chip spi_flash_chip_info = {
316 .enable_dma = 0, /* use dma transfer with this chip*/
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_BFIN_SPI_ADC) \
322 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
323/* SPI ADC chip */
324static struct bfin5xx_spi_chip spi_adc_chip_info = {
325 .enable_dma = 0, /* use dma transfer with this chip*/
326/*
327 * tll6527m V1.0 does not support native spi slave selects
328 * hence DMA mode will not be useful since the ADC needs
329 * CS to toggle for each sample and cs_change_per_word
330 * seems to be removed from spi_bfin5xx.c
331 */
332 .bits_per_word = 16,
333};
334#endif
335
336#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
337static struct bfin5xx_spi_chip mmc_spi_chip_info = {
338 .enable_dma = 0,
339 .bits_per_word = 8,
340};
341#endif
342
343#if defined(CONFIG_TOUCHSCREEN_AD7879) \
344 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
345static const struct ad7879_platform_data bfin_ad7879_ts_info = {
346 .model = 7879, /* Model = AD7879 */
347 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
348 .pressure_max = 10000,
349 .pressure_min = 0,
350 .first_conversion_delay = 3,
351 /* wait 512us before do a first conversion */
352 .acquisition_time = 1, /* 4us acquisition time per sample */
353 .median = 2, /* do 8 measurements */
354 .averaging = 1,
355 /* take the average of 4 middle samples */
356 .pen_down_acc_interval = 255, /* 9.4 ms */
357 .gpio_export = 1, /* configure AUX as GPIO output*/
358 .gpio_base = LCD_BACKLIGHT_GPIO,
359};
360#endif
361
362#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
363 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
364static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
371static struct bfin5xx_spi_chip spidev_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375#endif
376
377#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
378static struct platform_device bfin_i2s = {
379 .name = "bfin-i2s",
380 .id = CONFIG_SND_BF5XX_SPORT_NUM,
381 /* TODO: add platform data here */
382};
383#endif
384
385#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
386static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 8,
389};
390#endif
391
392#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
393static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
394 .enable_dma = 0,
395 .bits_per_word = 8,
396};
397
398static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
399 .enable_dma = 0,
400 .bits_per_word = 8,
401};
402
403#include <linux/spi/mcp23s08.h>
404static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
405 .chip[0].is_present = true,
406 .base = 0x30,
407};
408static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
409 .chip[2].is_present = true,
410 .base = 0x38,
411};
412#endif
413
414static struct spi_board_info bfin_spi_board_info[] __initdata = {
415#if defined(CONFIG_MTD_M25P80) \
416 || defined(CONFIG_MTD_M25P80_MODULE)
417 {
418 /* the modalias must be the same as spi device driver name */
419 .modalias = "m25p80", /* Name of spi_driver for this device */
420 .max_speed_hz = 25000000,
421 /* max spi clock (SCK) speed in HZ */
422 .bus_num = 0, /* Framework bus number */
423 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
424 /* Can be connected to TLL6527M GPIO connector */
425 /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
426 .platform_data = &bfin_spi_flash_data,
427 .controller_data = &spi_flash_chip_info,
428 .mode = SPI_MODE_3,
429 },
430#endif
431
432#if defined(CONFIG_BFIN_SPI_ADC)
433 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
434 {
435 .modalias = "bfin_spi_adc",
436 /* Name of spi_driver for this device */
437 .max_speed_hz = 10000000,
438 /* max spi clock (SCK) speed in HZ */
439 .bus_num = 0, /* Framework bus number */
440 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
441 /* Framework chip select. */
442 .platform_data = NULL, /* No spi_driver specific config */
443 .controller_data = &spi_adc_chip_info,
444 .mode = SPI_MODE_0,
445 },
446#endif
447
448#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
449 {
450 .modalias = "mmc_spi",
451/*
452 * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
453 * SPI buffer limitations
454 */
455 .max_speed_hz = 10000000,
456 /* max spi clock (SCK) speed in HZ */
457 .bus_num = 0,
458 .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
459 .controller_data = &mmc_spi_chip_info,
460 .mode = SPI_MODE_0,
461 },
462#endif
463#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
464 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
465 {
466 .modalias = "ad7879",
467 .platform_data = &bfin_ad7879_ts_info,
468 .irq = IRQ_PH14,
469 .max_speed_hz = 5000000,
470 /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
473 .controller_data = &spi_ad7879_chip_info,
474 .mode = SPI_CPHA | SPI_CPOL,
475 },
476#endif
477#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
478 {
479 .modalias = "spidev",
480 .max_speed_hz = 10000000,
481 /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
482 .bus_num = 0,
483 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
484 .mode = SPI_CPHA | SPI_CPOL,
485 .controller_data = &spidev_chip_info,
486 },
487#endif
488#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
489 {
490 .modalias = "bfin-lq035q1-spi",
491 .max_speed_hz = 20000000,
492 .bus_num = 0,
493 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
494 .controller_data = &lq035q1_spi_chip_info,
495 .mode = SPI_CPHA | SPI_CPOL,
496 },
497#endif
498#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
499 {
500 .modalias = "mcp23s08",
501 .platform_data = &bfin_mcp23s08_sys_gpio_info,
502 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
503 .bus_num = 0,
504 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
505 .controller_data = &spi_mcp23s08_sys_chip_info,
506 .mode = SPI_CPHA | SPI_CPOL,
507 },
508 {
509 .modalias = "mcp23s08",
510 .platform_data = &bfin_mcp23s08_usr_gpio_info,
511 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
512 .bus_num = 0,
513 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
514 .controller_data = &spi_mcp23s08_usr_chip_info,
515 .mode = SPI_CPHA | SPI_CPOL,
516 },
517#endif
518};
519
520#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
521/* SPI controller data */
522static struct bfin5xx_spi_master bfin_spi0_info = {
523 .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
524 /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
525 .enable_dma = 1, /* master has the ability to do dma transfer */
526 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
527};
528
529/* SPI (0) */
530static struct resource bfin_spi0_resource[] = {
531 [0] = {
532 .start = SPI0_REGBASE,
533 .end = SPI0_REGBASE + 0xFF,
534 .flags = IORESOURCE_MEM,
535 },
536 [1] = {
537 .start = CH_SPI,
538 .end = CH_SPI,
539 .flags = IORESOURCE_DMA,
540 },
541 [2] = {
542 .start = IRQ_SPI,
543 .end = IRQ_SPI,
544 .flags = IORESOURCE_IRQ,
545 },
546};
547
548static struct platform_device bfin_spi0_device = {
549 .name = "bfin-spi",
550 .id = 0, /* Bus number */
551 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
552 .resource = bfin_spi0_resource,
553 .dev = {
554 .platform_data = &bfin_spi0_info, /* Passed to driver */
555 },
556};
557#endif /* spi master and devices */
558
559#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
560#ifdef CONFIG_SERIAL_BFIN_UART0
561static struct resource bfin_uart0_resources[] = {
562 {
563 .start = UART0_THR,
564 .end = UART0_GCTL+2,
565 .flags = IORESOURCE_MEM,
566 },
567 {
568 .start = IRQ_UART0_RX,
569 .end = IRQ_UART0_RX+1,
570 .flags = IORESOURCE_IRQ,
571 },
572 {
573 .start = IRQ_UART0_ERROR,
574 .end = IRQ_UART0_ERROR,
575 .flags = IORESOURCE_IRQ,
576 },
577 {
578 .start = CH_UART0_TX,
579 .end = CH_UART0_TX,
580 .flags = IORESOURCE_DMA,
581 },
582 {
583 .start = CH_UART0_RX,
584 .end = CH_UART0_RX,
585 .flags = IORESOURCE_DMA,
586 },
587};
588
589static unsigned short bfin_uart0_peripherals[] = {
590 P_UART0_TX, P_UART0_RX, 0
591};
592
593static struct platform_device bfin_uart0_device = {
594 .name = "bfin-uart",
595 .id = 0,
596 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
597 .resource = bfin_uart0_resources,
598 .dev = {
599 .platform_data = &bfin_uart0_peripherals,
600 /* Passed to driver */
601 },
602};
603#endif
604#ifdef CONFIG_SERIAL_BFIN_UART1
605static struct resource bfin_uart1_resources[] = {
606 {
607 .start = UART1_THR,
608 .end = UART1_GCTL+2,
609 .flags = IORESOURCE_MEM,
610 },
611 {
612 .start = IRQ_UART1_RX,
613 .end = IRQ_UART1_RX+1,
614 .flags = IORESOURCE_IRQ,
615 },
616 {
617 .start = IRQ_UART1_ERROR,
618 .end = IRQ_UART1_ERROR,
619 .flags = IORESOURCE_IRQ,
620 },
621 {
622 .start = CH_UART1_TX,
623 .end = CH_UART1_TX,
624 .flags = IORESOURCE_DMA,
625 },
626 {
627 .start = CH_UART1_RX,
628 .end = CH_UART1_RX,
629 .flags = IORESOURCE_DMA,
630 },
631#ifdef CONFIG_BFIN_UART1_CTSRTS
632 { /* CTS pin */
633 .start = GPIO_PF9,
634 .end = GPIO_PF9,
635 .flags = IORESOURCE_IO,
636 },
637 { /* RTS pin */
638 .start = GPIO_PF10,
639 .end = GPIO_PF10,
640 .flags = IORESOURCE_IO,
641 },
642#endif
643};
644
645static unsigned short bfin_uart1_peripherals[] = {
646 P_UART1_TX, P_UART1_RX, 0
647};
648
649static struct platform_device bfin_uart1_device = {
650 .name = "bfin-uart",
651 .id = 1,
652 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
653 .resource = bfin_uart1_resources,
654 .dev = {
655 .platform_data = &bfin_uart1_peripherals,
656 /* Passed to driver */
657 },
658};
659#endif
660#endif
661
662#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
663#ifdef CONFIG_BFIN_SIR0
664static struct resource bfin_sir0_resources[] = {
665 {
666 .start = 0xFFC00400,
667 .end = 0xFFC004FF,
668 .flags = IORESOURCE_MEM,
669 },
670 {
671 .start = IRQ_UART0_RX,
672 .end = IRQ_UART0_RX+1,
673 .flags = IORESOURCE_IRQ,
674 },
675 {
676 .start = CH_UART0_RX,
677 .end = CH_UART0_RX+1,
678 .flags = IORESOURCE_DMA,
679 },
680};
681
682static struct platform_device bfin_sir0_device = {
683 .name = "bfin_sir",
684 .id = 0,
685 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
686 .resource = bfin_sir0_resources,
687};
688#endif
689#ifdef CONFIG_BFIN_SIR1
690static struct resource bfin_sir1_resources[] = {
691 {
692 .start = 0xFFC02000,
693 .end = 0xFFC020FF,
694 .flags = IORESOURCE_MEM,
695 },
696 {
697 .start = IRQ_UART1_RX,
698 .end = IRQ_UART1_RX+1,
699 .flags = IORESOURCE_IRQ,
700 },
701 {
702 .start = CH_UART1_RX,
703 .end = CH_UART1_RX+1,
704 .flags = IORESOURCE_DMA,
705 },
706};
707
708static struct platform_device bfin_sir1_device = {
709 .name = "bfin_sir",
710 .id = 1,
711 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
712 .resource = bfin_sir1_resources,
713};
714#endif
715#endif
716
717#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
718static struct resource bfin_twi0_resource[] = {
719 [0] = {
720 .start = TWI0_REGBASE,
721 .end = TWI0_REGBASE,
722 .flags = IORESOURCE_MEM,
723 },
724 [1] = {
725 .start = IRQ_TWI,
726 .end = IRQ_TWI,
727 .flags = IORESOURCE_IRQ,
728 },
729};
730
731static struct platform_device i2c_bfin_twi_device = {
732 .name = "i2c-bfin-twi",
733 .id = 0,
734 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
735 .resource = bfin_twi0_resource,
736};
737#endif
738
739static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
740#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
741 {
742 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
743 },
744#endif
745
746#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
747 {
748 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
749 },
750#endif
751#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
752 || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
753 {
754 I2C_BOARD_INFO("ad7879", 0x2C),
755 .irq = IRQ_PH14,
756 .platform_data = (void *)&bfin_ad7879_ts_info,
757 },
758#endif
759#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
760 {
761 I2C_BOARD_INFO("ssm2602", 0x1b),
762 },
763#endif
764 {
765 I2C_BOARD_INFO("adm1192", 0x2e),
766 },
767
768 {
769 I2C_BOARD_INFO("ltc3576", 0x09),
770 },
771#if defined(CONFIG_INPUT_ADXL34X_I2C) \
772 || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
773 {
774 I2C_BOARD_INFO("adxl34x", 0x53),
775 .irq = IRQ_PH13,
776 .platform_data = (void *)&adxl345_info,
777 },
778#endif
779};
780
781#if defined(CONFIG_SERIAL_BFIN_SPORT) \
782 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
783#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
784static struct resource bfin_sport0_uart_resources[] = {
785 {
786 .start = SPORT0_TCR1,
787 .end = SPORT0_MRCS3+4,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .start = IRQ_SPORT0_RX,
792 .end = IRQ_SPORT0_RX+1,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = IRQ_SPORT0_ERROR,
797 .end = IRQ_SPORT0_ERROR,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802static unsigned short bfin_sport0_peripherals[] = {
803 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
804 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
805};
806
807static struct platform_device bfin_sport0_uart_device = {
808 .name = "bfin-sport-uart",
809 .id = 0,
810 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
811 .resource = bfin_sport0_uart_resources,
812 .dev = {
813 .platform_data = &bfin_sport0_peripherals,
814 /* Passed to driver */
815 },
816};
817#endif
818#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
819static struct resource bfin_sport1_uart_resources[] = {
820 {
821 .start = SPORT1_TCR1,
822 .end = SPORT1_MRCS3+4,
823 .flags = IORESOURCE_MEM,
824 },
825 {
826 .start = IRQ_SPORT1_RX,
827 .end = IRQ_SPORT1_RX+1,
828 .flags = IORESOURCE_IRQ,
829 },
830 {
831 .start = IRQ_SPORT1_ERROR,
832 .end = IRQ_SPORT1_ERROR,
833 .flags = IORESOURCE_IRQ,
834 },
835};
836
837static unsigned short bfin_sport1_peripherals[] = {
838 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
839 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
840};
841
842static struct platform_device bfin_sport1_uart_device = {
843 .name = "bfin-sport-uart",
844 .id = 1,
845 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
846 .resource = bfin_sport1_uart_resources,
847 .dev = {
848 .platform_data = &bfin_sport1_peripherals,
849 /* Passed to driver */
850 },
851};
852#endif
853#endif
854
855static const unsigned int cclk_vlev_datasheet[] = {
856 VRPAIR(VLEV_100, 400000000),
857 VRPAIR(VLEV_105, 426000000),
858 VRPAIR(VLEV_110, 500000000),
859 VRPAIR(VLEV_115, 533000000),
860 VRPAIR(VLEV_120, 600000000),
861};
862
863static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
864 .tuple_tab = cclk_vlev_datasheet,
865 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
866 .vr_settling_time = 25 /* us */,
867};
868
869static struct platform_device bfin_dpmc = {
870 .name = "bfin dpmc",
871 .dev = {
872 .platform_data = &bfin_dmpc_vreg_data,
873 },
874};
875
876static struct platform_device *tll6527m_devices[] __initdata = {
877
878 &bfin_dpmc,
879
880#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
881 &rtc_device,
882#endif
883
884#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
885 &musb_device,
886#endif
887
888#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
889 &bfin_mii_bus,
890 &bfin_mac_device,
891#endif
892
893#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
894 &bfin_spi0_device,
895#endif
896
897#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
898 &bfin_lq035q1_device,
899#endif
900
901#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
902#ifdef CONFIG_SERIAL_BFIN_UART0
903 &bfin_uart0_device,
904#endif
905#ifdef CONFIG_SERIAL_BFIN_UART1
906 &bfin_uart1_device,
907#endif
908#endif
909
910#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
911#ifdef CONFIG_BFIN_SIR0
912 &bfin_sir0_device,
913#endif
914#ifdef CONFIG_BFIN_SIR1
915 &bfin_sir1_device,
916#endif
917#endif
918
919#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
920 &i2c_bfin_twi_device,
921#endif
922
923#if defined(CONFIG_SERIAL_BFIN_SPORT) \
924 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
925#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
926 &bfin_sport0_uart_device,
927#endif
928#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
929 &bfin_sport1_uart_device,
930#endif
931#endif
932
933#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
934 &tll6527m_flash_device,
935#endif
936
937#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
938 &bfin_i2s,
939#endif
940
941#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
942 &spi_decoded_gpio,
943#endif
944};
945
946static int __init tll6527m_init(void)
947{
948 printk(KERN_INFO "%s(): registering device resources\n", __func__);
949 i2c_register_board_info(0, bfin_i2c_board_info,
950 ARRAY_SIZE(bfin_i2c_board_info));
951 platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
952 spi_register_board_info(bfin_spi_board_info,
953 ARRAY_SIZE(bfin_spi_board_info));
954 return 0;
955}
956
957arch_initcall(tll6527m_init);
958
959static struct platform_device *tll6527m_early_devices[] __initdata = {
960#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
961#ifdef CONFIG_SERIAL_BFIN_UART0
962 &bfin_uart0_device,
963#endif
964#ifdef CONFIG_SERIAL_BFIN_UART1
965 &bfin_uart1_device,
966#endif
967#endif
968
969#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
970#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
971 &bfin_sport0_uart_device,
972#endif
973#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
974 &bfin_sport1_uart_device,
975#endif
976#endif
977};
978
979void __init native_machine_early_platform_add_devices(void)
980{
981 printk(KERN_INFO "register early platform devices\n");
982 early_platform_add_devices(tll6527m_early_devices,
983 ARRAY_SIZE(tll6527m_early_devices));
984}
985
986void native_machine_restart(char *cmd)
987{
988 /* workaround reboot hang when booting from SPI */
989 if ((bfin_read_SYSCR() & 0x7) == 0x3)
990 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
991}
992
993void bfin_get_ether_addr(char *addr)
994{
995 /* the MAC is stored in OTP memory page 0xDF */
996 u32 ret;
997 u64 otp_mac;
998 u32 (*otp_read)(u32 page, u32 flags,
999 u64 *page_content) = (void *)0xEF00001A;
1000
1001 ret = otp_read(0xDF, 0x00, &otp_mac);
1002 if (!(ret & 0x1)) {
1003 char *otp_mac_p = (char *)&otp_mac;
1004 for (ret = 0; ret < 6; ++ret)
1005 addr[ret] = otp_mac_p[5 - ret];
1006 }
1007}
1008EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
index 7bc7577d6c4f..1fabdefea73a 100644
--- a/arch/blackfin/mach-bf527/dma.c
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 9358afa05c90..e66a7e89cd3c 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,14 +5,14 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2010 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the ADI BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
220#define ANOMALY_05000483 (1) 220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
223/* The CODEC Zero-Cross Detect Feature is not Functional */
224#define ANOMALY_05000487 (1)
223/* IFLUSH sucks at life */ 225/* IFLUSH sucks at life */
224#define ANOMALY_05000491 (1) 226#define ANOMALY_05000491 (1)
225 227
@@ -268,11 +270,13 @@
268#define ANOMALY_05000323 (0) 270#define ANOMALY_05000323 (0)
269#define ANOMALY_05000362 (1) 271#define ANOMALY_05000362 (1)
270#define ANOMALY_05000363 (0) 272#define ANOMALY_05000363 (0)
273#define ANOMALY_05000383 (0)
271#define ANOMALY_05000400 (0) 274#define ANOMALY_05000400 (0)
272#define ANOMALY_05000402 (0) 275#define ANOMALY_05000402 (0)
273#define ANOMALY_05000412 (0) 276#define ANOMALY_05000412 (0)
274#define ANOMALY_05000447 (0) 277#define ANOMALY_05000447 (0)
275#define ANOMALY_05000448 (0) 278#define ANOMALY_05000448 (0)
276#define ANOMALY_05000474 (0) 279#define ANOMALY_05000474 (0)
280#define ANOMALY_05000480 (0)
277 281
278#endif 282#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index c1d55b878b45..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Copyright 2007-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#include <linux/serial.h>
8#include <asm/dma.h>
9#include <asm/portmux.h>
10
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS
39
40# ifndef CONFIG_UART0_CTS_PIN
41# define CONFIG_UART0_CTS_PIN -1
42# endif
43
44# ifndef CONFIG_UART0_RTS_PIN
45# define CONFIG_UART0_RTS_PIN -1
46# endif
47
48# ifndef CONFIG_UART1_CTS_PIN
49# define CONFIG_UART1_CTS_PIN -1
50# endif
51
52# ifndef CONFIG_UART1_RTS_PIN
53# define CONFIG_UART1_RTS_PIN -1
54# endif
55#endif
56
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res {
102 unsigned long uart_base_addr;
103 int uart_irq;
104 int uart_status_irq;
105#ifdef CONFIG_SERIAL_BFIN_DMA
106 unsigned int uart_tx_dma_channel;
107 unsigned int uart_rx_dma_channel;
108#endif
109#ifdef CONFIG_SERIAL_BFIN_CTSRTS
110 int uart_cts_pin;
111 int uart_rts_pin;
112#endif
113};
114
115struct bfin_serial_res bfin_serial_resource[] = {
116#ifdef CONFIG_SERIAL_BFIN_UART0
117 {
118 0xFFC00400,
119 IRQ_UART0_RX,
120 IRQ_UART0_ERROR,
121#ifdef CONFIG_SERIAL_BFIN_DMA
122 CH_UART0_TX,
123 CH_UART0_RX,
124#endif
125#ifdef CONFIG_SERIAL_BFIN_CTSRTS
126 CONFIG_UART0_CTS_PIN,
127 CONFIG_UART0_RTS_PIN,
128#endif
129 },
130#endif
131#ifdef CONFIG_SERIAL_BFIN_UART1
132 {
133 0xFFC02000,
134 IRQ_UART1_RX,
135 IRQ_UART1_ERROR,
136#ifdef CONFIG_SERIAL_BFIN_DMA
137 CH_UART1_TX,
138 CH_UART1_RX,
139#endif
140#ifdef CONFIG_SERIAL_BFIN_CTSRTS
141 CONFIG_UART1_CTS_PIN,
142 CONFIG_UART1_RTS_PIN,
143#endif
144 },
145#endif
146};
147
148#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index f714c5de3073..e1d279274487 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -1,49 +1,37 @@
1/* 1/*
2 * Copyright 2007-2009 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
8#define _MACH_BLACKFIN_H_ 8#define _MACH_BLACKFIN_H_
9 9
10#include "bf527.h" 10#include "bf527.h"
11#include "defBF522.h"
12#include "anomaly.h" 11#include "anomaly.h"
13 12
14#if defined(CONFIG_BF527) || defined(CONFIG_BF526) 13#include <asm/def_LPBlackfin.h>
15#include "defBF527.h" 14#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
15# include "defBF522.h"
16#endif 16#endif
17
18#if defined(CONFIG_BF525) || defined(CONFIG_BF524) 17#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
19#include "defBF525.h" 18# include "defBF525.h"
20#endif 19#endif
21
22#if !defined(__ASSEMBLY__)
23#include "cdefBF522.h"
24
25#if defined(CONFIG_BF527) || defined(CONFIG_BF526) 20#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
26#include "cdefBF527.h" 21# include "defBF527.h"
27#endif 22#endif
28 23
29#if defined(CONFIG_BF525) || defined(CONFIG_BF524) 24#if !defined(__ASSEMBLY__)
30#include "cdefBF525.h" 25# include <asm/cdef_LPBlackfin.h>
31#endif 26# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
27# include "cdefBF522.h"
28# endif
29# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
30# include "cdefBF525.h"
31# endif
32# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
33# include "cdefBF527.h"
34# endif
32#endif 35#endif
33 36
34#define BFIN_UART_NR_PORTS 2
35
36#define OFFSET_THR 0x00 /* Transmit Holding register */
37#define OFFSET_RBR 0x00 /* Receive Buffer register */
38#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
39#define OFFSET_IER 0x04 /* Interrupt Enable Register */
40#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
41#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
42#define OFFSET_LCR 0x0C /* Line Control Register */
43#define OFFSET_MCR 0x10 /* Modem Control Register */
44#define OFFSET_LSR 0x14 /* Line Status Register */
45#define OFFSET_MSR 0x18 /* Modem Status Register */
46#define OFFSET_SCR 0x1C /* SCR Scratch Register */
47#define OFFSET_GCTL 0x24 /* Global Control Register */
48
49#endif 37#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 1079af8c7aef..2c12e879aa4e 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1,21 +1,1095 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF522_H 7#ifndef _CDEF_BF522_H
8#define _CDEF_BF522_H 8#define _CDEF_BF522_H
9 9
10/* include all Core registers and bit definitions */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
11#include "defBF522.h" 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
13#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
14#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
15#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
16#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
17#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
18#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
19#define bfin_read_CHIPID() bfin_read32(CHIPID)
20#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
12 21
13/* include core specific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15 22
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ 23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24#define bfin_read_SWRST() bfin_read16(SWRST)
25#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
26#define bfin_read_SYSCR() bfin_read16(SYSCR)
27#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
17 28
18/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 29#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
19#include "cdefBF52x_base.h" 30#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
31#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
32#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
33#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
34#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
35
36#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
38#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
39#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
40#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
41#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
42#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
43#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
44
45#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
46#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
47#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
48#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
49
50#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
54
55/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
56
57#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
58#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
59#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
60#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
61#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
62#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
63#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
64#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
65#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
66#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
67#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
68#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
69#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
70#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
71
72/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
73#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
74#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
75#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
76#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
77#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
78#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
79
80
81/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
83#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
84#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
85#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
86#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
87#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
88#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
89#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
90#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
91#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
92#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
93#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
94#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
95#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
96
97
98/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
99#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
100#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
101#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
102#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
103#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
104#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
105#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
106#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
107#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
108#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
109#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
110#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
111#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
112#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
113#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
114#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
115#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
116#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
117#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
118#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
119#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
120#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
121#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
122#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
123
124
125/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
126#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
127#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
128#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
129#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
130#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
131#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
132#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
133#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
134#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
135#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
136#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
137#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
138#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
139#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
140
141
142/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
143#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
144#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
145#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
146#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
147#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
148#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
149#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
150#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
151
152#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
153#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
154#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
155#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
156#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
157#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
158#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
159#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
160
161#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
162#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
163#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
164#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
165#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
166#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
167#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
168#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
169
170#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
171#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
172#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
173#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
174#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
175#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
176#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
177#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
178
179#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
180#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
181#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
182#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
183#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
184#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
185#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
186#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
187
188#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
189#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
190#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
191#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
192#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
193#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
194#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
195#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
196
197#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
198#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
199#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
200#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
201#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
202#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
203#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
204#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
205
206#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
207#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
208#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
209#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
210#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
211#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
212#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
213#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
214
215#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
216#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
217#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
218#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
219#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
220#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
221
222
223/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
224#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
225#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
226#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
227#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
228#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
229#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
230#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
231#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
232#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
233#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
234#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
235#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
236#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
237#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
238#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
239#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
240#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
241#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
242#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
243#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
244#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
245#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
246#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
247#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
248#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
249#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
250#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
251#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
252#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
253#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
254#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
255#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
256#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
257#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
258
259
260/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
261#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
262#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
263#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
264#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
265#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
266#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
267#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
268#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
269#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
270#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
271#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
272#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
273#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
274#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
275#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
276#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
277#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
278#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
279#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
280#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
281#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
282#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
283#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
284#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
285#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
286#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
287#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
288#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
289#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
290#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
291#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
292#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
293#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
294#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
295#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
296#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
297#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
298#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
299#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
300#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
301#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
302#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
303#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
304#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
305#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
306#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
307#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
308#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
309#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
310#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
311#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
312#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
313
314
315/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
316#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
317#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
318#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
319#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
320#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
321#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
322#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
323#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
324#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
325#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
326#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
327#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
328#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
329#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
330#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
331#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
332#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
333#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
334#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
335#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
336#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
337#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
338#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
339#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
340#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
341#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
342#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
343#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
344#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
345#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
346#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
347#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
348#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
349#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
350#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
351#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
352#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
353#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
354#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
355#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
356#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
357#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
358#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
359#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
360#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
361#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
362#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
363#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
364#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
365#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
366#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
367#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
368
369
370/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
371#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
372#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
373#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
374#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
375#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
376#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
377#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
378#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
379#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
380#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
381#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
382#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
383#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
384#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
385
386
387/* DMA Traffic Control Registers */
388#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
389#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
390#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
391#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
392
393/* DMA Controller */
394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
396#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
397#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
398#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
399#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
400#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
401#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
402#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
403#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
404#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
405#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
406#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
407#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
408#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
409#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
410#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
412#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
413#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
414#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
415#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
416#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
417#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
418#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
419#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
420
421#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
422#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
423#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
424#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
425#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
427#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
428#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
431#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
432#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
433#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
434#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
435#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
436#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
437#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
438#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
439#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
440#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
441#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
442#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
443#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
444#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
445#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
446#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
447
448#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
449#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
450#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
451#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
452#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
453#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
456#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
457#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
458#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
459#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
466#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
467#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
468#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
469#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
470#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
471#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
472#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
473#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
474
475#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
476#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
481#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
482#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
483#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
484#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
487#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
488#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
489#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
490#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
491#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
492#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
493#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
494#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
495#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
496#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
497#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
498#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
499#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
500#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
501
502#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
503#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
504#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
505#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
506#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
507#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
508#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
509#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
510#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
511#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
512#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
513#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
514#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
515#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
516#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
517#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
518#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
519#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
520#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
521#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
522#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
523#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
527#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
528
529#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
530#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
531#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
532#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
533#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
534#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
535#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
536#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
537#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
538#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
539#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
540#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
541#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
542#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
543#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
544#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
545#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
546#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
547#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
548#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
549#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
550#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
551#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
552#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
553#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
554#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
555
556#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
557#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
558#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
559#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
560#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
561#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
562#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
563#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
564#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
565#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
566#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
567#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
568#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
569#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
570#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
571#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
572#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
573#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
574#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
575#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
576#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
577#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
578#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
579#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
580#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
581#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
582
583#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
584#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
585#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
586#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
587#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
588#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
589#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
590#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
591#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
592#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
593#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
594#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
595#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
596#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
597#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
598#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
599#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
600#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
601#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
602#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
603#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
604#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
605#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
606#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
607#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
608#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
609
610#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
611#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
612#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
613#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
614#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
615#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
616#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
617#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
618#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
619#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
620#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
621#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
622#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
623#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
624#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
625#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
626#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
627#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
628#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
629#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
630#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
631#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
632#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
633#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
634#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
635#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
636
637#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
638#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
639#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
640#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
641#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
642#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
643#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
644#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
645#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
646#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
647#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
648#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
649#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
650#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
651#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
652#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
653#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
654#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
655#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
656#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
657#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
658#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
659#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
660#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
661#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
662#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
663
664#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
665#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
666#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
667#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
668#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
669#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
670#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
671#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
672#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
673#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
674#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
675#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
676#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
677#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
678#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
679#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
680#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
681#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
682#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
683#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
684#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
685#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
686#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
687#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
688#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
689#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
690
691#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
692#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
693#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
694#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
695#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
696#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
697#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
698#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
699#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
700#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
701#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
702#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
703#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
704#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
705#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
706#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
707#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
708#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
709#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
710#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
711#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
712#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
713#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
714#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
715#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
716#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
717
718#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
719#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
720#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
721#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
722#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
723#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
724#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
725#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
726#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
727#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
728#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
729#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
730#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
731#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
732#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
733#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
734#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
735#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
736#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
737#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
738#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
739#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
740#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
741#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
742#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
743#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
744
745#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
746#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
747#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
748#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
749#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
750#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
751#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
752#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
753#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
754#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
755#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
756#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
757#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
758#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
759#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
760#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
761#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
762#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
763#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
764#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
765#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
766#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
767#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
768#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
769#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
770#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
771
772#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
773#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
774#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
775#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
776#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
777#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
778#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
779#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
780#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
781#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
782#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
783#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
784#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
785#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
786#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
787#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
788#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
789#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
790#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
791#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
792#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
793#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
794#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
795#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
796#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
797#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
798
799#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
800#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
801#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
802#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
803#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
804#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
805#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
806#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
807#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
808#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
809#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
810#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
811#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
812#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
813#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
814#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
815#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
816#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
817#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
818#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
819#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
820#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
821#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
822#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
823#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
824#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
825
826
827/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
828#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
829#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
830#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
831#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
832#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
833#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
834#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
835#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
836#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
837#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
838#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
839
840
841/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
842
843/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
844#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
845#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
846#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
847#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
848#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
849#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
850#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
851#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
852#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
853#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
854#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
855#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
856#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
857#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
858#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
859#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
860#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
861#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
862#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
863#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
864#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
865#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
866#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
867#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
868#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
869#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
870#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
871#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
872#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
873#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
874#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
875#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
876#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
877#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
878
879
880/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
881#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
882#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
883#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
884#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
885#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
886#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
887#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
888#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
889#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
890#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
891#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
892#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
893#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
894#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
895#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
896#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
897#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
898#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
899#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
900#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
901#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
902#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
903#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
904#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
905#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
906#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
907#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
908#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
909#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
910#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
911#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
912#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
913#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
914#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
915
916
917/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
918#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
919#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
920#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
921#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
922#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
923#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
924#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
925#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
926#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
927#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
928#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
929#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
930#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
931#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
932#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
933#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
934#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
935#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
936#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
937#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
938#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
939#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
940#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
941#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
942
943/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
944
945/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
946#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
947#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
948#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
949#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
950#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
951#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
952#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
953#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
954
955
956/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
957#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
958#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
959#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
960#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
961#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
962#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
963#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
964#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
965#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
966#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
967#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
968#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
969#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
970#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
971
972#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
973#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
974#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
975#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
976#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
977#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
978#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
979#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
980#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
981#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
982#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
983#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
984#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
985#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
986
987/* ==== end from cdefBF534.h ==== */
988
989/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
990
991#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
992#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
993#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
994#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
995#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
996#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
997
998#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
999#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1000#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1001#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1002#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1003#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1004#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1005#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1006#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1007#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1008#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1009#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1010#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
1011#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
1012#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
1013#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
1014#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
1015#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
1016#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1017#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1018#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1019#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1020#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
1021#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
1022
1023/* HOST Port Registers */
1024
1025#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1026#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1027#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1028#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1029#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1030#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1031
1032/* Counter Registers */
1033
1034#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1035#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1036#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1037#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1038#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1039#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1040#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1041#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1042#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1043#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1044#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1045#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1046#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1047#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1048#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1049#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1050
1051/* Security Registers */
1052
1053#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1054#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1055#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1056#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1057#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1058#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1059
1060/* NFC Registers */
1061
1062#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1063#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1064#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1065#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1066#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1067#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1068#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1069#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1070#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1071#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1072#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1073#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1074#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1075#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1076#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1077#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1078#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1079#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1080#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1081#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1082#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1083#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1084#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1085#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1086#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1087#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1088#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1089#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1090#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1091#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1092#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1093#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
20 1094
21#endif /* _CDEF_BF522_H */ 1095#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index d7e2751c6bcc..d90a85b6b6b9 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -1,15 +1,12 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF525_H 7#ifndef _CDEF_BF525_H
8#define _CDEF_BF525_H 8#define _CDEF_BF525_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF525.h"
12
13/* BF525 is BF522 + USB */ 10/* BF525 is BF522 + USB */
14#include "cdefBF522.h" 11#include "cdefBF522.h"
15 12
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index c7ba544d50b6..eb22f5866105 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -1,15 +1,12 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF527_H 7#ifndef _CDEF_BF527_H
8#define _CDEF_BF527_H 8#define _CDEF_BF527_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF527.h"
12
13/* BF527 is BF525 + EMAC */ 10/* BF527 is BF525 + EMAC */
14#include "cdefBF525.h" 11#include "cdefBF525.h"
15 12
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
deleted file mode 100644
index 12f2ad45314e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ /dev/null
@@ -1,1163 +0,0 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _CDEF_BF52X_H
8#define _CDEF_BF52X_H
9
10#include <asm/blackfin.h>
11
12#include "defBF52x_base.h"
13
14/* Include core specific register pointer definitions */
15#include <asm/cdef_LPBlackfin.h>
16
17/* ==== begin from cdefBF534.h ==== */
18
19/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
20#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
21#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
23#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
24#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
25#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
26#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
27#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
28#define bfin_read_CHIPID() bfin_read32(CHIPID)
29#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
30
31
32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33#define bfin_read_SWRST() bfin_read16(SWRST)
34#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
35#define bfin_read_SYSCR() bfin_read16(SYSCR)
36#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
37
38#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
39#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
42#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
44
45#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
46#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
47#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
48#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
49#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
50#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
51#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
52#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
53
54#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
55#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
57#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
58
59#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
60#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
61#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
62#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
63
64/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
65
66#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
67#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
68#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
69#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
70#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
71#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
72#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
73#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
74#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
75#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
76#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
78#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
79#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
80
81/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
82#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
83#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
84#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
85#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
86#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
87#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
88
89
90/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
91#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
92#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
93#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
94#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
95#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
96#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
97#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
98#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
99#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
100#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
101#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
102#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
103#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
104#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
105
106
107/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
108#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
109#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
110#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
111#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
112#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
113#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
114#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
115#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
116#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
117#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
118#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
119#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
120#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
121#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
122#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
123#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
124#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
125#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
126#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
127#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
128#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
129#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
130#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
132
133
134/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
135#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
136#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
137#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
138#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
139#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
140#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
141#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
142#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
143#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
144#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
145#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
146#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
147#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
148#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
149
150
151/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
152#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
153#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
154#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
155#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
156#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
157#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
158#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
159#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
160
161#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
162#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
163#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
164#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
165#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
166#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
167#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
168#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
169
170#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
171#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
172#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
173#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
174#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
175#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
176#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
177#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
178
179#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
180#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
181#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
182#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
183#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
184#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
185#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
186#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
187
188#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
189#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
190#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
191#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
192#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
193#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
194#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
195#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
196
197#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
198#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
199#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
200#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
201#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
202#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
203#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
204#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
205
206#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
207#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
208#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
209#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
210#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
211#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
212#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
213#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
214
215#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
216#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
217#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
218#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
219#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
220#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
221#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
222#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
223
224#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
225#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
226#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
227#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
228#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
229#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
230
231
232/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
233#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
234#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
235#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
236#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
237#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
238#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
239#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
240#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
241#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
242#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
243#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
244#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
245#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
246#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
247#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
248#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
249#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
250#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
251#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
252#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
253#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
254#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
255#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
256#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
257#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
258#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
259#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
260#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
261#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
262#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
263#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
264#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
265#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
266#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
267
268
269/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
270#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
271#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
272#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
273#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
274#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
275#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
276#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
277#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
278#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
293#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
294#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
295#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
296#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
297#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
298#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
299#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
300#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
301#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
302#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
303#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
304#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
305#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
306#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
307#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
308#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
309#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
310#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
311#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
312#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
313#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
314#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
315#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
316#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
317#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
318#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
319#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
320#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
321#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
322
323
324/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
325#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
326#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
327#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
328#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
329#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
330#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
331#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
332#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
333#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
348#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
349#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
350#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
351#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
352#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
353#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
354#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
355#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
356#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
357#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
358#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
359#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
360#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
361#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
362#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
363#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
364#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
365#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
366#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
367#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
368#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
369#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
370#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
371#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
372#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
373#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
374#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
375#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
376#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
377
378
379/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
380#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
381#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
382#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
383#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
384#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
385#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
386#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
387#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
388#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
389#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
390#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
391#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
392#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
393#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
394
395
396/* DMA Traffic Control Registers */
397#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
398#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
399#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
400#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
401
402/* Alternate deprecated register names (below) provided for backwards code compatibility */
403#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
404#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
405#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
406#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
407
408/* DMA Controller */
409#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
410#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
411#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
412#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
413#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
414#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
415#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
416#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
417#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
418#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
419#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
420#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
421#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
422#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
423#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
424#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
425#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
426#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
427#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
428#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
429#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
430#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
431#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
432#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
433#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
434#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
435
436#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
437#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
438#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
439#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
440#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
441#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
442#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
443#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
444#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
445#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
446#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
447#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
448#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
449#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
450#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
451#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
452#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
453#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
454#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
455#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
456#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
457#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
458#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
459#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
460#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
461#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
462
463#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
464#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
465#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
466#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
467#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
468#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
469#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
470#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
471#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
472#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
473#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
474#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
475#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
476#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
477#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
478#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
479#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
480#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
481#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
482#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
483#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
484#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
485#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
486#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
487#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
488#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
489
490#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
491#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
492#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
493#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
494#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
495#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
496#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
497#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
498#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
499#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
500#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
501#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
502#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
503#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
504#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
505#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
506#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
507#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
508#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
509#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
510#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
511#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
512#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
513#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
514#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
515#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
516
517#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
518#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
519#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
520#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
521#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
523#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
524#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
525#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
526#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
527#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
528#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
529#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
530#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
531#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
532#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
533#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
534#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
535#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
536#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
537#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
538#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
539#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
540#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
541#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
542#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
543
544#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
545#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
546#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
547#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
548#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
549#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
550#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
551#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
552#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
554#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
555#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
556#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
557#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
558#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
559#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
560#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
561#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
562#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
563#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
564#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
565#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
566#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
567#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
568#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
569#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
570
571#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
572#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
573#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
574#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
575#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
576#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
577#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
578#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
579#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
580#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
581#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
582#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
583#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
584#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
585#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
586#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
587#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
588#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
589#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
590#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
591#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
592#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
593#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
594#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
595#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
596#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
597
598#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
599#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
600#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
601#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
602#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
603#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
604#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
605#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
606#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
607#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
608#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
609#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
610#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
611#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
612#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
613#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
614#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
615#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
616#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
617#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
618#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
619#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
620#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
621#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
622#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
623#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
624
625#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
627#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
628#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
629#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
630#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
631#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
632#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
633#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
634#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
635#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
636#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
637#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
638#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
639#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
640#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
641#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
642#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
647#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
648#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
649#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
650#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
651
652#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
653#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
654#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
655#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
656#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
657#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
658#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
659#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
660#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
661#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
662#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
663#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
664#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
665#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
666#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
667#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
668#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
669#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
670#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
671#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
672#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
673#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
674#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
675#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
676#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
677#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
678
679#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
680#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
681#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
682#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
683#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
684#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
685#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
686#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
687#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
688#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
689#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
690#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
691#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
692#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
693#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
694#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
695#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
696#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
697#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
698#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
699#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
700#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
701#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
702#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
703#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
704#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
705
706#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
707#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
708#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
709#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
710#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
711#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
712#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
713#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
714#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
715#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
716#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
717#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
718#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
719#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
720#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
721#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
722#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
723#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
724#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
725#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
726#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
727#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
728#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
729#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
730#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
731#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
732
733#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
734#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
735#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
736#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
737#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
738#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
739#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
740#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
741#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
742#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
743#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
744#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
745#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
746#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
747#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
748#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
749#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
750#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
751#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
752#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
753#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
754#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
755#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
756#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
757#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
758#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
759
760#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
761#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
762#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
763#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
764#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
765#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
766#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
767#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
768#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
769#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
770#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
771#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
772#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
773#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
774#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
775#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
776#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
777#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
778#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
779#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
780#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
781#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
786
787#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
788#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
789#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
790#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
791#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
792#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
793#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
794#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
795#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
796#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
797#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
798#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
799#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
800#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
801#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
802#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
803#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
804#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
805#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
806#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
807#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
808#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
809#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
810#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
811#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
812#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
813
814#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
815#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
816#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
817#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
818#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
819#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
820#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
821#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
822#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
823#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
824#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
825#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
826#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
827#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
828#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
829#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
830#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
831#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
832#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
833#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
834#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
835#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
836#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
837#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
838#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
839#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
840
841
842/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
843#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
844#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
845#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
846#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
847#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
848#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
849#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
850#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
851#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
852#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
853#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
854
855
856/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
857
858/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
859#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
860#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
861#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
862#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
863#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
864#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
865#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
866#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
867#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
868#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
869#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
870#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
871#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
872#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
873#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
874#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
875#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
876#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
877#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
878#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
879#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
880#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
881#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
882#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
883#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
884#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
885#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
886#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
887#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
888#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
889#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
890#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
891#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
892#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
893
894
895/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
896#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
897#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
898#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
899#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
900#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
901#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
902#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
903#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
904#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
905#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
906#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
907#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
908#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
909#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
910#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
911#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
912#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
913#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
914#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
915#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
916#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
917#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
918#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
919#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
920#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
921#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
922#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
923#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
924#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
925#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
926#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
927#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
928#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
929#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
930
931
932/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
933#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
934#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
935#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
936#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
937#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
938#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
939#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
940#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
941#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
942#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
943#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
944#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
945#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
946#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
947#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
948#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
949#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
950#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
951#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
952#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
953#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
954#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
955#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
956#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
957
958/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
959
960/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
961#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
962#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
963#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
964#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
965#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
966#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
967#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
968#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
969
970
971/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
972#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
973#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
974#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
975#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
976#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
977#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
978#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
979#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
980#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
981#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
982#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
983#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
984#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
985#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
986
987#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
988#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
989#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
990#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
991#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
992#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
993#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
994#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
995#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
996#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
997#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
998#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
999#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1000#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1001
1002/* ==== end from cdefBF534.h ==== */
1003
1004/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1005
1006#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1007#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1008#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1009#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1010#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1011#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1012
1013#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1014#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1015#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1016#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1017#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1018#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1019#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1020#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1021#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1022#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1023#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1024#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1025#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1026#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1027#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1028#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1029#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1030#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1031#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1032#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1033#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1034#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1035#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1036#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1037
1038/* HOST Port Registers */
1039
1040#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1041#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1042#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1043#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1044#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1045#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1046
1047/* Counter Registers */
1048
1049#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1050#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1051#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1052#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1053#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1054#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1055#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1056#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1057#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1058#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1059#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1060#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1061#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1062#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1063#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1064#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1065
1066/* Security Registers */
1067
1068#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1069#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1070#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1071#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1072#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1073#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1074
1075/* NFC Registers */
1076
1077#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1078#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1079#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1080#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1081#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1082#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1083#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1084#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1085#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1086#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1087#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1088#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1089#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1090#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1091#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1092#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1093#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1094#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1095#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1096#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1097#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1098#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1099#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1100#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1101#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1102#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1103#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1104#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1105#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1106#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1107#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1108#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1109
1110/* These need to be last due to the cdef/linux inter-dependencies */
1111#include <asm/irq.h>
1112
1113/* Writing to PLL_CTL initiates a PLL relock sequence. */
1114static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1115{
1116 unsigned long flags, iwr0, iwr1;
1117
1118 if (val == bfin_read_PLL_CTL())
1119 return;
1120
1121 local_irq_save_hw(flags);
1122 /* Enable the PLL Wakeup bit in SIC IWR */
1123 iwr0 = bfin_read32(SIC_IWR0);
1124 iwr1 = bfin_read32(SIC_IWR1);
1125 /* Only allow PPL Wakeup) */
1126 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1127 bfin_write32(SIC_IWR1, 0);
1128
1129 bfin_write16(PLL_CTL, val);
1130 SSYNC();
1131 asm("IDLE;");
1132
1133 bfin_write32(SIC_IWR0, iwr0);
1134 bfin_write32(SIC_IWR1, iwr1);
1135 local_irq_restore_hw(flags);
1136}
1137
1138/* Writing to VR_CTL initiates a PLL relock sequence. */
1139static __inline__ void bfin_write_VR_CTL(unsigned int val)
1140{
1141 unsigned long flags, iwr0, iwr1;
1142
1143 if (val == bfin_read_VR_CTL())
1144 return;
1145
1146 local_irq_save_hw(flags);
1147 /* Enable the PLL Wakeup bit in SIC IWR */
1148 iwr0 = bfin_read32(SIC_IWR0);
1149 iwr1 = bfin_read32(SIC_IWR1);
1150 /* Only allow PPL Wakeup) */
1151 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1152 bfin_write32(SIC_IWR1, 0);
1153
1154 bfin_write16(VR_CTL, val);
1155 SSYNC();
1156 asm("IDLE;");
1157
1158 bfin_write32(SIC_IWR0, iwr0);
1159 bfin_write32(SIC_IWR1, iwr1);
1160 local_irq_restore_hw(flags);
1161}
1162
1163#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index cb139a254810..37d353a19722 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,12 +7,1374 @@
7#ifndef _DEF_BF522_H 7#ifndef _DEF_BF522_H
8#define _DEF_BF522_H 8#define _DEF_BF522_H
9 9
10/* Include all Core registers and bit definitions */ 10/* ************************************************************** */
11#include <asm/def_LPBlackfin.h> 11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
12/* ************************************************************** */
12 13
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ 14/* ==== begin from defBF534.h ==== */
14 15
15/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 16/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
16#include "defBF52x_base.h" 17#define PLL_CTL 0xFFC00000 /* PLL Control Register */
18#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
19#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
20#define PLL_STAT 0xFFC0000C /* PLL Status Register */
21#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
22#define CHIPID 0xFFC00014 /* Device ID Register */
23
24
25/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
26#define SWRST 0xFFC00100 /* Software Reset Register */
27#define SYSCR 0xFFC00104 /* System Configuration Register */
28#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
29
30#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
31#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
32#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
33#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
34#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
35#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
36#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
37
38/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
39#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
40#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
41#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
42#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
43#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
44#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
45#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
46
47
48/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
49#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
50#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
51#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
52
53
54/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
55#define RTC_STAT 0xFFC00300 /* RTC Status Register */
56#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
57#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
58#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
59#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
60#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
61#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
62
63
64/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
65#define UART0_THR 0xFFC00400 /* Transmit Holding register */
66#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
67#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
68#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
69#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
70#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
71#define UART0_LCR 0xFFC0040C /* Line Control Register */
72#define UART0_MCR 0xFFC00410 /* Modem Control Register */
73#define UART0_LSR 0xFFC00414 /* Line Status Register */
74#define UART0_MSR 0xFFC00418 /* Modem Status Register */
75#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
76#define UART0_GCTL 0xFFC00424 /* Global Control Register */
77
78
79/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
80#define SPI0_REGBASE 0xFFC00500
81#define SPI_CTL 0xFFC00500 /* SPI Control Register */
82#define SPI_FLG 0xFFC00504 /* SPI Flag register */
83#define SPI_STAT 0xFFC00508 /* SPI Status register */
84#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
85#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
86#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
87#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
88
89
90/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
91#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
92#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
93#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
94#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
95
96#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
97#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
98#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
99#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
100
101#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
102#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
103#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
104#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
105
106#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
107#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
108#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
109#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
110
111#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
112#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
113#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
114#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
115
116#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
117#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
118#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
119#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
120
121#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
122#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
123#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
124#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
125
126#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
127#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
128#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
129#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
130
131#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
132#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
133#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
134
135
136/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
137#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
138#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
139#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
140#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
141#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
142#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
143#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
144#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
145#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
146#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
147#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
148#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
149#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
150#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
151#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
152#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
153#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
154
155
156/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
157#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
158#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
159#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
160#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
161#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
162#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
163#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
166#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
167#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
168#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
169#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
170#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
171#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
172#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
173#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
174#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
175#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
176#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
177#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
178#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
179
180
181/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
182#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
183#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
184#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
185#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
186#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
187#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
188#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
189#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
190#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
191#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
192#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
193#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
194#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
195#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
196#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
197#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
198#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
199#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
200#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
201#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
202#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
203#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
204
205
206/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
207#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
208#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
209#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
210#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
211#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
212#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
213#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
214
215
216/* DMA Traffic Control Registers */
217#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
218#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
219
220/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
221#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
222#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
223#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
224#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
225#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
226#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
227#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
228#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
229#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
230#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
231#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
232#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
233#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
234
235#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
236#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
237#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
238#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
239#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
240#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
241#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
242#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
243#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
244#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
245#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
246#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
247#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
248
249#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
250#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
251#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
252#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
253#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
254#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
255#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
256#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
257#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
258#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
259#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
260#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
261#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
262
263#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
264#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
265#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
266#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
267#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
268#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
269#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
270#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
271#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
272#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
273#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
274#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
275#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
276
277#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
278#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
279#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
280#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
281#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
282#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
283#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
284#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
285#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
286#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
287#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
288#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
289#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
290
291#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
292#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
293#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
294#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
295#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
296#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
297#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
298#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
299#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
300#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
301#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
302#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
303#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
304
305#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
306#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
307#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
308#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
309#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
310#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
311#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
312#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
313#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
314#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
315#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
316#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
317#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
318
319#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
320#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
321#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
322#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
323#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
324#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
325#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
326#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
327#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
328#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
329#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
330#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
331#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
332
333#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
334#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
335#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
336#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
337#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
338#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
339#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
340#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
341#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
342#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
343#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
344#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
345#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
346
347#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
348#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
349#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
350#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
351#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
352#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
353#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
354#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
355#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
356#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
357#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
358#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
359#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
360
361#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
362#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
363#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
364#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
365#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
366#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
367#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
368#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
369#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
370#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
371#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
372#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
373#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
374
375#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
376#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
377#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
378#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
379#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
380#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
381#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
382#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
383#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
384#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
385#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
386#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
387#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
388
389#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
390#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
391#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
392#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
393#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
394#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
395#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
396#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
397#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
398#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
399#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
400#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
401#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
402
403#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
404#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
405#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
406#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
407#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
408#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
409#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
410#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
411#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
412#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
413#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
414#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
415#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
416
417#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
418#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
419#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
420#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
421#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
422#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
423#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
424#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
425#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
426#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
427#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
428#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
429#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
430
431#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
432#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
433#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
434#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
435#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
436#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
437#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
438#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
439#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
440#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
441#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
442#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
443#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
444
445
446/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
447#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
448#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
449#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
450#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
451#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
452
453
454/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
455#define TWI0_REGBASE 0xFFC01400
456#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
457#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
458#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
459#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
460#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
461#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
462#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
463#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
464#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
465#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
466#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
467#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
468#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
469#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
470#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
471#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
472
473
474/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
475#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
476#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
477#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
478#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
479#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
480#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
481#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
482#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
483#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
484#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
485#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
486#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
487#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
488#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
489#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
490#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
491#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
492
493
494/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
495#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
496#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
497#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
498#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
499#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
500#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
501#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
502#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
503#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
504#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
505#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
506#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
507#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
508#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
509#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
510#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
511#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
512
513
514/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
515#define UART1_THR 0xFFC02000 /* Transmit Holding register */
516#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
517#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
518#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
519#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
520#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
521#define UART1_LCR 0xFFC0200C /* Line Control Register */
522#define UART1_MCR 0xFFC02010 /* Modem Control Register */
523#define UART1_LSR 0xFFC02014 /* Line Status Register */
524#define UART1_MSR 0xFFC02018 /* Modem Status Register */
525#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
526#define UART1_GCTL 0xFFC02024 /* Global Control Register */
527
528
529/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
530
531/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
532#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
533#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
534#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
535#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
536
537
538/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
539#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
540#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
541#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
542#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
543#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
544#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
545#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
546
547#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
548#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
549#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
550#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
551#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
552#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
553#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
554
555/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
556#define PORTF_MUX 0xFFC03210 /* Port F mux control */
557#define PORTG_MUX 0xFFC03214 /* Port G mux control */
558#define PORTH_MUX 0xFFC03218 /* Port H mux control */
559#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
560#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
561#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
562#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
563#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
564#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
565#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
566#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
567#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
568#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
569#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
570#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
571
572
573/***********************************************************************************
574** System MMR Register Bits And Macros
575**
576** Disclaimer: All macros are intended to make C and Assembly code more readable.
577** Use these macros carefully, as any that do left shifts for field
578** depositing will result in the lower order bits being destroyed. Any
579** macro that shifts left to properly position the bit-field should be
580** used as part of an OR to initialize a register and NOT as a dynamic
581** modifier UNLESS the lower order bits are saved and ORed back in when
582** the macro is used.
583*************************************************************************************/
584
585/* CHIPID Masks */
586#define CHIPID_VERSION 0xF0000000
587#define CHIPID_FAMILY 0x0FFFF000
588#define CHIPID_MANUFACTURE 0x00000FFE
589
590/* SWRST Masks */
591#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
592#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
593#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
594#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
595#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
596
597/* SYSCR Masks */
598#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
599#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
600
601
602/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
603/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
604
605#if 0
606#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
607
608#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
609#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
610#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
611#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
612#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
613#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
614#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
615
616#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
617#define IRQ_TWI 0x00000200 /* TWI Interrupt */
618#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
619#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
620#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
621#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
622#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
623#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
624
625#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
626#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
627#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
628#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
629#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
630#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
631#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
632#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
633#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
634#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
635
636#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
637#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
638#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
639#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
640#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
641#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
642#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
643#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
644#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
645#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
646#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
647#endif
648
649/* SIC_IAR0 Macros */
650#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
651#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
652#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
653#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
654#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
655#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
656#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
657#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
658
659/* SIC_IAR1 Macros */
660#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
661#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
662#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
663#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
664#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
665#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
666#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
667#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
668
669/* SIC_IAR2 Macros */
670#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
671#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
672#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
673#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
674#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
675#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
676#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
677#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
678
679/* SIC_IAR3 Macros */
680#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
681#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
682#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
683#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
684#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
685#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
686#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
687#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
688
689
690/* SIC_IMASK Masks */
691#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
692#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
693#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
694#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
695
696/* SIC_IWR Masks */
697#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
698#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
699#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
700#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
701
702/* **************** GENERAL PURPOSE TIMER MASKS **********************/
703/* TIMER_ENABLE Masks */
704#define TIMEN0 0x0001 /* Enable Timer 0 */
705#define TIMEN1 0x0002 /* Enable Timer 1 */
706#define TIMEN2 0x0004 /* Enable Timer 2 */
707#define TIMEN3 0x0008 /* Enable Timer 3 */
708#define TIMEN4 0x0010 /* Enable Timer 4 */
709#define TIMEN5 0x0020 /* Enable Timer 5 */
710#define TIMEN6 0x0040 /* Enable Timer 6 */
711#define TIMEN7 0x0080 /* Enable Timer 7 */
712
713/* TIMER_DISABLE Masks */
714#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
715#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
716#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
717#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
718#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
719#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
720#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
721#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
722
723/* TIMER_STATUS Masks */
724#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
725#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
726#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
727#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
728#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
729#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
730#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
731#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
732#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
733#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
734#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
735#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
736#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
737#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
738#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
739#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
740#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
741#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
742#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
743#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
744#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
745#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
746#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
747#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
748
749/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
750#define TOVL_ERR0 TOVF_ERR0
751#define TOVL_ERR1 TOVF_ERR1
752#define TOVL_ERR2 TOVF_ERR2
753#define TOVL_ERR3 TOVF_ERR3
754#define TOVL_ERR4 TOVF_ERR4
755#define TOVL_ERR5 TOVF_ERR5
756#define TOVL_ERR6 TOVF_ERR6
757#define TOVL_ERR7 TOVF_ERR7
758
759/* TIMERx_CONFIG Masks */
760#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
761#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
762#define EXT_CLK 0x0003 /* External Clock Mode */
763#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
764#define PERIOD_CNT 0x0008 /* Period Count */
765#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
766#define TIN_SEL 0x0020 /* Timer Input Select */
767#define OUT_DIS 0x0040 /* Output Pad Disable */
768#define CLK_SEL 0x0080 /* Timer Clock Select */
769#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
770#define EMU_RUN 0x0200 /* Emulation Behavior Select */
771#define ERR_TYP 0xC000 /* Error Type */
772
773/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
774/* EBIU_AMGCTL Masks */
775#define AMCKEN 0x0001 /* Enable CLKOUT */
776#define AMBEN_NONE 0x0000 /* All Banks Disabled */
777#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
778#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
779#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
780#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
781
782/* EBIU_AMBCTL0 Masks */
783#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
784#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
785#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
786#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
787#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
788#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
790#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
791#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
792#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
794#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
795#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
796#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
797#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
798#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
799#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
800#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
801#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
802#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
803#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
804#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
805#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
806#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
807#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
808#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
809#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
810#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
811#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
812#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
813#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
814#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
815#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
816#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
817#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
818#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
819#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
820#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
821#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
822#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
823#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
824#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
825#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
826#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
827
828#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
829#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
830#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
831#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
832#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
833#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
834#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
835#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
836#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
837#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
838#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
839#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
840#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
841#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
842#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
843#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
844#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
845#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
846#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
847#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
848#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
849#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
850#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
851#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
852#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
853#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
854#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
855#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
856#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
857#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
858#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
859#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
860#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
861#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
862#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
863#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
864#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
865#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
866#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
867#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
868#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
869#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
870#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
871#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
872
873/* EBIU_AMBCTL1 Masks */
874#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
875#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
876#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
877#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
878#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
879#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
881#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
882#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
883#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
885#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
886#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
887#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
888#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
889#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
890#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
891#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
892#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
893#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
894#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
895#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
896#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
897#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
898#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
899#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
900#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
901#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
902#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
903#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
904#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
905#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
906#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
907#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
908#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
909#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
910#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
911#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
912#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
913#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
914#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
915#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
916#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
917#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
918
919#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
920#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
921#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
922#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
923#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
924#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
925#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
926#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
927#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
928#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
929#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
930#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
931#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
932#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
933#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
934#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
935#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
936#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
937#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
938#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
939#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
940#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
941#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
942#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
943#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
944#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
945#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
946#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
947#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
948#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
949#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
950#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
951#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
952#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
953#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
954#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
955#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
956#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
957#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
958#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
959#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
960#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
961#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
962#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
963
964
965/* ********************** SDRAM CONTROLLER MASKS **********************************************/
966/* EBIU_SDGCTL Masks */
967#define SCTLE 0x00000001 /* Enable SDRAM Signals */
968#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
969#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
970#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
971#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
972#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
973#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
974#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
975#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
976#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
977#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
978#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
979#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
980#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
981#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
982#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
983#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
984#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
985#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
986#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
987#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
988#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
989#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
990#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
991#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
992#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
993#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
994#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
995#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
996#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
997#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
998#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
999#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1000#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1001#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1002#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1003#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1004#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1005#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1006#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1007#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1008#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1009#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1010#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1011#define EMREN 0x10000000 /* Extended Mode Register Enable */
1012#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1013#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1014
1015/* EBIU_SDBCTL Masks */
1016#define EBE 0x0001 /* Enable SDRAM External Bank */
1017#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1018#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1019#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1020#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1021#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1022#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1023#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1024#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1025#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1026#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1027
1028/* EBIU_SDSTAT Masks */
1029#define SDCI 0x0001 /* SDRAM Controller Idle */
1030#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1031#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1032#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1033#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1034#define BGSTAT 0x0020 /* Bus Grant Status */
1035
1036
1037/* ************************** DMA CONTROLLER MASKS ********************************/
1038
1039/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1040#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1041#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1042#define PMAP_PPI 0x0000 /* PPI Port DMA */
1043#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1044#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1045#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1046#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1047#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1048#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1049#define PMAP_SPI 0x7000 /* SPI Port DMA */
1050#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1051#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1052#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1053#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1054
1055/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1056/* PPI_CONTROL Masks */
1057#define PORT_EN 0x0001 /* PPI Port Enable */
1058#define PORT_DIR 0x0002 /* PPI Port Direction */
1059#define XFR_TYPE 0x000C /* PPI Transfer Type */
1060#define PORT_CFG 0x0030 /* PPI Port Configuration */
1061#define FLD_SEL 0x0040 /* PPI Active Field Select */
1062#define PACK_EN 0x0080 /* PPI Packing Mode */
1063#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1064#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1065#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1066#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1067#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1068#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1069#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1070#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1071#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1072#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1073#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1074#define DLENGTH 0x3800 /* PPI Data Length */
1075#define POLC 0x4000 /* PPI Clock Polarity */
1076#define POLS 0x8000 /* PPI Frame Sync Polarity */
1077
1078/* PPI_STATUS Masks */
1079#define FLD 0x0400 /* Field Indicator */
1080#define FT_ERR 0x0800 /* Frame Track Error */
1081#define OVR 0x1000 /* FIFO Overflow Error */
1082#define UNDR 0x2000 /* FIFO Underrun Error */
1083#define ERR_DET 0x4000 /* Error Detected Indicator */
1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1085
1086
1087/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1088/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1089#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1090#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1091
1092/* TWI_PRESCALE Masks */
1093#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1094#define TWI_ENA 0x0080 /* TWI Enable */
1095#define SCCB 0x0200 /* SCCB Compatibility Enable */
1096
1097/* TWI_SLAVE_CTL Masks */
1098#define SEN 0x0001 /* Slave Enable */
1099#define SADD_LEN 0x0002 /* Slave Address Length */
1100#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1101#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1102#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1103
1104/* TWI_SLAVE_STAT Masks */
1105#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1106#define GCALL 0x0002 /* General Call Indicator */
1107
1108/* TWI_MASTER_CTL Masks */
1109#define MEN 0x0001 /* Master Mode Enable */
1110#define MADD_LEN 0x0002 /* Master Address Length */
1111#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1112#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1113#define STOP 0x0010 /* Issue Stop Condition */
1114#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1115#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1116#define SDAOVR 0x4000 /* Serial Data Override */
1117#define SCLOVR 0x8000 /* Serial Clock Override */
1118
1119/* TWI_MASTER_STAT Masks */
1120#define MPROG 0x0001 /* Master Transfer In Progress */
1121#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1122#define ANAK 0x0004 /* Address Not Acknowledged */
1123#define DNAK 0x0008 /* Data Not Acknowledged */
1124#define BUFRDERR 0x0010 /* Buffer Read Error */
1125#define BUFWRERR 0x0020 /* Buffer Write Error */
1126#define SDASEN 0x0040 /* Serial Data Sense */
1127#define SCLSEN 0x0080 /* Serial Clock Sense */
1128#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1129
1130/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1131#define SINIT 0x0001 /* Slave Transfer Initiated */
1132#define SCOMP 0x0002 /* Slave Transfer Complete */
1133#define SERR 0x0004 /* Slave Transfer Error */
1134#define SOVF 0x0008 /* Slave Overflow */
1135#define MCOMP 0x0010 /* Master Transfer Complete */
1136#define MERR 0x0020 /* Master Transfer Error */
1137#define XMTSERV 0x0040 /* Transmit FIFO Service */
1138#define RCVSERV 0x0080 /* Receive FIFO Service */
1139
1140/* TWI_FIFO_CTRL Masks */
1141#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1142#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1143#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1144#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1145
1146/* TWI_FIFO_STAT Masks */
1147#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1148#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1149#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1150#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1151
1152#define RCVSTAT 0x000C /* Receive FIFO Status */
1153#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1154#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1156
1157
1158/* Omit CAN masks from defBF534.h */
1159
1160/* ******************* PIN CONTROL REGISTER MASKS ************************/
1161/* PORT_MUX Masks */
1162#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1163#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1164#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1165
1166#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1167#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1168#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1169#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1170
1171#define PFDE 0x0008 /* Port F DMA Request Enable */
1172#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1173#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1174
1175#define PFTE 0x0010 /* Port F Timer Enable */
1176#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1177#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1178
1179#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1180#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1181#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1182
1183#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1184#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1185#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1186
1187#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1188#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1189#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1190
1191#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1192#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1193#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1194
1195#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1196#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1197#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1198
1199#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1200#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1201#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1202
1203#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1204#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1205#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1206
1207/* entry addresses of the user-callable Boot ROM functions */
1208
1209#define _BOOTROM_RESET 0xEF000000
1210#define _BOOTROM_FINAL_INIT 0xEF000002
1211#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1212#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1213#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1214#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1215#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1216#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1217#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1218
1219/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1220#define PGDE_UART PFDE_UART
1221#define PGDE_DMA PFDE_DMA
1222#define CKELOW SCKELOW
1223
1224/* ==== end from defBF534.h ==== */
1225
1226/* HOST Port Registers */
1227
1228#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1229#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1230#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1231
1232/* Counter Registers */
1233
1234#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1235#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1236#define CNT_STATUS 0xffc03508 /* Status Register */
1237#define CNT_COMMAND 0xffc0350c /* Command Register */
1238#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1239#define CNT_COUNTER 0xffc03514 /* Counter Register */
1240#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1241#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1242
1243/* OTP/FUSE Registers */
1244
1245#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1246#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1247#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1248#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1249
1250/* Security Registers */
1251
1252#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1253#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1254#define SECURE_STATUS 0xffc03628 /* Secure Status */
1255
1256/* OTP Read/Write Data Buffer Registers */
1257
1258#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1259#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1260#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1261#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1262
1263/* NFC Registers */
1264
1265#define NFC_CTL 0xffc03700 /* NAND Control Register */
1266#define NFC_STAT 0xffc03704 /* NAND Status Register */
1267#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1268#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1269#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1270#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1271#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1272#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1273#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1274#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1275#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1276#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1277#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1278#define NFC_CMD 0xffc03744 /* NAND Command Register */
1279#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1280#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1281
1282/* ********************************************************** */
1283/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1284/* and MULTI BIT READ MACROS */
1285/* ********************************************************** */
1286
1287/* Bit masks for HOST_CONTROL */
1288
1289#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1290#define HOST_CNTR_nHOST_EN 0x0
1291#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1292#define HOST_CNTR_nHOST_END 0x0
1293#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1294#define HOST_CNTR_nDATA_SIZE 0x0
1295#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1296#define HOST_CNTR_nHOST_RST 0x0
1297#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1298#define HOST_CNTR_nHRDY_OVR 0x0
1299#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1300#define HOST_CNTR_nINT_MODE 0x0
1301#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1302#define HOST_CNTR_ nBT_EN 0x0
1303#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1304#define HOST_CNTR_nEHW 0x0
1305#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1306#define HOST_CNTR_nEHR 0x0
1307#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1308#define HOST_CNTR_nBDR 0x0
1309
1310/* Bit masks for HOST_STATUS */
1311
1312#define HOST_STAT_READY 0x1 /* DMA Ready */
1313#define HOST_STAT_nREADY 0x0
1314#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1315#define HOST_STAT_nFIFOFULL 0x0
1316#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1317#define HOST_STAT_nFIFOEMPTY 0x0
1318#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1319#define HOST_STAT_nCOMPLETE 0x0
1320#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1321#define HOST_STAT_nHSHK 0x0
1322#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1323#define HOST_STAT_nTIMEOUT 0x0
1324#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1325#define HOST_STAT_nHIRQ 0x0
1326#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1327#define HOST_STAT_nALLOW_CNFG 0x0
1328#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1329#define HOST_STAT_nDMA_DIR 0x0
1330#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1331#define HOST_STAT_nBTE 0x0
1332#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1333#define HOST_STAT_nHOSTRD_DONE 0x0
1334
1335/* Bit masks for HOST_TIMEOUT */
1336
1337#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1338
1339/* Bit masks for SECURE_SYSSWT */
1340
1341#define EMUDABL 0x1 /* Emulation Disable. */
1342#define nEMUDABL 0x0
1343#define RSTDABL 0x2 /* Reset Disable */
1344#define nRSTDABL 0x0
1345#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1346#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1347#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1348#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1349#define nDMA0OVR 0x0
1350#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1351#define nDMA1OVR 0x0
1352#define EMUOVR 0x4000 /* Emulation Override */
1353#define nEMUOVR 0x0
1354#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1355#define nOTPSEN 0x0
1356#define L2DABL 0x70000 /* L2 Memory Disable. */
1357
1358/* Bit masks for SECURE_CONTROL */
1359
1360#define SECURE0 0x1 /* SECURE 0 */
1361#define nSECURE0 0x0
1362#define SECURE1 0x2 /* SECURE 1 */
1363#define nSECURE1 0x0
1364#define SECURE2 0x4 /* SECURE 2 */
1365#define nSECURE2 0x0
1366#define SECURE3 0x8 /* SECURE 3 */
1367#define nSECURE3 0x0
1368
1369/* Bit masks for SECURE_STATUS */
1370
1371#define SECMODE 0x3 /* Secured Mode Control State */
1372#define NMI 0x4 /* Non Maskable Interrupt */
1373#define nNMI 0x0
1374#define AFVALID 0x8 /* Authentication Firmware Valid */
1375#define nAFVALID 0x0
1376#define AFEXIT 0x10 /* Authentication Firmware Exit */
1377#define nAFEXIT 0x0
1378#define SECSTAT 0xe0 /* Secure Status */
17 1379
18#endif /* _DEF_BF522_H */ 1380#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index c136f7032962..aab80bb1a683 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -185,8 +185,8 @@
185#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ 185#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
186#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ 186#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
187#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ 187#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
188#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ 188#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
189#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ 189#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
190 190
191#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ 191#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
192 192
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 4dd58fb33156..05369a92fbc8 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
deleted file mode 100644
index 3e000756aacd..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ /dev/null
@@ -1,1551 +0,0 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF52X_H
8#define _DEF_BF52X_H
9
10
11/* ************************************************************** */
12/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
13/* ************************************************************** */
14
15/* ==== begin from defBF534.h ==== */
16
17/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
18#define PLL_CTL 0xFFC00000 /* PLL Control Register */
19#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
20#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
21#define PLL_STAT 0xFFC0000C /* PLL Status Register */
22#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
23#define CHIPID 0xFFC00014 /* Device ID Register */
24
25
26/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
27#define SWRST 0xFFC00100 /* Software Reset Register */
28#define SYSCR 0xFFC00104 /* System Configuration Register */
29#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
30
31#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
32#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
33#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
34#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
35#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
36#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
37#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
38
39/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
40#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
41#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
42#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
43#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
44#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
45#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
46#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
47
48
49/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
50#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
51#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
52#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
53
54
55/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
56#define RTC_STAT 0xFFC00300 /* RTC Status Register */
57#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
58#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
59#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
60#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
61#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
62#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
63
64
65/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
66#define UART0_THR 0xFFC00400 /* Transmit Holding register */
67#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
68#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
69#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
70#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
71#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
72#define UART0_LCR 0xFFC0040C /* Line Control Register */
73#define UART0_MCR 0xFFC00410 /* Modem Control Register */
74#define UART0_LSR 0xFFC00414 /* Line Status Register */
75#define UART0_MSR 0xFFC00418 /* Modem Status Register */
76#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
77#define UART0_GCTL 0xFFC00424 /* Global Control Register */
78
79
80/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
81#define SPI0_REGBASE 0xFFC00500
82#define SPI_CTL 0xFFC00500 /* SPI Control Register */
83#define SPI_FLG 0xFFC00504 /* SPI Flag register */
84#define SPI_STAT 0xFFC00508 /* SPI Status register */
85#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
86#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
87#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
88#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
89
90
91/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
92#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
93#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
94#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
95#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
96
97#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
98#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
99#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
100#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
101
102#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
103#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
104#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
105#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
106
107#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
108#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
109#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
110#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
111
112#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
113#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
114#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
115#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
116
117#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
118#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
119#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
120#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
121
122#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
123#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
124#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
125#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
126
127#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
128#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
129#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
130#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
131
132#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
133#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
134#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
135
136
137/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
138#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
139#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
140#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
141#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
142#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
143#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
144#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
145#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
146#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
147#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
148#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
149#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
150#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
151#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
152#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
153#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
154#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
155
156
157/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
158#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
159#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
160#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
161#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
162#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
163#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
164#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
165#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
166#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
167#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
168#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
169#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
170#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
171#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
172#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
173#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
174#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
175#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
176#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
177#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
178#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
179#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
180
181
182/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
183#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
184#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
185#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
186#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
187#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
188#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
189#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
190#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
191#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
192#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
193#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
194#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
195#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
196#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
197#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
198#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
199#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
200#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
201#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
202#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
203#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
204#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
205
206
207/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
208#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
209#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
210#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
211#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
212#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
213#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
214#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
215
216
217/* DMA Traffic Control Registers */
218#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
219#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
220
221/* Alternate deprecated register names (below) provided for backwards code compatibility */
222#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
223#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
224
225/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
227#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
228#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
229#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
230#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
231#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
233#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
234#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
235#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
236#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
237#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
238#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
239
240#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
241#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
242#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
243#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
244#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
245#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
247#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
248#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
249#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
250#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
251#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
252#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
253
254#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
255#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
256#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
257#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
258#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
259#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
261#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
262#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
263#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
264#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
265#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
266#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
267
268#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
269#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
270#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
271#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
272#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
273#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
275#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
276#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
277#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
278#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
279#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
280#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
281
282#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
283#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
284#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
285#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
286#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
287#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
289#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
290#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
291#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
292#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
293#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
294#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
295
296#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
297#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
298#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
299#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
300#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
301#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
303#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
304#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
305#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
306#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
307#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
308#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
309
310#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
311#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
312#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
313#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
314#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
315#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
317#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
318#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
319#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
320#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
321#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
322#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
323
324#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
325#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
326#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
327#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
328#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
329#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
331#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
332#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
333#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
334#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
335#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
336#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
337
338#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
339#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
340#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
341#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
342#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
343#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
344#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
345#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
346#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
347#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
348#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
349#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
350#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
351
352#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
353#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
354#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
355#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
356#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
357#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
358#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
359#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
360#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
361#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
362#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
363#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
364#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
365
366#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
367#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
368#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
369#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
370#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
371#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
372#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
373#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
374#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
375#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
376#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
377#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
378#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
379
380#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
381#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
382#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
383#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
384#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
385#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
386#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
387#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
388#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
389#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
390#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
391#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
392#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
393
394#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
395#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
396#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
397#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
398#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
399#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
400#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
401#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
402#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
403#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
404#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
405#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
406#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
407
408#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
409#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
410#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
411#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
412#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
413#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
414#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
415#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
416#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
417#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
418#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
419#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
420#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
421
422#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
423#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
424#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
425#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
426#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
427#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
428#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
429#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
430#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
431#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
432#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
433#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
434#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
435
436#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
437#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
438#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
439#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
440#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
441#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
442#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
443#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
444#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
445#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
446#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
447#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
448#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
449
450
451/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
452#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
453#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
454#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
455#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457
458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
461#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477
478
479/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
480#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
481#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
482#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
483#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
484#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
485#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
486#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
487#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
488#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
489#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
490#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
491#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
492#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
493#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
494#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
495#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
496#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
497
498
499/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
500#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
501#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
502#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
503#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
504#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
505#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
506#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
507#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
508#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
509#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
510#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
511#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
512#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
513#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
514#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
515#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
516#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
517
518
519/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
520#define UART1_THR 0xFFC02000 /* Transmit Holding register */
521#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
522#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
523#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
524#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
525#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
526#define UART1_LCR 0xFFC0200C /* Line Control Register */
527#define UART1_MCR 0xFFC02010 /* Modem Control Register */
528#define UART1_LSR 0xFFC02014 /* Line Status Register */
529#define UART1_MSR 0xFFC02018 /* Modem Status Register */
530#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
531#define UART1_GCTL 0xFFC02024 /* Global Control Register */
532
533
534/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
535
536/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
537#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
538#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
539#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
540#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
541
542
543/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
544#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
545#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
546#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
547#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
548#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
549#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
550#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
551
552#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
553#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
554#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
555#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
556#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
557#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
558#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
559
560/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
561#define PORTF_MUX 0xFFC03210 /* Port F mux control */
562#define PORTG_MUX 0xFFC03214 /* Port G mux control */
563#define PORTH_MUX 0xFFC03218 /* Port H mux control */
564#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
565#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
566#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
567#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
568#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
569#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
570#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
571#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
572#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
573#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
574#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
575#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
576
577
578/***********************************************************************************
579** System MMR Register Bits And Macros
580**
581** Disclaimer: All macros are intended to make C and Assembly code more readable.
582** Use these macros carefully, as any that do left shifts for field
583** depositing will result in the lower order bits being destroyed. Any
584** macro that shifts left to properly position the bit-field should be
585** used as part of an OR to initialize a register and NOT as a dynamic
586** modifier UNLESS the lower order bits are saved and ORed back in when
587** the macro is used.
588*************************************************************************************/
589
590/* CHIPID Masks */
591#define CHIPID_VERSION 0xF0000000
592#define CHIPID_FAMILY 0x0FFFF000
593#define CHIPID_MANUFACTURE 0x00000FFE
594
595/* SWRST Masks */
596#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
597#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
598#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
599#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
600#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
601
602/* SYSCR Masks */
603#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
604#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
605
606
607/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
608/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
609
610#if 0
611#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
612
613#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
614#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
615#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
616#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
617#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
618#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
619#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
620
621#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
622#define IRQ_TWI 0x00000200 /* TWI Interrupt */
623#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
624#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
625#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
626#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
627#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
628#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
629
630#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
631#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
632#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
633#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
634#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
635#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
636#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
637#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
638#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
639#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
640
641#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
642#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
643#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
644#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
645#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
646#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
647#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
648#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
649#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
650#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
651#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
652#endif
653
654/* SIC_IAR0 Macros */
655#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
656#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
657#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
658#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
659#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
660#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
661#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
662#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
663
664/* SIC_IAR1 Macros */
665#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
666#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
667#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
668#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
669#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
670#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
671#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
672#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
673
674/* SIC_IAR2 Macros */
675#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
676#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
677#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
678#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
679#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
680#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
681#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
682#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
683
684/* SIC_IAR3 Macros */
685#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
686#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
687#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
688#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
689#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
690#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
691#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
692#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
693
694
695/* SIC_IMASK Masks */
696#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
697#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
698#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
699#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
700
701/* SIC_IWR Masks */
702#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
703#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
704#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
705#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
706
707
708/* ************** UART CONTROLLER MASKS *************************/
709/* UARTx_LCR Masks */
710#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
711#define STB 0x04 /* Stop Bits */
712#define PEN 0x08 /* Parity Enable */
713#define EPS 0x10 /* Even Parity Select */
714#define STP 0x20 /* Stick Parity */
715#define SB 0x40 /* Set Break */
716#define DLAB 0x80 /* Divisor Latch Access */
717
718/* UARTx_MCR Mask */
719#define LOOP_ENA 0x10 /* Loopback Mode Enable */
720#define LOOP_ENA_P 0x04
721
722/* UARTx_LSR Masks */
723#define DR 0x01 /* Data Ready */
724#define OE 0x02 /* Overrun Error */
725#define PE 0x04 /* Parity Error */
726#define FE 0x08 /* Framing Error */
727#define BI 0x10 /* Break Interrupt */
728#define THRE 0x20 /* THR Empty */
729#define TEMT 0x40 /* TSR and UART_THR Empty */
730
731/* UARTx_IER Masks */
732#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
733#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
734#define ELSI 0x04 /* Enable RX Status Interrupt */
735
736/* UARTx_IIR Masks */
737#define NINT 0x01 /* Pending Interrupt */
738#define IIR_TX_READY 0x02 /* UART_THR empty */
739#define IIR_RX_READY 0x04 /* Receive data ready */
740#define IIR_LINE_CHANGE 0x06 /* Receive line status */
741#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
742
743/* UARTx_GCTL Masks */
744#define UCEN 0x01 /* Enable UARTx Clocks */
745#define IREN 0x02 /* Enable IrDA Mode */
746#define TPOLC 0x04 /* IrDA TX Polarity Change */
747#define RPOLC 0x08 /* IrDA RX Polarity Change */
748#define FPE 0x10 /* Force Parity Error On Transmit */
749#define FFE 0x20 /* Force Framing Error On Transmit */
750
751
752/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
753/* SPI_CTL Masks */
754#define TIMOD 0x0003 /* Transfer Initiate Mode */
755#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
756#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
757#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
758#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
759#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
760#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
761#define PSSE 0x0010 /* Slave-Select Input Enable */
762#define EMISO 0x0020 /* Enable MISO As Output */
763#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
764#define LSBF 0x0200 /* LSB First */
765#define CPHA 0x0400 /* Clock Phase */
766#define CPOL 0x0800 /* Clock Polarity */
767#define MSTR 0x1000 /* Master/Slave* */
768#define WOM 0x2000 /* Write Open Drain Master */
769#define SPE 0x4000 /* SPI Enable */
770
771/* SPI_FLG Masks */
772#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
773#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
774#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
775#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
776#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
777#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
778#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
779#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
780#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
781#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
782#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
783#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
784#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
785#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
786
787/* SPI_STAT Masks */
788#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
789#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
790#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
791#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
792#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
793#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
794#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
795
796
797/* **************** GENERAL PURPOSE TIMER MASKS **********************/
798/* TIMER_ENABLE Masks */
799#define TIMEN0 0x0001 /* Enable Timer 0 */
800#define TIMEN1 0x0002 /* Enable Timer 1 */
801#define TIMEN2 0x0004 /* Enable Timer 2 */
802#define TIMEN3 0x0008 /* Enable Timer 3 */
803#define TIMEN4 0x0010 /* Enable Timer 4 */
804#define TIMEN5 0x0020 /* Enable Timer 5 */
805#define TIMEN6 0x0040 /* Enable Timer 6 */
806#define TIMEN7 0x0080 /* Enable Timer 7 */
807
808/* TIMER_DISABLE Masks */
809#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
810#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
811#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
812#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
813#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
814#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
815#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
816#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
817
818/* TIMER_STATUS Masks */
819#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
820#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
821#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
822#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
823#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
824#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
825#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
826#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
827#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
828#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
829#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
830#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
831#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
832#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
833#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
834#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
835#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
836#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
837#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
838#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
839#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
840#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
841#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
842#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
843
844/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
845#define TOVL_ERR0 TOVF_ERR0
846#define TOVL_ERR1 TOVF_ERR1
847#define TOVL_ERR2 TOVF_ERR2
848#define TOVL_ERR3 TOVF_ERR3
849#define TOVL_ERR4 TOVF_ERR4
850#define TOVL_ERR5 TOVF_ERR5
851#define TOVL_ERR6 TOVF_ERR6
852#define TOVL_ERR7 TOVF_ERR7
853
854/* TIMERx_CONFIG Masks */
855#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
856#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
857#define EXT_CLK 0x0003 /* External Clock Mode */
858#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
859#define PERIOD_CNT 0x0008 /* Period Count */
860#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
861#define TIN_SEL 0x0020 /* Timer Input Select */
862#define OUT_DIS 0x0040 /* Output Pad Disable */
863#define CLK_SEL 0x0080 /* Timer Clock Select */
864#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
865#define EMU_RUN 0x0200 /* Emulation Behavior Select */
866#define ERR_TYP 0xC000 /* Error Type */
867
868
869/* ****************** GPIO PORTS F, G, H MASKS ***********************/
870/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
871/* Port F Masks */
872#define PF0 0x0001
873#define PF1 0x0002
874#define PF2 0x0004
875#define PF3 0x0008
876#define PF4 0x0010
877#define PF5 0x0020
878#define PF6 0x0040
879#define PF7 0x0080
880#define PF8 0x0100
881#define PF9 0x0200
882#define PF10 0x0400
883#define PF11 0x0800
884#define PF12 0x1000
885#define PF13 0x2000
886#define PF14 0x4000
887#define PF15 0x8000
888
889/* Port G Masks */
890#define PG0 0x0001
891#define PG1 0x0002
892#define PG2 0x0004
893#define PG3 0x0008
894#define PG4 0x0010
895#define PG5 0x0020
896#define PG6 0x0040
897#define PG7 0x0080
898#define PG8 0x0100
899#define PG9 0x0200
900#define PG10 0x0400
901#define PG11 0x0800
902#define PG12 0x1000
903#define PG13 0x2000
904#define PG14 0x4000
905#define PG15 0x8000
906
907/* Port H Masks */
908#define PH0 0x0001
909#define PH1 0x0002
910#define PH2 0x0004
911#define PH3 0x0008
912#define PH4 0x0010
913#define PH5 0x0020
914#define PH6 0x0040
915#define PH7 0x0080
916#define PH8 0x0100
917#define PH9 0x0200
918#define PH10 0x0400
919#define PH11 0x0800
920#define PH12 0x1000
921#define PH13 0x2000
922#define PH14 0x4000
923#define PH15 0x8000
924
925/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
926/* EBIU_AMGCTL Masks */
927#define AMCKEN 0x0001 /* Enable CLKOUT */
928#define AMBEN_NONE 0x0000 /* All Banks Disabled */
929#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
930#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
931#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
932#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
933
934/* EBIU_AMBCTL0 Masks */
935#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
936#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
937#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
938#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
939#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
940#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
941#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
942#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
943#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
944#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
945#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
946#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
947#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
948#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
949#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
950#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
951#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
952#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
953#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
954#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
955#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
956#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
957#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
958#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
959#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
960#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
961#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
962#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
963#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
964#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
965#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
966#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
967#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
968#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
969#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
970#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
971#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
972#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
973#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
974#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
975#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
976#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
977#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
978#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
979
980#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
981#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
982#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
983#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
984#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
985#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
986#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
987#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
988#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
989#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
990#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
991#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
992#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
993#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
994#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
995#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
996#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
997#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
998#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
999#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1000#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1001#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1002#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1003#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1004#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1005#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1006#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1007#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1008#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1009#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1010#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1011#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1012#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1013#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1014#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1015#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1016#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1017#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1018#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1019#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1020#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1021#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1022#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1023#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1024
1025/* EBIU_AMBCTL1 Masks */
1026#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1027#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1028#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1029#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1030#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1031#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1032#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1033#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1034#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1035#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1036#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1037#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1038#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1039#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1040#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1041#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1042#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1043#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1044#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1045#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1046#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1047#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1048#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1049#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1050#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1051#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1052#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1053#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1054#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1055#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1056#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1057#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1058#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1059#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1060#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1061#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1062#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1063#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1064#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1065#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1066#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1067#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1068#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1069#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1070
1071#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1072#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1073#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1074#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1075#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1076#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1077#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1078#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1079#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1080#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1081#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1082#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1083#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1084#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1085#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1086#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1087#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1088#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1089#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1090#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1091#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1092#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1093#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1094#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1095#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1096#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1097#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1098#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1099#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1100#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1101#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1102#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1103#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1104#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1105#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1106#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1107#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1108#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1109#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1110#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1111#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1112#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1113#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1114#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1115
1116
1117/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1118/* EBIU_SDGCTL Masks */
1119#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1120#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1121#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1122#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1123#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1124#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1125#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1126#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1127#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1128#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1129#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1130#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1131#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1132#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1133#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1134#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1135#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1136#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1137#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1138#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1139#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1140#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1141#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1142#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1143#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1144#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1145#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1146#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1147#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1148#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1149#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1150#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1151#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1152#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1153#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1154#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1155#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1156#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1157#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1158#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1159#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1160#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1161#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1162#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1163#define EMREN 0x10000000 /* Extended Mode Register Enable */
1164#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1165#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1166
1167/* EBIU_SDBCTL Masks */
1168#define EBE 0x0001 /* Enable SDRAM External Bank */
1169#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1170#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1171#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1172#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1173#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1174#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1175#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1176#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1177#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1178#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1179
1180/* EBIU_SDSTAT Masks */
1181#define SDCI 0x0001 /* SDRAM Controller Idle */
1182#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1183#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1184#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1185#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1186#define BGSTAT 0x0020 /* Bus Grant Status */
1187
1188
1189/* ************************** DMA CONTROLLER MASKS ********************************/
1190
1191/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1192#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1193#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1194#define PMAP_PPI 0x0000 /* PPI Port DMA */
1195#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1196#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1197#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1198#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1199#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1200#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1201#define PMAP_SPI 0x7000 /* SPI Port DMA */
1202#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1203#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1204#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1205#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1206
1207/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1208/* PPI_CONTROL Masks */
1209#define PORT_EN 0x0001 /* PPI Port Enable */
1210#define PORT_DIR 0x0002 /* PPI Port Direction */
1211#define XFR_TYPE 0x000C /* PPI Transfer Type */
1212#define PORT_CFG 0x0030 /* PPI Port Configuration */
1213#define FLD_SEL 0x0040 /* PPI Active Field Select */
1214#define PACK_EN 0x0080 /* PPI Packing Mode */
1215#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1216#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1217#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1218#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1219#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1220#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1221#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1222#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1223#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1224#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1225#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1226#define DLENGTH 0x3800 /* PPI Data Length */
1227#define POLC 0x4000 /* PPI Clock Polarity */
1228#define POLS 0x8000 /* PPI Frame Sync Polarity */
1229
1230/* PPI_STATUS Masks */
1231#define FLD 0x0400 /* Field Indicator */
1232#define FT_ERR 0x0800 /* Frame Track Error */
1233#define OVR 0x1000 /* FIFO Overflow Error */
1234#define UNDR 0x2000 /* FIFO Underrun Error */
1235#define ERR_DET 0x4000 /* Error Detected Indicator */
1236#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1237
1238
1239/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1240/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1241#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1242#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1243
1244/* TWI_PRESCALE Masks */
1245#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1246#define TWI_ENA 0x0080 /* TWI Enable */
1247#define SCCB 0x0200 /* SCCB Compatibility Enable */
1248
1249/* TWI_SLAVE_CTL Masks */
1250#define SEN 0x0001 /* Slave Enable */
1251#define SADD_LEN 0x0002 /* Slave Address Length */
1252#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1253#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1254#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1255
1256/* TWI_SLAVE_STAT Masks */
1257#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1258#define GCALL 0x0002 /* General Call Indicator */
1259
1260/* TWI_MASTER_CTL Masks */
1261#define MEN 0x0001 /* Master Mode Enable */
1262#define MADD_LEN 0x0002 /* Master Address Length */
1263#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1264#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1265#define STOP 0x0010 /* Issue Stop Condition */
1266#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1267#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1268#define SDAOVR 0x4000 /* Serial Data Override */
1269#define SCLOVR 0x8000 /* Serial Clock Override */
1270
1271/* TWI_MASTER_STAT Masks */
1272#define MPROG 0x0001 /* Master Transfer In Progress */
1273#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1274#define ANAK 0x0004 /* Address Not Acknowledged */
1275#define DNAK 0x0008 /* Data Not Acknowledged */
1276#define BUFRDERR 0x0010 /* Buffer Read Error */
1277#define BUFWRERR 0x0020 /* Buffer Write Error */
1278#define SDASEN 0x0040 /* Serial Data Sense */
1279#define SCLSEN 0x0080 /* Serial Clock Sense */
1280#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1281
1282/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1283#define SINIT 0x0001 /* Slave Transfer Initiated */
1284#define SCOMP 0x0002 /* Slave Transfer Complete */
1285#define SERR 0x0004 /* Slave Transfer Error */
1286#define SOVF 0x0008 /* Slave Overflow */
1287#define MCOMP 0x0010 /* Master Transfer Complete */
1288#define MERR 0x0020 /* Master Transfer Error */
1289#define XMTSERV 0x0040 /* Transmit FIFO Service */
1290#define RCVSERV 0x0080 /* Receive FIFO Service */
1291
1292/* TWI_FIFO_CTRL Masks */
1293#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1294#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1295#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1296#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1297
1298/* TWI_FIFO_STAT Masks */
1299#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1300#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1301#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1302#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1303
1304#define RCVSTAT 0x000C /* Receive FIFO Status */
1305#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1306#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1307#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1308
1309
1310/* Omit CAN masks from defBF534.h */
1311
1312/* ******************* PIN CONTROL REGISTER MASKS ************************/
1313/* PORT_MUX Masks */
1314#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1315#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1316#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1317
1318#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1319#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1320#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1321#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1322
1323#define PFDE 0x0008 /* Port F DMA Request Enable */
1324#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1325#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1326
1327#define PFTE 0x0010 /* Port F Timer Enable */
1328#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1329#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1330
1331#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1332#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1333#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1334
1335#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1336#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1337#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1338
1339#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1340#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1341#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1342
1343#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1344#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1345#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1346
1347#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1348#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1349#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1350
1351#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1352#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1353#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1354
1355#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1356#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1357#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1358
1359
1360/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1361/* HDMAx_CTL Masks */
1362#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1363#define REP 0x0002 /* HDMA Request Polarity */
1364#define UTE 0x0004 /* Urgency Threshold Enable */
1365#define OIE 0x0010 /* Overflow Interrupt Enable */
1366#define BDIE 0x0020 /* Block Done Interrupt Enable */
1367#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1368#define DRQ 0x0300 /* HDMA Request Type */
1369#define DRQ_NONE 0x0000 /* No Request */
1370#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1371#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1372#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1373#define RBC 0x1000 /* Reload BCNT With IBCNT */
1374#define PS 0x2000 /* HDMA Pin Status */
1375#define OI 0x4000 /* Overflow Interrupt Generated */
1376#define BDI 0x8000 /* Block Done Interrupt Generated */
1377
1378/* entry addresses of the user-callable Boot ROM functions */
1379
1380#define _BOOTROM_RESET 0xEF000000
1381#define _BOOTROM_FINAL_INIT 0xEF000002
1382#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1383#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1384#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1385#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1386#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1387#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1388#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1389
1390/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1391#define PGDE_UART PFDE_UART
1392#define PGDE_DMA PFDE_DMA
1393#define CKELOW SCKELOW
1394
1395/* ==== end from defBF534.h ==== */
1396
1397/* HOST Port Registers */
1398
1399#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1400#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1401#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1402
1403/* Counter Registers */
1404
1405#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1406#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1407#define CNT_STATUS 0xffc03508 /* Status Register */
1408#define CNT_COMMAND 0xffc0350c /* Command Register */
1409#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1410#define CNT_COUNTER 0xffc03514 /* Counter Register */
1411#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1412#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1413
1414/* OTP/FUSE Registers */
1415
1416#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1417#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1418#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1419#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1420
1421/* Security Registers */
1422
1423#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1424#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1425#define SECURE_STATUS 0xffc03628 /* Secure Status */
1426
1427/* OTP Read/Write Data Buffer Registers */
1428
1429#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1430#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1431#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1432#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1433
1434/* NFC Registers */
1435
1436#define NFC_CTL 0xffc03700 /* NAND Control Register */
1437#define NFC_STAT 0xffc03704 /* NAND Status Register */
1438#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1439#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1440#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1441#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1442#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1443#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1444#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1445#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1446#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1447#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1448#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1449#define NFC_CMD 0xffc03744 /* NAND Command Register */
1450#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1451#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1452
1453/* ********************************************************** */
1454/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1455/* and MULTI BIT READ MACROS */
1456/* ********************************************************** */
1457
1458/* Bit masks for HOST_CONTROL */
1459
1460#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1461#define HOST_CNTR_nHOST_EN 0x0
1462#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1463#define HOST_CNTR_nHOST_END 0x0
1464#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1465#define HOST_CNTR_nDATA_SIZE 0x0
1466#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1467#define HOST_CNTR_nHOST_RST 0x0
1468#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1469#define HOST_CNTR_nHRDY_OVR 0x0
1470#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1471#define HOST_CNTR_nINT_MODE 0x0
1472#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1473#define HOST_CNTR_ nBT_EN 0x0
1474#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1475#define HOST_CNTR_nEHW 0x0
1476#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1477#define HOST_CNTR_nEHR 0x0
1478#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1479#define HOST_CNTR_nBDR 0x0
1480
1481/* Bit masks for HOST_STATUS */
1482
1483#define HOST_STAT_READY 0x1 /* DMA Ready */
1484#define HOST_STAT_nREADY 0x0
1485#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1486#define HOST_STAT_nFIFOFULL 0x0
1487#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1488#define HOST_STAT_nFIFOEMPTY 0x0
1489#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1490#define HOST_STAT_nCOMPLETE 0x0
1491#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1492#define HOST_STAT_nHSHK 0x0
1493#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1494#define HOST_STAT_nTIMEOUT 0x0
1495#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1496#define HOST_STAT_nHIRQ 0x0
1497#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1498#define HOST_STAT_nALLOW_CNFG 0x0
1499#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1500#define HOST_STAT_nDMA_DIR 0x0
1501#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1502#define HOST_STAT_nBTE 0x0
1503#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1504#define HOST_STAT_nHOSTRD_DONE 0x0
1505
1506/* Bit masks for HOST_TIMEOUT */
1507
1508#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1509
1510/* Bit masks for SECURE_SYSSWT */
1511
1512#define EMUDABL 0x1 /* Emulation Disable. */
1513#define nEMUDABL 0x0
1514#define RSTDABL 0x2 /* Reset Disable */
1515#define nRSTDABL 0x0
1516#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1517#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1518#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1519#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1520#define nDMA0OVR 0x0
1521#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1522#define nDMA1OVR 0x0
1523#define EMUOVR 0x4000 /* Emulation Override */
1524#define nEMUOVR 0x0
1525#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1526#define nOTPSEN 0x0
1527#define L2DABL 0x70000 /* L2 Memory Disable. */
1528
1529/* Bit masks for SECURE_CONTROL */
1530
1531#define SECURE0 0x1 /* SECURE 0 */
1532#define nSECURE0 0x0
1533#define SECURE1 0x2 /* SECURE 1 */
1534#define nSECURE1 0x0
1535#define SECURE2 0x4 /* SECURE 2 */
1536#define nSECURE2 0x0
1537#define SECURE3 0x8 /* SECURE 3 */
1538#define nSECURE3 0x0
1539
1540/* Bit masks for SECURE_STATUS */
1541
1542#define SECMODE 0x3 /* Secured Mode Control State */
1543#define NMI 0x4 /* Non Maskable Interrupt */
1544#define nNMI 0x0
1545#define AFVALID 0x8 /* Authentication Firmware Valid */
1546#define nAFVALID 0x0
1547#define AFEXIT 0x10 /* Authentication Firmware Exit */
1548#define nAFEXIT 0x0
1549#define SECSTAT 0xe0 /* Secure Status */
1550
1551#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d9253e41d..ed7310ff819b 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,38 +7,9 @@
7#ifndef _BF527_IRQ_H_ 7#ifndef _BF527_IRQ_H_
8#define _BF527_IRQ_H_ 8#define _BF527_IRQ_H_
9 9
10/* 10#include <mach-common/irq.h>
11 * Interrupt source definitions 11
12 Event Source Core Event Name 12#define NR_PERI_INTS (2 * 32)
13 Core Emulation **
14 Events (highest priority) EMU 0
15 Reset RST 1
16 NMI NMI 2
17 Exception EVX 3
18 Reserved -- 4
19 Hardware Error IVHW 5
20 Core Timer IVTMR 6 *
21
22 .....
23
24 Software Interrupt 1 IVG14 31
25 Software Interrupt 2 --
26 (lowest priority) IVG15 32 *
27*/
28
29#define NR_PERI_INTS (2 * 32)
30
31/* The ABSTRACT IRQ definitions */
32/** the first seven of the following are fixed, the rest you change if you need to **/
33#define IRQ_EMU 0 /* Emulation */
34#define IRQ_RST 1 /* reset */
35#define IRQ_NMI 2 /* Non Maskable */
36#define IRQ_EVX 3 /* Exception */
37#define IRQ_UNUSED 4 /* - unused interrupt */
38#define IRQ_HWERR 5 /* Hardware Error */
39#define IRQ_CORETMR 6 /* Core timer */
40
41#define BFIN_IRQ(x) ((x) + 7)
42 13
43#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -53,21 +24,21 @@
53#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 24#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
54#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 25#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
55#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 26#define IRQ_RTC BFIN_IRQ(14) /* RTC */
56#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ 27#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
57#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 28#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
58#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 29#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
59#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ 30#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
60#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 31#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
61#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 32#define IRQ_TWI BFIN_IRQ(20) /* TWI */
62#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ 33#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
63#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 34#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
64#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 35#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
65#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 36#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
66#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 37#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
67#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 38#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
68#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 39#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
69#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ 40#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
70#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 41#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
71#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 42#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
72#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 43#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
73#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 44#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
@@ -96,119 +67,108 @@
96#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ 67#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
97#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ 68#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
98 69
99#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
100 71
101#define IRQ_PF0 71 72#define IRQ_PF0 71
102#define IRQ_PF1 72 73#define IRQ_PF1 72
103#define IRQ_PF2 73 74#define IRQ_PF2 73
104#define IRQ_PF3 74 75#define IRQ_PF3 74
105#define IRQ_PF4 75 76#define IRQ_PF4 75
106#define IRQ_PF5 76 77#define IRQ_PF5 76
107#define IRQ_PF6 77 78#define IRQ_PF6 77
108#define IRQ_PF7 78 79#define IRQ_PF7 78
109#define IRQ_PF8 79 80#define IRQ_PF8 79
110#define IRQ_PF9 80 81#define IRQ_PF9 80
111#define IRQ_PF10 81 82#define IRQ_PF10 81
112#define IRQ_PF11 82 83#define IRQ_PF11 82
113#define IRQ_PF12 83 84#define IRQ_PF12 83
114#define IRQ_PF13 84 85#define IRQ_PF13 84
115#define IRQ_PF14 85 86#define IRQ_PF14 85
116#define IRQ_PF15 86 87#define IRQ_PF15 86
117 88
118#define IRQ_PG0 87 89#define IRQ_PG0 87
119#define IRQ_PG1 88 90#define IRQ_PG1 88
120#define IRQ_PG2 89 91#define IRQ_PG2 89
121#define IRQ_PG3 90 92#define IRQ_PG3 90
122#define IRQ_PG4 91 93#define IRQ_PG4 91
123#define IRQ_PG5 92 94#define IRQ_PG5 92
124#define IRQ_PG6 93 95#define IRQ_PG6 93
125#define IRQ_PG7 94 96#define IRQ_PG7 94
126#define IRQ_PG8 95 97#define IRQ_PG8 95
127#define IRQ_PG9 96 98#define IRQ_PG9 96
128#define IRQ_PG10 97 99#define IRQ_PG10 97
129#define IRQ_PG11 98 100#define IRQ_PG11 98
130#define IRQ_PG12 99 101#define IRQ_PG12 99
131#define IRQ_PG13 100 102#define IRQ_PG13 100
132#define IRQ_PG14 101 103#define IRQ_PG14 101
133#define IRQ_PG15 102 104#define IRQ_PG15 102
134 105
135#define IRQ_PH0 103 106#define IRQ_PH0 103
136#define IRQ_PH1 104 107#define IRQ_PH1 104
137#define IRQ_PH2 105 108#define IRQ_PH2 105
138#define IRQ_PH3 106 109#define IRQ_PH3 106
139#define IRQ_PH4 107 110#define IRQ_PH4 107
140#define IRQ_PH5 108 111#define IRQ_PH5 108
141#define IRQ_PH6 109 112#define IRQ_PH6 109
142#define IRQ_PH7 110 113#define IRQ_PH7 110
143#define IRQ_PH8 111 114#define IRQ_PH8 111
144#define IRQ_PH9 112 115#define IRQ_PH9 112
145#define IRQ_PH10 113 116#define IRQ_PH10 113
146#define IRQ_PH11 114 117#define IRQ_PH11 114
147#define IRQ_PH12 115 118#define IRQ_PH12 115
148#define IRQ_PH13 116 119#define IRQ_PH13 116
149#define IRQ_PH14 117 120#define IRQ_PH14 117
150#define IRQ_PH15 118 121#define IRQ_PH15 118
151 122
152#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
153 124
154#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
155#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
156#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
157#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
158#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
159#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
160#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
161#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162 133
163#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166#define IVG7 7
167#define IVG8 8
168#define IVG9 9
169#define IVG10 10
170#define IVG11 11
171#define IVG12 12
172#define IVG13 13
173#define IVG14 14
174#define IVG15 15
175 135
176/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
177#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
178#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
179#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
180#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
181#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
182#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
183#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
184#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
185 145
186/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
187#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
188#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
189#define IRQ_UART0_ERROR_POS 16 149#define IRQ_UART0_ERROR_POS 16
190#define IRQ_UART1_ERROR_POS 20 150#define IRQ_UART1_ERROR_POS 20
191#define IRQ_RTC_POS 24 151#define IRQ_RTC_POS 24
192#define IRQ_PPI_POS 28 152#define IRQ_PPI_POS 28
193 153
194/* IAR2 BIT FIELDS */ 154/* IAR2 BIT FIELDS */
195#define IRQ_SPORT0_RX_POS 0 155#define IRQ_SPORT0_RX_POS 0
196#define IRQ_SPORT0_TX_POS 4 156#define IRQ_SPORT0_TX_POS 4
197#define IRQ_SPORT1_RX_POS 8 157#define IRQ_SPORT1_RX_POS 8
198#define IRQ_SPORT1_TX_POS 12 158#define IRQ_SPORT1_TX_POS 12
199#define IRQ_TWI_POS 16 159#define IRQ_TWI_POS 16
200#define IRQ_SPI_POS 20 160#define IRQ_SPI_POS 20
201#define IRQ_UART0_RX_POS 24 161#define IRQ_UART0_RX_POS 24
202#define IRQ_UART0_TX_POS 28 162#define IRQ_UART0_TX_POS 28
203 163
204/* IAR3 BIT FIELDS */ 164/* IAR3 BIT FIELDS */
205#define IRQ_UART1_RX_POS 0 165#define IRQ_UART1_RX_POS 0
206#define IRQ_UART1_TX_POS 4 166#define IRQ_UART1_TX_POS 4
207#define IRQ_OPTSEC_POS 8 167#define IRQ_OPTSEC_POS 8
208#define IRQ_CNT_POS 12 168#define IRQ_CNT_POS 12
209#define IRQ_MAC_RX_POS 16 169#define IRQ_MAC_RX_POS 16
210#define IRQ_PORTH_INTA_POS 20 170#define IRQ_PORTH_INTA_POS 20
211#define IRQ_MAC_TX_POS 24 171#define IRQ_MAC_TX_POS 24
212#define IRQ_PORTH_INTB_POS 28 172#define IRQ_PORTH_INTB_POS 28
213 173
214/* IAR4 BIT FIELDS */ 174/* IAR4 BIT FIELDS */
@@ -224,21 +184,21 @@
224/* IAR5 BIT FIELDS */ 184/* IAR5 BIT FIELDS */
225#define IRQ_PORTG_INTA_POS 0 185#define IRQ_PORTG_INTA_POS 0
226#define IRQ_PORTG_INTB_POS 4 186#define IRQ_PORTG_INTB_POS 4
227#define IRQ_MEM_DMA0_POS 8 187#define IRQ_MEM_DMA0_POS 8
228#define IRQ_MEM_DMA1_POS 12 188#define IRQ_MEM_DMA1_POS 12
229#define IRQ_WATCH_POS 16 189#define IRQ_WATCH_POS 16
230#define IRQ_PORTF_INTA_POS 20 190#define IRQ_PORTF_INTA_POS 20
231#define IRQ_PORTF_INTB_POS 24 191#define IRQ_PORTF_INTB_POS 24
232#define IRQ_SPI_ERROR_POS 28 192#define IRQ_SPI_ERROR_POS 28
233 193
234/* IAR6 BIT FIELDS */ 194/* IAR6 BIT FIELDS */
235#define IRQ_NFC_ERROR_POS 0 195#define IRQ_NFC_ERROR_POS 0
236#define IRQ_HDMA_ERROR_POS 4 196#define IRQ_HDMA_ERROR_POS 4
237#define IRQ_HDMA_POS 8 197#define IRQ_HDMA_POS 8
238#define IRQ_USB_EINT_POS 12 198#define IRQ_USB_EINT_POS 12
239#define IRQ_USB_INT0_POS 16 199#define IRQ_USB_INT0_POS 16
240#define IRQ_USB_INT1_POS 20 200#define IRQ_USB_INT1_POS 20
241#define IRQ_USB_INT2_POS 24 201#define IRQ_USB_INT2_POS 24
242#define IRQ_USB_DMA_POS 28 202#define IRQ_USB_DMA_POS 28
243 203
244#endif /* _BF527_IRQ_H_ */ 204#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
new file mode 100644
index 000000000000..94cca674d835
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -0,0 +1 @@
#include <mach-common/pll.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 19:47:44 -0400