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authorMike Frysinger <vapier@gentoo.org>2009-06-13 06:37:14 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-22 21:15:38 -0400
commita200ad22bb15fe01cf222fa631687876baad5e01 (patch)
treedd7c7e85a7ea56ff9a694348a68f66bb2d8a7c92 /arch/blackfin/mach-bf527/include
parent4d5e6fd42c137dad3b1aced073c6fcb494a8e507 (diff)
Blackfin: update anomaly lists
Update anomaly headers to match latest released anomaly sheets. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf527/include')
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index c84ddea95749..0d63f7406168 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -34,7 +34,7 @@
34#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) 34#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
35#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) 35#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
36 36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
38#define ANOMALY_05000074 (1) 38#define ANOMALY_05000074 (1)
39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
40#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 40#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
@@ -184,8 +184,12 @@
184#define ANOMALY_05000456 (1) 184#define ANOMALY_05000456 (1)
185/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 185/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
186#define ANOMALY_05000457 (1) 186#define ANOMALY_05000457 (1)
187/* False Hardware Error when RETI points to invalid memory */ 187/* False Hardware Error when RETI Points to Invalid Memory */
188#define ANOMALY_05000461 (1) 188#define ANOMALY_05000461 (1)
189/* USB Rx DMA hang */
190#define ANOMALY_05000465 (1)
191/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
192#define ANOMALY_05000467 (1)
189 193
190/* Anomalies that don't exist on this proc */ 194/* Anomalies that don't exist on this proc */
191#define ANOMALY_05000099 (0) 195#define ANOMALY_05000099 (0)
@@ -195,24 +199,30 @@
195#define ANOMALY_05000158 (0) 199#define ANOMALY_05000158 (0)
196#define ANOMALY_05000171 (0) 200#define ANOMALY_05000171 (0)
197#define ANOMALY_05000179 (0) 201#define ANOMALY_05000179 (0)
202#define ANOMALY_05000182 (0)
198#define ANOMALY_05000183 (0) 203#define ANOMALY_05000183 (0)
199#define ANOMALY_05000198 (0) 204#define ANOMALY_05000198 (0)
205#define ANOMALY_05000202 (0)
200#define ANOMALY_05000215 (0) 206#define ANOMALY_05000215 (0)
201#define ANOMALY_05000220 (0) 207#define ANOMALY_05000220 (0)
202#define ANOMALY_05000227 (0) 208#define ANOMALY_05000227 (0)
203#define ANOMALY_05000230 (0) 209#define ANOMALY_05000230 (0)
204#define ANOMALY_05000231 (0) 210#define ANOMALY_05000231 (0)
205#define ANOMALY_05000233 (0) 211#define ANOMALY_05000233 (0)
212#define ANOMALY_05000234 (0)
206#define ANOMALY_05000242 (0) 213#define ANOMALY_05000242 (0)
207#define ANOMALY_05000244 (0) 214#define ANOMALY_05000244 (0)
208#define ANOMALY_05000248 (0) 215#define ANOMALY_05000248 (0)
209#define ANOMALY_05000250 (0) 216#define ANOMALY_05000250 (0)
217#define ANOMALY_05000257 (0)
210#define ANOMALY_05000261 (0) 218#define ANOMALY_05000261 (0)
211#define ANOMALY_05000263 (0) 219#define ANOMALY_05000263 (0)
212#define ANOMALY_05000266 (0) 220#define ANOMALY_05000266 (0)
213#define ANOMALY_05000273 (0) 221#define ANOMALY_05000273 (0)
214#define ANOMALY_05000274 (0) 222#define ANOMALY_05000274 (0)
215#define ANOMALY_05000278 (0) 223#define ANOMALY_05000278 (0)
224#define ANOMALY_05000281 (0)
225#define ANOMALY_05000283 (0)
216#define ANOMALY_05000285 (0) 226#define ANOMALY_05000285 (0)
217#define ANOMALY_05000287 (0) 227#define ANOMALY_05000287 (0)
218#define ANOMALY_05000301 (0) 228#define ANOMALY_05000301 (0)
@@ -220,6 +230,7 @@
220#define ANOMALY_05000307 (0) 230#define ANOMALY_05000307 (0)
221#define ANOMALY_05000311 (0) 231#define ANOMALY_05000311 (0)
222#define ANOMALY_05000312 (0) 232#define ANOMALY_05000312 (0)
233#define ANOMALY_05000315 (0)
223#define ANOMALY_05000323 (0) 234#define ANOMALY_05000323 (0)
224#define ANOMALY_05000362 (1) 235#define ANOMALY_05000362 (1)
225#define ANOMALY_05000363 (0) 236#define ANOMALY_05000363 (0)