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authorMike Frysinger <vapier@gentoo.org>2010-07-29 01:53:33 -0400
committerMike Frysinger <vapier@gentoo.org>2010-08-06 12:55:56 -0400
commit39750324053c2aa4314e460b5ce1767f4dfbeff1 (patch)
treefecee75496cdc5b3ab05dcb8f0c441b6ef8d408f /arch/blackfin/mach-bf527/include
parentc385acceb4db55a492cb16b24b6102af90348440 (diff)
Blackfin: unify rotary encoder bitmasks
Avoid duplication and ugly global namespace pollution. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf527/include')
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h108
1 files changed, 0 insertions, 108 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index f08dae0d5138..5f97f01fcda6 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -1589,114 +1589,6 @@
1589 1589
1590#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ 1590#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1591 1591
1592/* Bit masks for CNT_CONFIG */
1593
1594#define CNTE 0x1 /* Counter Enable */
1595#define nCNTE 0x0
1596#define DEBE 0x2 /* Debounce Enable */
1597#define nDEBE 0x0
1598#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1599#define nCDGINV 0x0
1600#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1601#define nCUDINV 0x0
1602#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1603#define nCZMINV 0x0
1604#define CNTMODE 0x700 /* Counter Operating Mode */
1605#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1606#define nZMZC 0x0
1607#define BNDMODE 0x3000 /* Boundary register Mode */
1608#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1609#define nINPDIS 0x0
1610
1611/* Bit masks for CNT_IMASK */
1612
1613#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1614#define nICIE 0x0
1615#define UCIE 0x2 /* Up count Interrupt Enable */
1616#define nUCIE 0x0
1617#define DCIE 0x4 /* Down count Interrupt Enable */
1618#define nDCIE 0x0
1619#define MINCIE 0x8 /* Min Count Interrupt Enable */
1620#define nMINCIE 0x0
1621#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1622#define nMAXCIE 0x0
1623#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1624#define nCOV31IE 0x0
1625#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1626#define nCOV15IE 0x0
1627#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1628#define nCZEROIE 0x0
1629#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1630#define nCZMIE 0x0
1631#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1632#define nCZMEIE 0x0
1633#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1634#define nCZMZIE 0x0
1635
1636/* Bit masks for CNT_STATUS */
1637
1638#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1639#define nICII 0x0
1640#define UCII 0x2 /* Up count Interrupt Identifier */
1641#define nUCII 0x0
1642#define DCII 0x4 /* Down count Interrupt Identifier */
1643#define nDCII 0x0
1644#define MINCII 0x8 /* Min Count Interrupt Identifier */
1645#define nMINCII 0x0
1646#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1647#define nMAXCII 0x0
1648#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1649#define nCOV31II 0x0
1650#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1651#define nCOV15II 0x0
1652#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1653#define nCZEROII 0x0
1654#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1655#define nCZMII 0x0
1656#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1657#define nCZMEII 0x0
1658#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1659#define nCZMZII 0x0
1660
1661/* Bit masks for CNT_COMMAND */
1662
1663#define W1LCNT 0xf /* Load Counter Register */
1664#define W1LMIN 0xf0 /* Load Min Register */
1665#define W1LMAX 0xf00 /* Load Max Register */
1666#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1667#define nW1ZMONCE 0x0
1668
1669/* Bit masks for CNT_DEBOUNCE */
1670
1671#define DPRESCALE 0xf /* Load Counter Register */
1672
1673/* CNT_COMMAND bit field options */
1674
1675#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1676#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1677#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1678
1679#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1680#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1681#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1682
1683#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1684#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1685#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1686
1687/* CNT_CONFIG bit field options */
1688
1689#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1690#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1691#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1692#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1693#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1694
1695#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1696#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1697#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1698#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1699
1700/* Bit masks for SECURE_SYSSWT */ 1592/* Bit masks for SECURE_SYSSWT */
1701 1593
1702#define EMUDABL 0x1 /* Emulation Disable. */ 1594#define EMUDABL 0x1 /* Emulation Disable. */