diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2008-08-28 05:32:01 -0400 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-08-28 05:32:01 -0400 |
| commit | d310fb4bb73629840430cb13cb282915e49fef4b (patch) | |
| tree | a651b0f7fcdb7c217bc5a59500d36447dcec1580 /arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |
| parent | 226a6ec31117113a3b775b6b8d63dc4487c2d333 (diff) | |
Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/defBF52x_base.h')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | 185 |
1 files changed, 88 insertions, 97 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index fc69cf93f149..6ac2ed7026eb 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |||
| @@ -151,7 +151,7 @@ | |||
| 151 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | 151 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ |
| 152 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | 152 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ |
| 153 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | 153 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ |
| 154 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | 154 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ |
| 155 | 155 | ||
| 156 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | 156 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ |
| 157 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | 157 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ |
| @@ -634,18 +634,9 @@ | |||
| 634 | /* PLL_DIV Macros */ | 634 | /* PLL_DIV Macros */ |
| 635 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | 635 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ |
| 636 | 636 | ||
| 637 | /* VR_CTL Masks */ | 637 | /* VR_CTL Masks */ |
| 638 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | 638 | #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ |
| 639 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | 639 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ |
| 640 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
| 641 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
| 642 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
| 643 | |||
| 644 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
| 645 | #define GAIN_5 0x0000 /* GAIN = 5 */ | ||
| 646 | #define GAIN_10 0x0004 /* GAIN = 10 */ | ||
| 647 | #define GAIN_20 0x0008 /* GAIN = 20 */ | ||
| 648 | #define GAIN_50 0x000C /* GAIN = 50 */ | ||
| 649 | 640 | ||
| 650 | #define VLEV 0x00F0 /* Internal Voltage Level */ | 641 | #define VLEV 0x00F0 /* Internal Voltage Level */ |
| 651 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | 642 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ |
| @@ -660,7 +651,7 @@ | |||
| 660 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | 651 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ |
| 661 | 652 | ||
| 662 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | 653 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ |
| 663 | #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ | 654 | #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ |
| 664 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ | 655 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ |
| 665 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ | 656 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ |
| 666 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ | 657 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ |
| @@ -697,16 +688,16 @@ | |||
| 697 | 688 | ||
| 698 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | 689 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ |
| 699 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | 690 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ |
| 700 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | 691 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ |
| 701 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | 692 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ |
| 702 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | 693 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ |
| 703 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | 694 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ |
| 704 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | 695 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ |
| 705 | 696 | ||
| 706 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | 697 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ |
| 707 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | 698 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ |
| 708 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | 699 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ |
| 709 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | 700 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ |
| 710 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | 701 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ |
| 711 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | 702 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ |
| 712 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | 703 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ |
| @@ -801,7 +792,7 @@ | |||
| 801 | #define WDEV_NONE 0x0006 /* no event on roll over */ | 792 | #define WDEV_NONE 0x0006 /* no event on roll over */ |
| 802 | #define WDEN 0x0FF0 /* enable watchdog */ | 793 | #define WDEN 0x0FF0 /* enable watchdog */ |
| 803 | #define WDDIS 0x0AD0 /* disable watchdog */ | 794 | #define WDDIS 0x0AD0 /* disable watchdog */ |
| 804 | #define WDRO 0x8000 /* watchdog rolled over latch */ | 795 | #define WDRO 0x8000 /* watchdog rolled over latch */ |
| 805 | 796 | ||
| 806 | /* depreciated WDOG_CTL Register Masks for legacy code */ | 797 | /* depreciated WDOG_CTL Register Masks for legacy code */ |
| 807 | 798 | ||
| @@ -882,7 +873,7 @@ | |||
| 882 | #define NINT 0x01 /* Pending Interrupt */ | 873 | #define NINT 0x01 /* Pending Interrupt */ |
| 883 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | 874 | #define IIR_TX_READY 0x02 /* UART_THR empty */ |
| 884 | #define IIR_RX_READY 0x04 /* Receive data ready */ | 875 | #define IIR_RX_READY 0x04 /* Receive data ready */ |
| 885 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | 876 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ |
| 886 | #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ | 877 | #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ |
| 887 | 878 | ||
| 888 | /* UARTx_GCTL Masks */ | 879 | /* UARTx_GCTL Masks */ |
| @@ -1638,12 +1629,12 @@ | |||
| 1638 | 1629 | ||
| 1639 | /* entry addresses of the user-callable Boot ROM functions */ | 1630 | /* entry addresses of the user-callable Boot ROM functions */ |
| 1640 | 1631 | ||
| 1641 | #define _BOOTROM_RESET 0xEF000000 | 1632 | #define _BOOTROM_RESET 0xEF000000 |
| 1642 | #define _BOOTROM_FINAL_INIT 0xEF000002 | 1633 | #define _BOOTROM_FINAL_INIT 0xEF000002 |
| 1643 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | 1634 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 |
| 1644 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | 1635 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 |
| 1645 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | 1636 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A |
| 1646 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | 1637 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C |
| 1647 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | 1638 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 |
| 1648 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | 1639 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 |
| 1649 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | 1640 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 |
| @@ -1771,71 +1762,71 @@ | |||
| 1771 | /* Bit masks for CNT_CONFIG */ | 1762 | /* Bit masks for CNT_CONFIG */ |
| 1772 | 1763 | ||
| 1773 | #define CNTE 0x1 /* Counter Enable */ | 1764 | #define CNTE 0x1 /* Counter Enable */ |
| 1774 | #define nCNTE 0x0 | 1765 | #define nCNTE 0x0 |
| 1775 | #define DEBE 0x2 /* Debounce Enable */ | 1766 | #define DEBE 0x2 /* Debounce Enable */ |
| 1776 | #define nDEBE 0x0 | 1767 | #define nDEBE 0x0 |
| 1777 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ | 1768 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ |
| 1778 | #define nCDGINV 0x0 | 1769 | #define nCDGINV 0x0 |
| 1779 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ | 1770 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ |
| 1780 | #define nCUDINV 0x0 | 1771 | #define nCUDINV 0x0 |
| 1781 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ | 1772 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ |
| 1782 | #define nCZMINV 0x0 | 1773 | #define nCZMINV 0x0 |
| 1783 | #define CNTMODE 0x700 /* Counter Operating Mode */ | 1774 | #define CNTMODE 0x700 /* Counter Operating Mode */ |
| 1784 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ | 1775 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ |
| 1785 | #define nZMZC 0x0 | 1776 | #define nZMZC 0x0 |
| 1786 | #define BNDMODE 0x3000 /* Boundary register Mode */ | 1777 | #define BNDMODE 0x3000 /* Boundary register Mode */ |
| 1787 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ | 1778 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ |
| 1788 | #define nINPDIS 0x0 | 1779 | #define nINPDIS 0x0 |
| 1789 | 1780 | ||
| 1790 | /* Bit masks for CNT_IMASK */ | 1781 | /* Bit masks for CNT_IMASK */ |
| 1791 | 1782 | ||
| 1792 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ | 1783 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ |
| 1793 | #define nICIE 0x0 | 1784 | #define nICIE 0x0 |
| 1794 | #define UCIE 0x2 /* Up count Interrupt Enable */ | 1785 | #define UCIE 0x2 /* Up count Interrupt Enable */ |
| 1795 | #define nUCIE 0x0 | 1786 | #define nUCIE 0x0 |
| 1796 | #define DCIE 0x4 /* Down count Interrupt Enable */ | 1787 | #define DCIE 0x4 /* Down count Interrupt Enable */ |
| 1797 | #define nDCIE 0x0 | 1788 | #define nDCIE 0x0 |
| 1798 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ | 1789 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ |
| 1799 | #define nMINCIE 0x0 | 1790 | #define nMINCIE 0x0 |
| 1800 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ | 1791 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ |
| 1801 | #define nMAXCIE 0x0 | 1792 | #define nMAXCIE 0x0 |
| 1802 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ | 1793 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ |
| 1803 | #define nCOV31IE 0x0 | 1794 | #define nCOV31IE 0x0 |
| 1804 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ | 1795 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ |
| 1805 | #define nCOV15IE 0x0 | 1796 | #define nCOV15IE 0x0 |
| 1806 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ | 1797 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ |
| 1807 | #define nCZEROIE 0x0 | 1798 | #define nCZEROIE 0x0 |
| 1808 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ | 1799 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ |
| 1809 | #define nCZMIE 0x0 | 1800 | #define nCZMIE 0x0 |
| 1810 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ | 1801 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ |
| 1811 | #define nCZMEIE 0x0 | 1802 | #define nCZMEIE 0x0 |
| 1812 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ | 1803 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ |
| 1813 | #define nCZMZIE 0x0 | 1804 | #define nCZMZIE 0x0 |
| 1814 | 1805 | ||
| 1815 | /* Bit masks for CNT_STATUS */ | 1806 | /* Bit masks for CNT_STATUS */ |
| 1816 | 1807 | ||
| 1817 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ | 1808 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ |
| 1818 | #define nICII 0x0 | 1809 | #define nICII 0x0 |
| 1819 | #define UCII 0x2 /* Up count Interrupt Identifier */ | 1810 | #define UCII 0x2 /* Up count Interrupt Identifier */ |
| 1820 | #define nUCII 0x0 | 1811 | #define nUCII 0x0 |
| 1821 | #define DCII 0x4 /* Down count Interrupt Identifier */ | 1812 | #define DCII 0x4 /* Down count Interrupt Identifier */ |
| 1822 | #define nDCII 0x0 | 1813 | #define nDCII 0x0 |
| 1823 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ | 1814 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ |
| 1824 | #define nMINCII 0x0 | 1815 | #define nMINCII 0x0 |
| 1825 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ | 1816 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ |
| 1826 | #define nMAXCII 0x0 | 1817 | #define nMAXCII 0x0 |
| 1827 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ | 1818 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ |
| 1828 | #define nCOV31II 0x0 | 1819 | #define nCOV31II 0x0 |
| 1829 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ | 1820 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ |
| 1830 | #define nCOV15II 0x0 | 1821 | #define nCOV15II 0x0 |
| 1831 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ | 1822 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ |
| 1832 | #define nCZEROII 0x0 | 1823 | #define nCZEROII 0x0 |
| 1833 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ | 1824 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ |
| 1834 | #define nCZMII 0x0 | 1825 | #define nCZMII 0x0 |
| 1835 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ | 1826 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ |
| 1836 | #define nCZMEII 0x0 | 1827 | #define nCZMEII 0x0 |
| 1837 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ | 1828 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ |
| 1838 | #define nCZMZII 0x0 | 1829 | #define nCZMZII 0x0 |
| 1839 | 1830 | ||
| 1840 | /* Bit masks for CNT_COMMAND */ | 1831 | /* Bit masks for CNT_COMMAND */ |
| 1841 | 1832 | ||
| @@ -1843,7 +1834,7 @@ | |||
| 1843 | #define W1LMIN 0xf0 /* Load Min Register */ | 1834 | #define W1LMIN 0xf0 /* Load Min Register */ |
| 1844 | #define W1LMAX 0xf00 /* Load Max Register */ | 1835 | #define W1LMAX 0xf00 /* Load Max Register */ |
| 1845 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ | 1836 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ |
| 1846 | #define nW1ZMONCE 0x0 | 1837 | #define nW1ZMONCE 0x0 |
| 1847 | 1838 | ||
| 1848 | /* Bit masks for CNT_DEBOUNCE */ | 1839 | /* Bit masks for CNT_DEBOUNCE */ |
| 1849 | 1840 | ||
| @@ -1853,15 +1844,15 @@ | |||
| 1853 | 1844 | ||
| 1854 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ | 1845 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ |
| 1855 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ | 1846 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ |
| 1856 | #define nFIEN 0x0 | 1847 | #define nFIEN 0x0 |
| 1857 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ | 1848 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ |
| 1858 | #define nFTESTDEC 0x0 | 1849 | #define nFTESTDEC 0x0 |
| 1859 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ | 1850 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ |
| 1860 | #define nFWRTEST 0x0 | 1851 | #define nFWRTEST 0x0 |
| 1861 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ | 1852 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ |
| 1862 | #define nFRDEN 0x0 | 1853 | #define nFRDEN 0x0 |
| 1863 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ | 1854 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ |
| 1864 | #define nFWREN 0x0 | 1855 | #define nFWREN 0x0 |
| 1865 | 1856 | ||
| 1866 | /* Bit masks for OTP_BEN */ | 1857 | /* Bit masks for OTP_BEN */ |
| 1867 | 1858 | ||
| @@ -1870,15 +1861,15 @@ | |||
| 1870 | /* Bit masks for OTP_STATUS */ | 1861 | /* Bit masks for OTP_STATUS */ |
| 1871 | 1862 | ||
| 1872 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ | 1863 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ |
| 1873 | #define nFCOMP 0x0 | 1864 | #define nFCOMP 0x0 |
| 1874 | #define FERROR 0x2 /* OTP/Fuse Access Error */ | 1865 | #define FERROR 0x2 /* OTP/Fuse Access Error */ |
| 1875 | #define nFERROR 0x0 | 1866 | #define nFERROR 0x0 |
| 1876 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ | 1867 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ |
| 1877 | #define nMMRGLOAD 0x0 | 1868 | #define nMMRGLOAD 0x0 |
| 1878 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ | 1869 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ |
| 1879 | #define nMMRGLOCK 0x0 | 1870 | #define nMMRGLOCK 0x0 |
| 1880 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ | 1871 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ |
| 1881 | #define nFPGMEN 0x0 | 1872 | #define nFPGMEN 0x0 |
| 1882 | 1873 | ||
| 1883 | /* Bit masks for OTP_TIMING */ | 1874 | /* Bit masks for OTP_TIMING */ |
| 1884 | 1875 | ||
| @@ -1892,42 +1883,42 @@ | |||
| 1892 | /* Bit masks for SECURE_SYSSWT */ | 1883 | /* Bit masks for SECURE_SYSSWT */ |
| 1893 | 1884 | ||
| 1894 | #define EMUDABL 0x1 /* Emulation Disable. */ | 1885 | #define EMUDABL 0x1 /* Emulation Disable. */ |
| 1895 | #define nEMUDABL 0x0 | 1886 | #define nEMUDABL 0x0 |
| 1896 | #define RSTDABL 0x2 /* Reset Disable */ | 1887 | #define RSTDABL 0x2 /* Reset Disable */ |
| 1897 | #define nRSTDABL 0x0 | 1888 | #define nRSTDABL 0x0 |
| 1898 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | 1889 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ |
| 1899 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | 1890 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ |
| 1900 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | 1891 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ |
| 1901 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | 1892 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ |
| 1902 | #define nDMA0OVR 0x0 | 1893 | #define nDMA0OVR 0x0 |
| 1903 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | 1894 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ |
| 1904 | #define nDMA1OVR 0x0 | 1895 | #define nDMA1OVR 0x0 |
| 1905 | #define EMUOVR 0x4000 /* Emulation Override */ | 1896 | #define EMUOVR 0x4000 /* Emulation Override */ |
| 1906 | #define nEMUOVR 0x0 | 1897 | #define nEMUOVR 0x0 |
| 1907 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | 1898 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ |
| 1908 | #define nOTPSEN 0x0 | 1899 | #define nOTPSEN 0x0 |
| 1909 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | 1900 | #define L2DABL 0x70000 /* L2 Memory Disable. */ |
| 1910 | 1901 | ||
| 1911 | /* Bit masks for SECURE_CONTROL */ | 1902 | /* Bit masks for SECURE_CONTROL */ |
| 1912 | 1903 | ||
| 1913 | #define SECURE0 0x1 /* SECURE 0 */ | 1904 | #define SECURE0 0x1 /* SECURE 0 */ |
| 1914 | #define nSECURE0 0x0 | 1905 | #define nSECURE0 0x0 |
| 1915 | #define SECURE1 0x2 /* SECURE 1 */ | 1906 | #define SECURE1 0x2 /* SECURE 1 */ |
| 1916 | #define nSECURE1 0x0 | 1907 | #define nSECURE1 0x0 |
| 1917 | #define SECURE2 0x4 /* SECURE 2 */ | 1908 | #define SECURE2 0x4 /* SECURE 2 */ |
| 1918 | #define nSECURE2 0x0 | 1909 | #define nSECURE2 0x0 |
| 1919 | #define SECURE3 0x8 /* SECURE 3 */ | 1910 | #define SECURE3 0x8 /* SECURE 3 */ |
| 1920 | #define nSECURE3 0x0 | 1911 | #define nSECURE3 0x0 |
| 1921 | 1912 | ||
| 1922 | /* Bit masks for SECURE_STATUS */ | 1913 | /* Bit masks for SECURE_STATUS */ |
| 1923 | 1914 | ||
| 1924 | #define SECMODE 0x3 /* Secured Mode Control State */ | 1915 | #define SECMODE 0x3 /* Secured Mode Control State */ |
| 1925 | #define NMI 0x4 /* Non Maskable Interrupt */ | 1916 | #define NMI 0x4 /* Non Maskable Interrupt */ |
| 1926 | #define nNMI 0x0 | 1917 | #define nNMI 0x0 |
| 1927 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | 1918 | #define AFVALID 0x8 /* Authentication Firmware Valid */ |
| 1928 | #define nAFVALID 0x0 | 1919 | #define nAFVALID 0x0 |
| 1929 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | 1920 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ |
| 1930 | #define nAFEXIT 0x0 | 1921 | #define nAFEXIT 0x0 |
| 1931 | #define SECSTAT 0xe0 /* Secure Status */ | 1922 | #define SECSTAT 0xe0 /* Secure Status */ |
| 1932 | 1923 | ||
| 1933 | /* Bit masks for NFC_CTL */ | 1924 | /* Bit masks for NFC_CTL */ |
| @@ -1935,60 +1926,60 @@ | |||
| 1935 | #define WR_DLY 0xf /* Write Strobe Delay */ | 1926 | #define WR_DLY 0xf /* Write Strobe Delay */ |
| 1936 | #define RD_DLY 0xf0 /* Read Strobe Delay */ | 1927 | #define RD_DLY 0xf0 /* Read Strobe Delay */ |
| 1937 | #define NWIDTH 0x100 /* NAND Data Width */ | 1928 | #define NWIDTH 0x100 /* NAND Data Width */ |
| 1938 | #define nNWIDTH 0x0 | 1929 | #define nNWIDTH 0x0 |
| 1939 | #define PG_SIZE 0x200 /* Page Size */ | 1930 | #define PG_SIZE 0x200 /* Page Size */ |
| 1940 | #define nPG_SIZE 0x0 | 1931 | #define nPG_SIZE 0x0 |
| 1941 | 1932 | ||
| 1942 | /* Bit masks for NFC_STAT */ | 1933 | /* Bit masks for NFC_STAT */ |
| 1943 | 1934 | ||
| 1944 | #define NBUSY 0x1 /* Not Busy */ | 1935 | #define NBUSY 0x1 /* Not Busy */ |
| 1945 | #define nNBUSY 0x0 | 1936 | #define nNBUSY 0x0 |
| 1946 | #define WB_FULL 0x2 /* Write Buffer Full */ | 1937 | #define WB_FULL 0x2 /* Write Buffer Full */ |
| 1947 | #define nWB_FULL 0x0 | 1938 | #define nWB_FULL 0x0 |
| 1948 | #define PG_WR_STAT 0x4 /* Page Write Pending */ | 1939 | #define PG_WR_STAT 0x4 /* Page Write Pending */ |
| 1949 | #define nPG_WR_STAT 0x0 | 1940 | #define nPG_WR_STAT 0x0 |
| 1950 | #define PG_RD_STAT 0x8 /* Page Read Pending */ | 1941 | #define PG_RD_STAT 0x8 /* Page Read Pending */ |
| 1951 | #define nPG_RD_STAT 0x0 | 1942 | #define nPG_RD_STAT 0x0 |
| 1952 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | 1943 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ |
| 1953 | #define nWB_EMPTY 0x0 | 1944 | #define nWB_EMPTY 0x0 |
| 1954 | 1945 | ||
| 1955 | /* Bit masks for NFC_IRQSTAT */ | 1946 | /* Bit masks for NFC_IRQSTAT */ |
| 1956 | 1947 | ||
| 1957 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ | 1948 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ |
| 1958 | #define nNBUSYIRQ 0x0 | 1949 | #define nNBUSYIRQ 0x0 |
| 1959 | #define WB_OVF 0x2 /* Write Buffer Overflow */ | 1950 | #define WB_OVF 0x2 /* Write Buffer Overflow */ |
| 1960 | #define nWB_OVF 0x0 | 1951 | #define nWB_OVF 0x0 |
| 1961 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ | 1952 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ |
| 1962 | #define nWB_EDGE 0x0 | 1953 | #define nWB_EDGE 0x0 |
| 1963 | #define RD_RDY 0x8 /* Read Data Ready */ | 1954 | #define RD_RDY 0x8 /* Read Data Ready */ |
| 1964 | #define nRD_RDY 0x0 | 1955 | #define nRD_RDY 0x0 |
| 1965 | #define WR_DONE 0x10 /* Page Write Done */ | 1956 | #define WR_DONE 0x10 /* Page Write Done */ |
| 1966 | #define nWR_DONE 0x0 | 1957 | #define nWR_DONE 0x0 |
| 1967 | 1958 | ||
| 1968 | /* Bit masks for NFC_IRQMASK */ | 1959 | /* Bit masks for NFC_IRQMASK */ |
| 1969 | 1960 | ||
| 1970 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ | 1961 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ |
| 1971 | #define nMASK_BUSYIRQ 0x0 | 1962 | #define nMASK_BUSYIRQ 0x0 |
| 1972 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ | 1963 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ |
| 1973 | #define nMASK_WBOVF 0x0 | 1964 | #define nMASK_WBOVF 0x0 |
| 1974 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ | 1965 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ |
| 1975 | #define nMASK_WBEMPTY 0x0 | 1966 | #define nMASK_WBEMPTY 0x0 |
| 1976 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ | 1967 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ |
| 1977 | #define nMASK_RDRDY 0x0 | 1968 | #define nMASK_RDRDY 0x0 |
| 1978 | #define MASK_WRDONE 0x10 /* Mask Write Done */ | 1969 | #define MASK_WRDONE 0x10 /* Mask Write Done */ |
| 1979 | #define nMASK_WRDONE 0x0 | 1970 | #define nMASK_WRDONE 0x0 |
| 1980 | 1971 | ||
| 1981 | /* Bit masks for NFC_RST */ | 1972 | /* Bit masks for NFC_RST */ |
| 1982 | 1973 | ||
| 1983 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ | 1974 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ |
| 1984 | #define nECC_RST 0x0 | 1975 | #define nECC_RST 0x0 |
| 1985 | 1976 | ||
| 1986 | /* Bit masks for NFC_PGCTL */ | 1977 | /* Bit masks for NFC_PGCTL */ |
| 1987 | 1978 | ||
| 1988 | #define PG_RD_START 0x1 /* Page Read Start */ | 1979 | #define PG_RD_START 0x1 /* Page Read Start */ |
| 1989 | #define nPG_RD_START 0x0 | 1980 | #define nPG_RD_START 0x0 |
| 1990 | #define PG_WR_START 0x2 /* Page Write Start */ | 1981 | #define PG_WR_START 0x2 /* Page Write Start */ |
| 1991 | #define nPG_WR_START 0x0 | 1982 | #define nPG_WR_START 0x0 |
| 1992 | 1983 | ||
| 1993 | /* Bit masks for NFC_ECC0 */ | 1984 | /* Bit masks for NFC_ECC0 */ |
| 1994 | 1985 | ||