aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf518
diff options
context:
space:
mode:
authorMike Frysinger <vapier@gentoo.org>2010-06-08 23:02:09 -0400
committerMike Frysinger <vapier@gentoo.org>2010-08-06 12:55:49 -0400
commit502c8a0e07450ff886b80a11150a123bae92f3f7 (patch)
tree23cb5a47714e4f863035edfbde5c712dd820d314 /arch/blackfin/mach-bf518
parent306208f40cde5f835e891976031571b81815b9df (diff)
Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
Even though the PH8 pin is only internal to the processor packaging, it can be controlled like any other GPIO pin. Now that we have a proper GPIO define, we can fix the SPI0 CS4 define for the internal SPI flash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/gpio.h3
-rw-r--r--arch/blackfin/mach-bf518/include/mach/portmux.h2
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
index bbab2d76499c..3532a744c389 100644
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_GPIO_H_ 7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10#define MAX_BLACKFIN_GPIOS 40 10#define MAX_BLACKFIN_GPIOS 41
11 11
12#define GPIO_PF0 0 12#define GPIO_PF0 0
13#define GPIO_PF1 1 13#define GPIO_PF1 1
@@ -49,6 +49,7 @@
49#define GPIO_PH5 37 49#define GPIO_PH5 37
50#define GPIO_PH6 38 50#define GPIO_PH6 38
51#define GPIO_PH7 39 51#define GPIO_PH7 39
52#define GPIO_PH8 40
52 53
53#define PORT_F GPIO_PF0 54#define PORT_F GPIO_PF0
54#define PORT_G GPIO_PG0 55#define PORT_G GPIO_PG0
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index d39eb4b66de7..5d62430a621a 100644
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -95,7 +95,7 @@
95#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) 95#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
96#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) 96#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
97#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) 97#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
98#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) 98#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
99#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) 99#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
100 100
101#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) 101#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))