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authorMike Frysinger <vapier@gentoo.org>2011-03-30 03:59:00 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:42 -0400
commit3dd666067d2b285724c828946e83100ea4c43d4b (patch)
treebb0e0c060013e12a7d6674f8139a5fec59cf6fbc /arch/blackfin/mach-bf518
parent6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff)
Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h218
1 files changed, 109 insertions, 109 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index daf1fa5bbb00..edf8efd457dc 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -9,7 +9,7 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
13 13
14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -25,23 +25,23 @@
25#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 25#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
26#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 26#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
27#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 27#define IRQ_RTC BFIN_IRQ(14) /* RTC */
28#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */ 28#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
29#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 29#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
30#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 30#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
31#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */ 31#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
32#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */ 32#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
33#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */ 33#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
34#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 34#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
35#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 35#define IRQ_TWI BFIN_IRQ(20) /* TWI */
36#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */ 36#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
37#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 37#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
38#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 38#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
39#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 39#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
40#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 40#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
41#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 41#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
42#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 42#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
43#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */ 43#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
44#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 44#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
45#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ 45#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
46#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 46#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
47#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ 47#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
@@ -67,90 +67,90 @@
67#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */ 67#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
68#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */ 68#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
69 69
70#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
71 71
72#define IRQ_PF0 71 72#define IRQ_PF0 71
73#define IRQ_PF1 72 73#define IRQ_PF1 72
74#define IRQ_PF2 73 74#define IRQ_PF2 73
75#define IRQ_PF3 74 75#define IRQ_PF3 74
76#define IRQ_PF4 75 76#define IRQ_PF4 75
77#define IRQ_PF5 76 77#define IRQ_PF5 76
78#define IRQ_PF6 77 78#define IRQ_PF6 77
79#define IRQ_PF7 78 79#define IRQ_PF7 78
80#define IRQ_PF8 79 80#define IRQ_PF8 79
81#define IRQ_PF9 80 81#define IRQ_PF9 80
82#define IRQ_PF10 81 82#define IRQ_PF10 81
83#define IRQ_PF11 82 83#define IRQ_PF11 82
84#define IRQ_PF12 83 84#define IRQ_PF12 83
85#define IRQ_PF13 84 85#define IRQ_PF13 84
86#define IRQ_PF14 85 86#define IRQ_PF14 85
87#define IRQ_PF15 86 87#define IRQ_PF15 86
88 88
89#define IRQ_PG0 87 89#define IRQ_PG0 87
90#define IRQ_PG1 88 90#define IRQ_PG1 88
91#define IRQ_PG2 89 91#define IRQ_PG2 89
92#define IRQ_PG3 90 92#define IRQ_PG3 90
93#define IRQ_PG4 91 93#define IRQ_PG4 91
94#define IRQ_PG5 92 94#define IRQ_PG5 92
95#define IRQ_PG6 93 95#define IRQ_PG6 93
96#define IRQ_PG7 94 96#define IRQ_PG7 94
97#define IRQ_PG8 95 97#define IRQ_PG8 95
98#define IRQ_PG9 96 98#define IRQ_PG9 96
99#define IRQ_PG10 97 99#define IRQ_PG10 97
100#define IRQ_PG11 98 100#define IRQ_PG11 98
101#define IRQ_PG12 99 101#define IRQ_PG12 99
102#define IRQ_PG13 100 102#define IRQ_PG13 100
103#define IRQ_PG14 101 103#define IRQ_PG14 101
104#define IRQ_PG15 102 104#define IRQ_PG15 102
105 105
106#define IRQ_PH0 103 106#define IRQ_PH0 103
107#define IRQ_PH1 104 107#define IRQ_PH1 104
108#define IRQ_PH2 105 108#define IRQ_PH2 105
109#define IRQ_PH3 106 109#define IRQ_PH3 106
110#define IRQ_PH4 107 110#define IRQ_PH4 107
111#define IRQ_PH5 108 111#define IRQ_PH5 108
112#define IRQ_PH6 109 112#define IRQ_PH6 109
113#define IRQ_PH7 110 113#define IRQ_PH7 110
114#define IRQ_PH8 111 114#define IRQ_PH8 111
115#define IRQ_PH9 112 115#define IRQ_PH9 112
116#define IRQ_PH10 113 116#define IRQ_PH10 113
117#define IRQ_PH11 114 117#define IRQ_PH11 114
118#define IRQ_PH12 115 118#define IRQ_PH12 115
119#define IRQ_PH13 116 119#define IRQ_PH13 116
120#define IRQ_PH14 117 120#define IRQ_PH14 117
121#define IRQ_PH15 118 121#define IRQ_PH15 118
122 122
123#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
124 124
125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
133 133
134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
135 135
136/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
137#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
138#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
139#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
140#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
141#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
142#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
143#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
144#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
145 145
146/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
147#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
148#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
149#define IRQ_PTP_ERROR_POS 8 149#define IRQ_PTP_ERROR_POS 8
150#define IRQ_UART0_ERROR_POS 16 150#define IRQ_UART0_ERROR_POS 16
151#define IRQ_UART1_ERROR_POS 20 151#define IRQ_UART1_ERROR_POS 20
152#define IRQ_RTC_POS 24 152#define IRQ_RTC_POS 24
153#define IRQ_PPI_POS 28 153#define IRQ_PPI_POS 28
154 154
155/* IAR2 BIT FIELDS */ 155/* IAR2 BIT FIELDS */
156#define IRQ_SPORT0_RX_POS 0 156#define IRQ_SPORT0_RX_POS 0
@@ -159,19 +159,19 @@
159#define IRQ_SPORT1_RX_POS 8 159#define IRQ_SPORT1_RX_POS 8
160#define IRQ_SPI1_POS 8 160#define IRQ_SPI1_POS 8
161#define IRQ_SPORT1_TX_POS 12 161#define IRQ_SPORT1_TX_POS 12
162#define IRQ_TWI_POS 16 162#define IRQ_TWI_POS 16
163#define IRQ_SPI0_POS 20 163#define IRQ_SPI0_POS 20
164#define IRQ_UART0_RX_POS 24 164#define IRQ_UART0_RX_POS 24
165#define IRQ_UART0_TX_POS 28 165#define IRQ_UART0_TX_POS 28
166 166
167/* IAR3 BIT FIELDS */ 167/* IAR3 BIT FIELDS */
168#define IRQ_UART1_RX_POS 0 168#define IRQ_UART1_RX_POS 0
169#define IRQ_UART1_TX_POS 4 169#define IRQ_UART1_TX_POS 4
170#define IRQ_OPTSEC_POS 8 170#define IRQ_OPTSEC_POS 8
171#define IRQ_CNT_POS 12 171#define IRQ_CNT_POS 12
172#define IRQ_MAC_RX_POS 16 172#define IRQ_MAC_RX_POS 16
173#define IRQ_PORTH_INTA_POS 20 173#define IRQ_PORTH_INTA_POS 20
174#define IRQ_MAC_TX_POS 24 174#define IRQ_MAC_TX_POS 24
175#define IRQ_PORTH_INTB_POS 28 175#define IRQ_PORTH_INTB_POS 28
176 176
177/* IAR4 BIT FIELDS */ 177/* IAR4 BIT FIELDS */
@@ -187,19 +187,19 @@
187/* IAR5 BIT FIELDS */ 187/* IAR5 BIT FIELDS */
188#define IRQ_PORTG_INTA_POS 0 188#define IRQ_PORTG_INTA_POS 0
189#define IRQ_PORTG_INTB_POS 4 189#define IRQ_PORTG_INTB_POS 4
190#define IRQ_MEM_DMA0_POS 8 190#define IRQ_MEM_DMA0_POS 8
191#define IRQ_MEM_DMA1_POS 12 191#define IRQ_MEM_DMA1_POS 12
192#define IRQ_WATCH_POS 16 192#define IRQ_WATCH_POS 16
193#define IRQ_PORTF_INTA_POS 20 193#define IRQ_PORTF_INTA_POS 20
194#define IRQ_PORTF_INTB_POS 24 194#define IRQ_PORTF_INTB_POS 24
195#define IRQ_SPI0_ERROR_POS 28 195#define IRQ_SPI0_ERROR_POS 28
196 196
197/* IAR6 BIT FIELDS */ 197/* IAR6 BIT FIELDS */
198#define IRQ_SPI1_ERROR_POS 0 198#define IRQ_SPI1_ERROR_POS 0
199#define IRQ_RSI_INT0_POS 12 199#define IRQ_RSI_INT0_POS 12
200#define IRQ_RSI_INT1_POS 16 200#define IRQ_RSI_INT1_POS 16
201#define IRQ_PWM_TRIP_POS 20 201#define IRQ_PWM_TRIP_POS 20
202#define IRQ_PWM_SYNC_POS 24 202#define IRQ_PWM_SYNC_POS 24
203#define IRQ_PTP_STAT_POS 28 203#define IRQ_PTP_STAT_POS 28
204 204
205#endif /* _BF518_IRQ_H_ */ 205#endif