Blackfin arch: merge adeos blackfin part to arch/blackfin/

[Mike Frysinger <vapier.adi@gmail.com>:
 - handle bf531/bf532/bf534/bf536 variants in ipipe.h
 - cleanup IPIPE logic for bfin_set_irq_handler()
 - cleanup ipipe asm code a bit and add missing ENDPROC()
 - simplify IPIPE code in trap_c
 - unify some of the IPIPE code and fix style
 - simplify DO_IRQ_L1 handling with ipipe code
 - revert IRQ_SW_INT# addition from ipipe merge
 - remove duplicate get_{c,s}clk() prototypes
]

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

2 files changed, 20 insertions, 20 deletions

diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 9fbcd2221986..ee3d4733369c 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -1163,7 +1163,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
         if (val == bfin_read_PLL_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr0 = bfin_read32(SIC_IWR0);
         iwr1 = bfin_read32(SIC_IWR1);
@@ -1177,7 +1177,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
 
         bfin_write32(SIC_IWR0, iwr0);
         bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 /* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1188,7 +1188,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         if (val == bfin_read_VR_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr0 = bfin_read32(SIC_IWR0);
         iwr1 = bfin_read32(SIC_IWR1);
@@ -1202,7 +1202,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 
         bfin_write32(SIC_IWR0, iwr0);
         bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 #endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index e5062f107ae2..3ff0f093313d 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -98,14 +98,14 @@
 #define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
-#define IRQ_TMR0                BFIN_IRQ(32)    /* Timer 0 */
-#define IRQ_TMR1                BFIN_IRQ(33)    /* Timer 1 */
-#define IRQ_TMR2                BFIN_IRQ(34)    /* Timer 2 */
-#define IRQ_TMR3                BFIN_IRQ(35)    /* Timer 3 */
-#define IRQ_TMR4                BFIN_IRQ(36)    /* Timer 4 */
-#define IRQ_TMR5                BFIN_IRQ(37)    /* Timer 5 */
-#define IRQ_TMR6                BFIN_IRQ(38)    /* Timer 6 */
-#define IRQ_TMR7                BFIN_IRQ(39)    /* Timer 7 */
+#define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(33)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(34)    /* Timer 2 */
+#define IRQ_TIMER3              BFIN_IRQ(35)    /* Timer 3 */
+#define IRQ_TIMER4              BFIN_IRQ(36)    /* Timer 4 */
+#define IRQ_TIMER5              BFIN_IRQ(37)    /* Timer 5 */
+#define IRQ_TIMER6              BFIN_IRQ(38)    /* Timer 6 */
+#define IRQ_TIMER7              BFIN_IRQ(39)    /* Timer 7 */
 #define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
 #define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
 #define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
@@ -230,14 +230,14 @@
 #define IRQ_PORTH_INTB_POS      28
 
 /* IAR4 BIT FIELDS */
-#define IRQ_TMR0_POS            0
-#define IRQ_TMR1_POS            4
-#define IRQ_TMR2_POS            8
-#define IRQ_TMR3_POS            12
-#define IRQ_TMR4_POS            16
-#define IRQ_TMR5_POS            20
-#define IRQ_TMR6_POS            24
-#define IRQ_TMR7_POS            28
+#define IRQ_TIMER0_POS          0
+#define IRQ_TIMER1_POS          4
+#define IRQ_TIMER2_POS          8
+#define IRQ_TIMER3_POS          12
+#define IRQ_TIMER4_POS          16
+#define IRQ_TIMER5_POS          20
+#define IRQ_TIMER6_POS          24
+#define IRQ_TIMER7_POS          28
 
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0