diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-10-26 23:56:12 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-01-10 07:18:09 -0500 |
| commit | 53ee5826546df6b1a989393f8701d1380a441449 (patch) | |
| tree | fbf87e496f67bbfbfc53c27e18b78d770163bf08 /arch/blackfin/mach-bf518/include | |
| parent | 1a5c226528990515c603bae04233016411b44159 (diff) | |
Blackfin: bf51x/bf52x: drop redundant "base" def/cdef header
The defBF512.h header exists only to include defBF51x_base.h, and it is
the only place where defBF51x_base.h is included. So move the contents
of the defBF51x_base.h header into the defBF512.h header.
Same situation for the other def/cdef pairs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf518/include')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF512.h | 1037 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h | 1048 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF512.h | 1385 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 1397 |
4 files changed, 2418 insertions, 2449 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h index 4a207194d76c..52a7b7ded88f 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h | |||
| @@ -7,7 +7,1040 @@ | |||
| 7 | #ifndef _CDEF_BF512_H | 7 | #ifndef _CDEF_BF512_H |
| 8 | #define _CDEF_BF512_H | 8 | #define _CDEF_BF512_H |
| 9 | 9 | ||
| 10 | /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | 10 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
| 11 | #include "cdefBF51x_base.h" | 11 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 12 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
| 13 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | ||
| 14 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
| 15 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
| 16 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | ||
| 17 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
| 18 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | ||
| 19 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
| 20 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | ||
| 21 | |||
| 22 | |||
| 23 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 24 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
| 25 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | ||
| 26 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
| 27 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | ||
| 28 | |||
| 29 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) | ||
| 30 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) | ||
| 31 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | ||
| 32 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | ||
| 33 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) | ||
| 34 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) | ||
| 35 | |||
| 36 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | ||
| 37 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | ||
| 38 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | ||
| 39 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | ||
| 40 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | ||
| 41 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | ||
| 42 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | ||
| 43 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | ||
| 44 | |||
| 45 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | ||
| 46 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | ||
| 47 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) | ||
| 48 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) | ||
| 49 | |||
| 50 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | ||
| 51 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | ||
| 52 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) | ||
| 53 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) | ||
| 54 | |||
| 55 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 56 | |||
| 57 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | ||
| 58 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | ||
| 59 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | ||
| 60 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | ||
| 61 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | ||
| 62 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | ||
| 63 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | ||
| 64 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | ||
| 65 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) | ||
| 66 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) | ||
| 67 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | ||
| 68 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | ||
| 69 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | ||
| 70 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | ||
| 71 | |||
| 72 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 73 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | ||
| 74 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | ||
| 75 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | ||
| 76 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | ||
| 77 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | ||
| 78 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | ||
| 79 | |||
| 80 | |||
| 81 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 82 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | ||
| 83 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | ||
| 84 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | ||
| 85 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | ||
| 86 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | ||
| 87 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | ||
| 88 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | ||
| 89 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | ||
| 90 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | ||
| 91 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | ||
| 92 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | ||
| 93 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) | ||
| 94 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | ||
| 95 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | ||
| 96 | |||
| 97 | |||
| 98 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 99 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | ||
| 100 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | ||
| 101 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | ||
| 102 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | ||
| 103 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | ||
| 104 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | ||
| 105 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) | ||
| 106 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) | ||
| 107 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | ||
| 108 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | ||
| 109 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) | ||
| 110 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) | ||
| 111 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | ||
| 112 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | ||
| 113 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | ||
| 114 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | ||
| 115 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | ||
| 116 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | ||
| 117 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) | ||
| 118 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) | ||
| 119 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | ||
| 120 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | ||
| 121 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | ||
| 122 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | ||
| 123 | |||
| 124 | |||
| 125 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 126 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
| 127 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | ||
| 128 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
| 129 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | ||
| 130 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
| 131 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | ||
| 132 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
| 133 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | ||
| 134 | |||
| 135 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
| 136 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | ||
| 137 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
| 138 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | ||
| 139 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
| 140 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | ||
| 141 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
| 142 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | ||
| 143 | |||
| 144 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
| 145 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | ||
| 146 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
| 147 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | ||
| 148 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
| 149 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | ||
| 150 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
| 151 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | ||
| 152 | |||
| 153 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | ||
| 154 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) | ||
| 155 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | ||
| 156 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) | ||
| 157 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | ||
| 158 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) | ||
| 159 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | ||
| 160 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) | ||
| 161 | |||
| 162 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | ||
| 163 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) | ||
| 164 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | ||
| 165 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) | ||
| 166 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | ||
| 167 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) | ||
| 168 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | ||
| 169 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) | ||
| 170 | |||
| 171 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | ||
| 172 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) | ||
| 173 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | ||
| 174 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) | ||
| 175 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | ||
| 176 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) | ||
| 177 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | ||
| 178 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) | ||
| 179 | |||
| 180 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | ||
| 181 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) | ||
| 182 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | ||
| 183 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) | ||
| 184 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | ||
| 185 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) | ||
| 186 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | ||
| 187 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) | ||
| 188 | |||
| 189 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | ||
| 190 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) | ||
| 191 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | ||
| 192 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) | ||
| 193 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | ||
| 194 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) | ||
| 195 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | ||
| 196 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) | ||
| 197 | |||
| 198 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | ||
| 199 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) | ||
| 200 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | ||
| 201 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) | ||
| 202 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) | ||
| 203 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) | ||
| 204 | |||
| 205 | |||
| 206 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 207 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) | ||
| 208 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) | ||
| 209 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) | ||
| 210 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) | ||
| 211 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) | ||
| 212 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) | ||
| 213 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) | ||
| 214 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) | ||
| 215 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) | ||
| 216 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) | ||
| 217 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) | ||
| 218 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) | ||
| 219 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) | ||
| 220 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) | ||
| 221 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) | ||
| 222 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) | ||
| 223 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) | ||
| 224 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) | ||
| 225 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) | ||
| 226 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) | ||
| 227 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) | ||
| 228 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) | ||
| 229 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) | ||
| 230 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) | ||
| 231 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) | ||
| 232 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) | ||
| 233 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) | ||
| 234 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) | ||
| 235 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) | ||
| 236 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) | ||
| 237 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) | ||
| 238 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) | ||
| 239 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) | ||
| 240 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) | ||
| 241 | |||
| 242 | |||
| 243 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 244 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 245 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
| 246 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 247 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
| 248 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 249 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
| 250 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 251 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
| 252 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 253 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
| 254 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 255 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
| 256 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) | ||
| 257 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) | ||
| 258 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) | ||
| 259 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) | ||
| 260 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) | ||
| 261 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) | ||
| 262 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) | ||
| 263 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) | ||
| 264 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 265 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
| 266 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 267 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
| 268 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 269 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
| 270 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 271 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
| 272 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 273 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
| 274 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 275 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
| 276 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 277 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
| 278 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 279 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
| 280 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 281 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
| 282 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 283 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
| 284 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 285 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
| 286 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 287 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
| 288 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 289 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
| 290 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 291 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
| 292 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 293 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
| 294 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 295 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
| 296 | |||
| 297 | |||
| 298 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 299 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
| 300 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | ||
| 301 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
| 302 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | ||
| 303 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
| 304 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | ||
| 305 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
| 306 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | ||
| 307 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
| 308 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | ||
| 309 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
| 310 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | ||
| 311 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) | ||
| 312 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) | ||
| 313 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) | ||
| 314 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) | ||
| 315 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) | ||
| 316 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) | ||
| 317 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) | ||
| 318 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) | ||
| 319 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
| 320 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | ||
| 321 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
| 322 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | ||
| 323 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
| 324 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | ||
| 325 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
| 326 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | ||
| 327 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
| 328 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | ||
| 329 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
| 330 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | ||
| 331 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
| 332 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | ||
| 333 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
| 334 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | ||
| 335 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
| 336 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | ||
| 337 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
| 338 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | ||
| 339 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
| 340 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | ||
| 341 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
| 342 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | ||
| 343 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
| 344 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | ||
| 345 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
| 346 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | ||
| 347 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
| 348 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | ||
| 349 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
| 350 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | ||
| 351 | |||
| 352 | |||
| 353 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 354 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
| 355 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | ||
| 356 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
| 357 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | ||
| 358 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
| 359 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | ||
| 360 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
| 361 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) | ||
| 362 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | ||
| 363 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) | ||
| 364 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
| 365 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) | ||
| 366 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
| 367 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) | ||
| 368 | |||
| 369 | |||
| 370 | /* DMA Traffic Control Registers */ | ||
| 371 | #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) | ||
| 372 | #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) | ||
| 373 | #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) | ||
| 374 | #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) | ||
| 375 | |||
| 376 | /* DMA Controller */ | ||
| 377 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | ||
| 378 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | ||
| 379 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | ||
| 380 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) | ||
| 381 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | ||
| 382 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) | ||
| 383 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | ||
| 384 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | ||
| 385 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | ||
| 386 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | ||
| 387 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | ||
| 388 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) | ||
| 389 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | ||
| 390 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) | ||
| 391 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | ||
| 392 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) | ||
| 393 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | ||
| 394 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) | ||
| 395 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | ||
| 396 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | ||
| 397 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | ||
| 398 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | ||
| 399 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | ||
| 400 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | ||
| 401 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | ||
| 402 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | ||
| 403 | |||
| 404 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | ||
| 405 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | ||
| 406 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | ||
| 407 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) | ||
| 408 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | ||
| 409 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) | ||
| 410 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | ||
| 411 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | ||
| 412 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | ||
| 413 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | ||
| 414 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | ||
| 415 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) | ||
| 416 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | ||
| 417 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) | ||
| 418 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | ||
| 419 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) | ||
| 420 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | ||
| 421 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) | ||
| 422 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | ||
| 423 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | ||
| 424 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | ||
| 425 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | ||
| 426 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | ||
| 427 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | ||
| 428 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | ||
| 429 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | ||
| 430 | |||
| 431 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | ||
| 432 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | ||
| 433 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | ||
| 434 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) | ||
| 435 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | ||
| 436 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) | ||
| 437 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | ||
| 438 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | ||
| 439 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | ||
| 440 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | ||
| 441 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | ||
| 442 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) | ||
| 443 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | ||
| 444 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) | ||
| 445 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | ||
| 446 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) | ||
| 447 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | ||
| 448 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) | ||
| 449 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | ||
| 450 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | ||
| 451 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | ||
| 452 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | ||
| 453 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | ||
| 454 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | ||
| 455 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | ||
| 456 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | ||
| 457 | |||
| 458 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | ||
| 459 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | ||
| 460 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | ||
| 461 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) | ||
| 462 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | ||
| 463 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) | ||
| 464 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | ||
| 465 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | ||
| 466 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | ||
| 467 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | ||
| 468 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | ||
| 469 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) | ||
| 470 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | ||
| 471 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) | ||
| 472 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | ||
| 473 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) | ||
| 474 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | ||
| 475 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) | ||
| 476 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | ||
| 477 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | ||
| 478 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | ||
| 479 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | ||
| 480 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | ||
| 481 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | ||
| 482 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | ||
| 483 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | ||
| 484 | |||
| 485 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | ||
| 486 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | ||
| 487 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | ||
| 488 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) | ||
| 489 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | ||
| 490 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) | ||
| 491 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | ||
| 492 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | ||
| 493 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | ||
| 494 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | ||
| 495 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | ||
| 496 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) | ||
| 497 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | ||
| 498 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) | ||
| 499 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | ||
| 500 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) | ||
| 501 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | ||
| 502 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) | ||
| 503 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | ||
| 504 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | ||
| 505 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | ||
| 506 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | ||
| 507 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | ||
| 508 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | ||
| 509 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | ||
| 510 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | ||
| 511 | |||
| 512 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | ||
| 513 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | ||
| 514 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | ||
| 515 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) | ||
| 516 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | ||
| 517 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) | ||
| 518 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | ||
| 519 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | ||
| 520 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | ||
| 521 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | ||
| 522 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | ||
| 523 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) | ||
| 524 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | ||
| 525 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) | ||
| 526 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | ||
| 527 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) | ||
| 528 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | ||
| 529 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) | ||
| 530 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | ||
| 531 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | ||
| 532 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | ||
| 533 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | ||
| 534 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | ||
| 535 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | ||
| 536 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | ||
| 537 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | ||
| 538 | |||
| 539 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | ||
| 540 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | ||
| 541 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | ||
| 542 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) | ||
| 543 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | ||
| 544 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) | ||
| 545 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | ||
| 546 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | ||
| 547 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | ||
| 548 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | ||
| 549 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | ||
| 550 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) | ||
| 551 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | ||
| 552 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) | ||
| 553 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | ||
| 554 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) | ||
| 555 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | ||
| 556 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) | ||
| 557 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | ||
| 558 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | ||
| 559 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | ||
| 560 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | ||
| 561 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | ||
| 562 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | ||
| 563 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | ||
| 564 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | ||
| 565 | |||
| 566 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | ||
| 567 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | ||
| 568 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | ||
| 569 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) | ||
| 570 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | ||
| 571 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) | ||
| 572 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | ||
| 573 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | ||
| 574 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | ||
| 575 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | ||
| 576 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | ||
| 577 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) | ||
| 578 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | ||
| 579 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) | ||
| 580 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | ||
| 581 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) | ||
| 582 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | ||
| 583 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) | ||
| 584 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | ||
| 585 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | ||
| 586 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | ||
| 587 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | ||
| 588 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | ||
| 589 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | ||
| 590 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | ||
| 591 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | ||
| 592 | |||
| 593 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | ||
| 594 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | ||
| 595 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | ||
| 596 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) | ||
| 597 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) | ||
| 598 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) | ||
| 599 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | ||
| 600 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | ||
| 601 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | ||
| 602 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | ||
| 603 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | ||
| 604 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) | ||
| 605 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | ||
| 606 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) | ||
| 607 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) | ||
| 608 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) | ||
| 609 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) | ||
| 610 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) | ||
| 611 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | ||
| 612 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | ||
| 613 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | ||
| 614 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | ||
| 615 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | ||
| 616 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | ||
| 617 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | ||
| 618 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | ||
| 619 | |||
| 620 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | ||
| 621 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | ||
| 622 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | ||
| 623 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) | ||
| 624 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) | ||
| 625 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) | ||
| 626 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | ||
| 627 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | ||
| 628 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | ||
| 629 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | ||
| 630 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | ||
| 631 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) | ||
| 632 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | ||
| 633 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) | ||
| 634 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) | ||
| 635 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) | ||
| 636 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) | ||
| 637 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) | ||
| 638 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | ||
| 639 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | ||
| 640 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | ||
| 641 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | ||
| 642 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | ||
| 643 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | ||
| 644 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | ||
| 645 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | ||
| 646 | |||
| 647 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | ||
| 648 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | ||
| 649 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | ||
| 650 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) | ||
| 651 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) | ||
| 652 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) | ||
| 653 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | ||
| 654 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | ||
| 655 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | ||
| 656 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | ||
| 657 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | ||
| 658 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) | ||
| 659 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | ||
| 660 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) | ||
| 661 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) | ||
| 662 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) | ||
| 663 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) | ||
| 664 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) | ||
| 665 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | ||
| 666 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | ||
| 667 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | ||
| 668 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | ||
| 669 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | ||
| 670 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | ||
| 671 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | ||
| 672 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | ||
| 673 | |||
| 674 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | ||
| 675 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | ||
| 676 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | ||
| 677 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) | ||
| 678 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) | ||
| 679 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) | ||
| 680 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | ||
| 681 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | ||
| 682 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | ||
| 683 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | ||
| 684 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | ||
| 685 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) | ||
| 686 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | ||
| 687 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) | ||
| 688 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) | ||
| 689 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) | ||
| 690 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) | ||
| 691 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) | ||
| 692 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | ||
| 693 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | ||
| 694 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | ||
| 695 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | ||
| 696 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | ||
| 697 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | ||
| 698 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | ||
| 699 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | ||
| 700 | |||
| 701 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | ||
| 702 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) | ||
| 703 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | ||
| 704 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) | ||
| 705 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | ||
| 706 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) | ||
| 707 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | ||
| 708 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) | ||
| 709 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | ||
| 710 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) | ||
| 711 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | ||
| 712 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) | ||
| 713 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | ||
| 714 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) | ||
| 715 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | ||
| 716 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) | ||
| 717 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | ||
| 718 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) | ||
| 719 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | ||
| 720 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) | ||
| 721 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | ||
| 722 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) | ||
| 723 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | ||
| 724 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) | ||
| 725 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | ||
| 726 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) | ||
| 727 | |||
| 728 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | ||
| 729 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) | ||
| 730 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | ||
| 731 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) | ||
| 732 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | ||
| 733 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) | ||
| 734 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | ||
| 735 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) | ||
| 736 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | ||
| 737 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) | ||
| 738 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | ||
| 739 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) | ||
| 740 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | ||
| 741 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) | ||
| 742 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | ||
| 743 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) | ||
| 744 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | ||
| 745 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) | ||
| 746 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | ||
| 747 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) | ||
| 748 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | ||
| 749 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) | ||
| 750 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | ||
| 751 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) | ||
| 752 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | ||
| 753 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) | ||
| 754 | |||
| 755 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | ||
| 756 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) | ||
| 757 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | ||
| 758 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) | ||
| 759 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | ||
| 760 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) | ||
| 761 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | ||
| 762 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | ||
| 763 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | ||
| 764 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | ||
| 765 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | ||
| 766 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) | ||
| 767 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | ||
| 768 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) | ||
| 769 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | ||
| 770 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) | ||
| 771 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | ||
| 772 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) | ||
| 773 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | ||
| 774 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) | ||
| 775 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | ||
| 776 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) | ||
| 777 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | ||
| 778 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) | ||
| 779 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | ||
| 780 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) | ||
| 781 | |||
| 782 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | ||
| 783 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) | ||
| 784 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | ||
| 785 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) | ||
| 786 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | ||
| 787 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) | ||
| 788 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | ||
| 789 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | ||
| 790 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | ||
| 791 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | ||
| 792 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | ||
| 793 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) | ||
| 794 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | ||
| 795 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) | ||
| 796 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | ||
| 797 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) | ||
| 798 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | ||
| 799 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) | ||
| 800 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | ||
| 801 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) | ||
| 802 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | ||
| 803 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) | ||
| 804 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | ||
| 805 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) | ||
| 806 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | ||
| 807 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) | ||
| 808 | |||
| 809 | |||
| 810 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 811 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | ||
| 812 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | ||
| 813 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | ||
| 814 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | ||
| 815 | #define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) | ||
| 816 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | ||
| 817 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | ||
| 818 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | ||
| 819 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | ||
| 820 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | ||
| 821 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | ||
| 822 | |||
| 823 | |||
| 824 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 825 | |||
| 826 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 827 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) | ||
| 828 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) | ||
| 829 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) | ||
| 830 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) | ||
| 831 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) | ||
| 832 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) | ||
| 833 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) | ||
| 834 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) | ||
| 835 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) | ||
| 836 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) | ||
| 837 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) | ||
| 838 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) | ||
| 839 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) | ||
| 840 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) | ||
| 841 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) | ||
| 842 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) | ||
| 843 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) | ||
| 844 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) | ||
| 845 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) | ||
| 846 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) | ||
| 847 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) | ||
| 848 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) | ||
| 849 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) | ||
| 850 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) | ||
| 851 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) | ||
| 852 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) | ||
| 853 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) | ||
| 854 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) | ||
| 855 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) | ||
| 856 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) | ||
| 857 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) | ||
| 858 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) | ||
| 859 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) | ||
| 860 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) | ||
| 861 | |||
| 862 | |||
| 863 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 864 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) | ||
| 865 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) | ||
| 866 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) | ||
| 867 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) | ||
| 868 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) | ||
| 869 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) | ||
| 870 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) | ||
| 871 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) | ||
| 872 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) | ||
| 873 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) | ||
| 874 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) | ||
| 875 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) | ||
| 876 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) | ||
| 877 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) | ||
| 878 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) | ||
| 879 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) | ||
| 880 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) | ||
| 881 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) | ||
| 882 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) | ||
| 883 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) | ||
| 884 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) | ||
| 885 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) | ||
| 886 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) | ||
| 887 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) | ||
| 888 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) | ||
| 889 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) | ||
| 890 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) | ||
| 891 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) | ||
| 892 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) | ||
| 893 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) | ||
| 894 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) | ||
| 895 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) | ||
| 896 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) | ||
| 897 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) | ||
| 898 | |||
| 899 | |||
| 900 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 901 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | ||
| 902 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | ||
| 903 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | ||
| 904 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | ||
| 905 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | ||
| 906 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | ||
| 907 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) | ||
| 908 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) | ||
| 909 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | ||
| 910 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | ||
| 911 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) | ||
| 912 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) | ||
| 913 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | ||
| 914 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | ||
| 915 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | ||
| 916 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | ||
| 917 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | ||
| 918 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | ||
| 919 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) | ||
| 920 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) | ||
| 921 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | ||
| 922 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | ||
| 923 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | ||
| 924 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | ||
| 925 | |||
| 926 | /* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ | ||
| 927 | |||
| 928 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 929 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) | ||
| 930 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) | ||
| 931 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) | ||
| 932 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) | ||
| 933 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) | ||
| 934 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) | ||
| 935 | #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) | ||
| 936 | #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) | ||
| 937 | |||
| 938 | |||
| 939 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 940 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) | ||
| 941 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) | ||
| 942 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) | ||
| 943 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) | ||
| 944 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) | ||
| 945 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) | ||
| 946 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) | ||
| 947 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) | ||
| 948 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) | ||
| 949 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) | ||
| 950 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) | ||
| 951 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) | ||
| 952 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) | ||
| 953 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) | ||
| 954 | |||
| 955 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) | ||
| 956 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) | ||
| 957 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) | ||
| 958 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) | ||
| 959 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) | ||
| 960 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) | ||
| 961 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) | ||
| 962 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) | ||
| 963 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) | ||
| 964 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) | ||
| 965 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) | ||
| 966 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) | ||
| 967 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | ||
| 968 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) | ||
| 969 | |||
| 970 | /* ==== end from cdefBF534.h ==== */ | ||
| 971 | |||
| 972 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 973 | |||
| 974 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) | ||
| 975 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) | ||
| 976 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) | ||
| 977 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) | ||
| 978 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) | ||
| 979 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) | ||
| 980 | |||
| 981 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) | ||
| 982 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) | ||
| 983 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) | ||
| 984 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) | ||
| 985 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) | ||
| 986 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) | ||
| 987 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) | ||
| 988 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) | ||
| 989 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) | ||
| 990 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) | ||
| 991 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) | ||
| 992 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) | ||
| 993 | #define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) | ||
| 994 | #define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) | ||
| 995 | #define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) | ||
| 996 | #define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) | ||
| 997 | #define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) | ||
| 998 | #define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) | ||
| 999 | #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) | ||
| 1000 | #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) | ||
| 1001 | #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) | ||
| 1002 | #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) | ||
| 1003 | #define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) | ||
| 1004 | #define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) | ||
| 1005 | |||
| 1006 | /* HOST Port Registers */ | ||
| 1007 | |||
| 1008 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) | ||
| 1009 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) | ||
| 1010 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) | ||
| 1011 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) | ||
| 1012 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) | ||
| 1013 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) | ||
| 1014 | |||
| 1015 | /* Counter Registers */ | ||
| 1016 | |||
| 1017 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) | ||
| 1018 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) | ||
| 1019 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) | ||
| 1020 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) | ||
| 1021 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) | ||
| 1022 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) | ||
| 1023 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) | ||
| 1024 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) | ||
| 1025 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) | ||
| 1026 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) | ||
| 1027 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) | ||
| 1028 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) | ||
| 1029 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) | ||
| 1030 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) | ||
| 1031 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) | ||
| 1032 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) | ||
| 1033 | |||
| 1034 | /* Security Registers */ | ||
| 1035 | |||
| 1036 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) | ||
| 1037 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) | ||
| 1038 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) | ||
| 1039 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) | ||
| 1040 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) | ||
| 1041 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) | ||
| 1042 | |||
| 1043 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1044 | #include <asm/irq.h> | ||
| 12 | 1045 | ||
| 13 | #endif /* _CDEF_BF512_H */ | 1046 | #endif /* _CDEF_BF512_H */ |
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h deleted file mode 100644 index 178b061d0480..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ /dev/null | |||
| @@ -1,1048 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2010 Analog Devices Inc. | ||
| 3 | * | ||
| 4 | * Licensed under the GPL-2 or later | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _CDEF_BF52X_H | ||
| 8 | #define _CDEF_BF52X_H | ||
| 9 | |||
| 10 | /* ==== begin from cdefBF534.h ==== */ | ||
| 11 | |||
| 12 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 13 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | ||
| 14 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
| 15 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | ||
| 16 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
| 17 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
| 18 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | ||
| 19 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
| 20 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | ||
| 21 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
| 22 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | ||
| 23 | |||
| 24 | |||
| 25 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 26 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
| 27 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | ||
| 28 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
| 29 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | ||
| 30 | |||
| 31 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) | ||
| 32 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) | ||
| 33 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | ||
| 34 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | ||
| 35 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) | ||
| 36 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) | ||
| 37 | |||
| 38 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | ||
| 39 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | ||
| 40 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | ||
| 41 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | ||
| 42 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | ||
| 43 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | ||
| 44 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | ||
| 45 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | ||
| 46 | |||
| 47 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | ||
| 48 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | ||
| 49 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) | ||
| 50 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) | ||
| 51 | |||
| 52 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | ||
| 53 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | ||
| 54 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) | ||
| 55 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) | ||
| 56 | |||
| 57 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 58 | |||
| 59 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | ||
| 60 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | ||
| 61 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | ||
| 62 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | ||
| 63 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | ||
| 64 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | ||
| 65 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | ||
| 66 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | ||
| 67 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) | ||
| 68 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) | ||
| 69 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | ||
| 70 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | ||
| 71 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | ||
| 72 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | ||
| 73 | |||
| 74 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 75 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | ||
| 76 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | ||
| 77 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | ||
| 78 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | ||
| 79 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | ||
| 80 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | ||
| 81 | |||
| 82 | |||
| 83 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 84 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | ||
| 85 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | ||
| 86 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | ||
| 87 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | ||
| 88 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | ||
| 89 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | ||
| 90 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | ||
| 91 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | ||
| 92 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | ||
| 93 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | ||
| 94 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | ||
| 95 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) | ||
| 96 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | ||
| 97 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | ||
| 98 | |||
| 99 | |||
| 100 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 101 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | ||
| 102 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | ||
| 103 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | ||
| 104 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | ||
| 105 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | ||
| 106 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | ||
| 107 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) | ||
| 108 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) | ||
| 109 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | ||
| 110 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | ||
| 111 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) | ||
| 112 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) | ||
| 113 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | ||
| 114 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | ||
| 115 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | ||
| 116 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | ||
| 117 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | ||
| 118 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | ||
| 119 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) | ||
| 120 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) | ||
| 121 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | ||
| 122 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | ||
| 123 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | ||
| 124 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | ||
| 125 | |||
| 126 | |||
| 127 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 128 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
| 129 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | ||
| 130 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
| 131 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | ||
| 132 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
| 133 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | ||
| 134 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
| 135 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | ||
| 136 | |||
| 137 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
| 138 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | ||
| 139 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
| 140 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | ||
| 141 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
| 142 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | ||
| 143 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
| 144 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | ||
| 145 | |||
| 146 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
| 147 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | ||
| 148 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
| 149 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | ||
| 150 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
| 151 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | ||
| 152 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
| 153 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | ||
| 154 | |||
| 155 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | ||
| 156 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) | ||
| 157 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | ||
| 158 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) | ||
| 159 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | ||
| 160 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) | ||
| 161 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | ||
| 162 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) | ||
| 163 | |||
| 164 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | ||
| 165 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) | ||
| 166 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | ||
| 167 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) | ||
| 168 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | ||
| 169 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) | ||
| 170 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | ||
| 171 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) | ||
| 172 | |||
| 173 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | ||
| 174 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) | ||
| 175 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | ||
| 176 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) | ||
| 177 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | ||
| 178 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) | ||
| 179 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | ||
| 180 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) | ||
| 181 | |||
| 182 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | ||
| 183 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) | ||
| 184 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | ||
| 185 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) | ||
| 186 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | ||
| 187 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) | ||
| 188 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | ||
| 189 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) | ||
| 190 | |||
| 191 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | ||
| 192 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) | ||
| 193 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | ||
| 194 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) | ||
| 195 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | ||
| 196 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) | ||
| 197 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | ||
| 198 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) | ||
| 199 | |||
| 200 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | ||
| 201 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) | ||
| 202 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | ||
| 203 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) | ||
| 204 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) | ||
| 205 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) | ||
| 206 | |||
| 207 | |||
| 208 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 209 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) | ||
| 210 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) | ||
| 211 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) | ||
| 212 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) | ||
| 213 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) | ||
| 214 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) | ||
| 215 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) | ||
| 216 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) | ||
| 217 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) | ||
| 218 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) | ||
| 219 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) | ||
| 220 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) | ||
| 221 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) | ||
| 222 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) | ||
| 223 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) | ||
| 224 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) | ||
| 225 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) | ||
| 226 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) | ||
| 227 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) | ||
| 228 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) | ||
| 229 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) | ||
| 230 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) | ||
| 231 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) | ||
| 232 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) | ||
| 233 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) | ||
| 234 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) | ||
| 235 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) | ||
| 236 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) | ||
| 237 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) | ||
| 238 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) | ||
| 239 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) | ||
| 240 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) | ||
| 241 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) | ||
| 242 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) | ||
| 243 | |||
| 244 | |||
| 245 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 246 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 247 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
| 248 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 249 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
| 250 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 251 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
| 252 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 253 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
| 254 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 255 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
| 256 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 257 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
| 258 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) | ||
| 259 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) | ||
| 260 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) | ||
| 261 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) | ||
| 262 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) | ||
| 263 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) | ||
| 264 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) | ||
| 265 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) | ||
| 266 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 267 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
| 268 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 269 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
| 270 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 271 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
| 272 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 273 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
| 274 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 275 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
| 276 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 277 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
| 278 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 279 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
| 280 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 281 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
| 282 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 283 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
| 284 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 285 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
| 286 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 287 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
| 288 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 289 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
| 290 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 291 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
| 292 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 293 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
| 294 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 295 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
| 296 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 297 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
| 298 | |||
| 299 | |||
| 300 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 301 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
| 302 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | ||
| 303 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
| 304 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | ||
| 305 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
| 306 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | ||
| 307 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
| 308 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | ||
| 309 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
| 310 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | ||
| 311 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
| 312 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | ||
| 313 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) | ||
| 314 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) | ||
| 315 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) | ||
| 316 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) | ||
| 317 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) | ||
| 318 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) | ||
| 319 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) | ||
| 320 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) | ||
| 321 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
| 322 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | ||
| 323 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
| 324 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | ||
| 325 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
| 326 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | ||
| 327 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
| 328 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | ||
| 329 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
| 330 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | ||
| 331 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
| 332 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | ||
| 333 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
| 334 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | ||
| 335 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
| 336 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | ||
| 337 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
| 338 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | ||
| 339 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
| 340 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | ||
| 341 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
| 342 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | ||
| 343 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
| 344 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | ||
| 345 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
| 346 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | ||
| 347 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
| 348 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | ||
| 349 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
| 350 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | ||
| 351 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
| 352 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | ||
| 353 | |||
| 354 | |||
| 355 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 356 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
| 357 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | ||
| 358 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
| 359 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | ||
| 360 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
| 361 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | ||
| 362 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
| 363 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) | ||
| 364 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | ||
| 365 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) | ||
| 366 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
| 367 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) | ||
| 368 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
| 369 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) | ||
| 370 | |||
| 371 | |||
| 372 | /* DMA Traffic Control Registers */ | ||
| 373 | #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) | ||
| 374 | #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) | ||
| 375 | #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) | ||
| 376 | #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) | ||
| 377 | |||
| 378 | /* DMA Controller */ | ||
| 379 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | ||
| 380 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | ||
| 381 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | ||
| 382 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) | ||
| 383 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | ||
| 384 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) | ||
| 385 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | ||
| 386 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | ||
| 387 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | ||
| 388 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | ||
| 389 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | ||
| 390 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) | ||
| 391 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | ||
| 392 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) | ||
| 393 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | ||
| 394 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) | ||
| 395 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | ||
| 396 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) | ||
| 397 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | ||
| 398 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | ||
| 399 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | ||
| 400 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | ||
| 401 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | ||
| 402 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | ||
| 403 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | ||
| 404 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | ||
| 405 | |||
| 406 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | ||
| 407 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | ||
| 408 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | ||
| 409 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) | ||
| 410 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | ||
| 411 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) | ||
| 412 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | ||
| 413 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | ||
| 414 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | ||
| 415 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | ||
| 416 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | ||
| 417 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) | ||
| 418 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | ||
| 419 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) | ||
| 420 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | ||
| 421 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) | ||
| 422 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | ||
| 423 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) | ||
| 424 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | ||
| 425 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | ||
| 426 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | ||
| 427 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | ||
| 428 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | ||
| 429 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | ||
| 430 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | ||
| 431 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | ||
| 432 | |||
| 433 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | ||
| 434 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | ||
| 435 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | ||
| 436 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) | ||
| 437 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | ||
| 438 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) | ||
| 439 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | ||
| 440 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | ||
| 441 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | ||
| 442 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | ||
| 443 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | ||
| 444 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) | ||
| 445 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | ||
| 446 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) | ||
| 447 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | ||
| 448 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) | ||
| 449 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | ||
| 450 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) | ||
| 451 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | ||
| 452 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | ||
| 453 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | ||
| 454 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | ||
| 455 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | ||
| 456 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | ||
| 457 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | ||
| 458 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | ||
| 459 | |||
| 460 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | ||
| 461 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | ||
| 462 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | ||
| 463 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) | ||
| 464 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | ||
| 465 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) | ||
| 466 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | ||
| 467 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | ||
| 468 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | ||
| 469 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | ||
| 470 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | ||
| 471 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) | ||
| 472 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | ||
| 473 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) | ||
| 474 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | ||
| 475 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) | ||
| 476 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | ||
| 477 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) | ||
| 478 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | ||
| 479 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | ||
| 480 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | ||
| 481 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | ||
| 482 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | ||
| 483 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | ||
| 484 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | ||
| 485 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | ||
| 486 | |||
| 487 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | ||
| 488 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | ||
| 489 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | ||
| 490 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) | ||
| 491 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | ||
| 492 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) | ||
| 493 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | ||
| 494 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | ||
| 495 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | ||
| 496 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | ||
| 497 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | ||
| 498 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) | ||
| 499 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | ||
| 500 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) | ||
| 501 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | ||
| 502 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) | ||
| 503 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | ||
| 504 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) | ||
| 505 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | ||
| 506 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | ||
| 507 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | ||
| 508 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | ||
| 509 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | ||
| 510 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | ||
| 511 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | ||
| 512 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | ||
| 513 | |||
| 514 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | ||
| 515 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | ||
| 516 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | ||
| 517 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) | ||
| 518 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | ||
| 519 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) | ||
| 520 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | ||
| 521 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | ||
| 522 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | ||
| 523 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | ||
| 524 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | ||
| 525 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) | ||
| 526 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | ||
| 527 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) | ||
| 528 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | ||
| 529 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) | ||
| 530 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | ||
| 531 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) | ||
| 532 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | ||
| 533 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | ||
| 534 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | ||
| 535 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | ||
| 536 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | ||
| 537 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | ||
| 538 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | ||
| 539 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | ||
| 540 | |||
| 541 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | ||
| 542 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | ||
| 543 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | ||
| 544 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) | ||
| 545 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | ||
| 546 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) | ||
| 547 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | ||
| 548 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | ||
| 549 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | ||
| 550 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | ||
| 551 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | ||
| 552 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) | ||
| 553 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | ||
| 554 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) | ||
| 555 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | ||
| 556 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) | ||
| 557 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | ||
| 558 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) | ||
| 559 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | ||
| 560 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | ||
| 561 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | ||
| 562 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | ||
| 563 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | ||
| 564 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | ||
| 565 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | ||
| 566 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | ||
| 567 | |||
| 568 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | ||
| 569 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | ||
| 570 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | ||
| 571 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) | ||
| 572 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | ||
| 573 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) | ||
| 574 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | ||
| 575 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | ||
| 576 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | ||
| 577 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | ||
| 578 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | ||
| 579 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) | ||
| 580 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | ||
| 581 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) | ||
| 582 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | ||
| 583 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) | ||
| 584 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | ||
| 585 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) | ||
| 586 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | ||
| 587 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | ||
| 588 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | ||
| 589 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | ||
| 590 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | ||
| 591 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | ||
| 592 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | ||
| 593 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | ||
| 594 | |||
| 595 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | ||
| 596 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | ||
| 597 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | ||
| 598 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) | ||
| 599 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) | ||
| 600 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) | ||
| 601 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | ||
| 602 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | ||
| 603 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | ||
| 604 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | ||
| 605 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | ||
| 606 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) | ||
| 607 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | ||
| 608 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) | ||
| 609 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) | ||
| 610 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) | ||
| 611 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) | ||
| 612 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) | ||
| 613 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | ||
| 614 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | ||
| 615 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | ||
| 616 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | ||
| 617 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | ||
| 618 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | ||
| 619 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | ||
| 620 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | ||
| 621 | |||
| 622 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | ||
| 623 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | ||
| 624 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | ||
| 625 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) | ||
| 626 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) | ||
| 627 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) | ||
| 628 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | ||
| 629 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | ||
| 630 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | ||
| 631 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | ||
| 632 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | ||
| 633 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) | ||
| 634 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | ||
| 635 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) | ||
| 636 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) | ||
| 637 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) | ||
| 638 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) | ||
| 639 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) | ||
| 640 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | ||
| 641 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | ||
| 642 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | ||
| 643 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | ||
| 644 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | ||
| 645 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | ||
| 646 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | ||
| 647 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | ||
| 648 | |||
| 649 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | ||
| 650 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | ||
| 651 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | ||
| 652 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) | ||
| 653 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) | ||
| 654 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) | ||
| 655 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | ||
| 656 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | ||
| 657 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | ||
| 658 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | ||
| 659 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | ||
| 660 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) | ||
| 661 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | ||
| 662 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) | ||
| 663 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) | ||
| 664 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) | ||
| 665 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) | ||
| 666 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) | ||
| 667 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | ||
| 668 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | ||
| 669 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | ||
| 670 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | ||
| 671 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | ||
| 672 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | ||
| 673 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | ||
| 674 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | ||
| 675 | |||
| 676 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | ||
| 677 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | ||
| 678 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | ||
| 679 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) | ||
| 680 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) | ||
| 681 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) | ||
| 682 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | ||
| 683 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | ||
| 684 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | ||
| 685 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | ||
| 686 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | ||
| 687 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) | ||
| 688 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | ||
| 689 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) | ||
| 690 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) | ||
| 691 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) | ||
| 692 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) | ||
| 693 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) | ||
| 694 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | ||
| 695 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | ||
| 696 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | ||
| 697 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | ||
| 698 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | ||
| 699 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | ||
| 700 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | ||
| 701 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | ||
| 702 | |||
| 703 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | ||
| 704 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) | ||
| 705 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | ||
| 706 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) | ||
| 707 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | ||
| 708 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) | ||
| 709 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | ||
| 710 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) | ||
| 711 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | ||
| 712 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) | ||
| 713 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | ||
| 714 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) | ||
| 715 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | ||
| 716 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) | ||
| 717 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | ||
| 718 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) | ||
| 719 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | ||
| 720 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) | ||
| 721 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | ||
| 722 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) | ||
| 723 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | ||
| 724 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) | ||
| 725 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | ||
| 726 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) | ||
| 727 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | ||
| 728 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) | ||
| 729 | |||
| 730 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | ||
| 731 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) | ||
| 732 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | ||
| 733 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) | ||
| 734 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | ||
| 735 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) | ||
| 736 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | ||
| 737 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) | ||
| 738 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | ||
| 739 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) | ||
| 740 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | ||
| 741 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) | ||
| 742 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | ||
| 743 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) | ||
| 744 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | ||
| 745 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) | ||
| 746 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | ||
| 747 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) | ||
| 748 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | ||
| 749 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) | ||
| 750 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | ||
| 751 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) | ||
| 752 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | ||
| 753 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) | ||
| 754 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | ||
| 755 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) | ||
| 756 | |||
| 757 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | ||
| 758 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) | ||
| 759 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | ||
| 760 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) | ||
| 761 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | ||
| 762 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) | ||
| 763 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | ||
| 764 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | ||
| 765 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | ||
| 766 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | ||
| 767 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | ||
| 768 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) | ||
| 769 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | ||
| 770 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) | ||
| 771 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | ||
| 772 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) | ||
| 773 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | ||
| 774 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) | ||
| 775 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | ||
| 776 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) | ||
| 777 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | ||
| 778 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) | ||
| 779 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | ||
| 780 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) | ||
| 781 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | ||
| 782 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) | ||
| 783 | |||
| 784 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | ||
| 785 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) | ||
| 786 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | ||
| 787 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) | ||
| 788 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | ||
| 789 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) | ||
| 790 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | ||
| 791 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | ||
| 792 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | ||
| 793 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | ||
| 794 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | ||
| 795 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) | ||
| 796 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | ||
| 797 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) | ||
| 798 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | ||
| 799 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) | ||
| 800 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | ||
| 801 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) | ||
| 802 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | ||
| 803 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) | ||
| 804 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | ||
| 805 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) | ||
| 806 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | ||
| 807 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) | ||
| 808 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | ||
| 809 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) | ||
| 810 | |||
| 811 | |||
| 812 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 813 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | ||
| 814 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | ||
| 815 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | ||
| 816 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | ||
| 817 | #define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) | ||
| 818 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | ||
| 819 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | ||
| 820 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | ||
| 821 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | ||
| 822 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | ||
| 823 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | ||
| 824 | |||
| 825 | |||
| 826 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 827 | |||
| 828 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 829 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) | ||
| 830 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) | ||
| 831 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) | ||
| 832 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) | ||
| 833 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) | ||
| 834 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) | ||
| 835 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) | ||
| 836 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) | ||
| 837 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) | ||
| 838 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) | ||
| 839 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) | ||
| 840 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) | ||
| 841 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) | ||
| 842 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) | ||
| 843 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) | ||
| 844 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) | ||
| 845 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) | ||
| 846 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) | ||
| 847 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) | ||
| 848 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) | ||
| 849 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) | ||
| 850 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) | ||
| 851 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) | ||
| 852 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) | ||
| 853 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) | ||
| 854 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) | ||
| 855 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) | ||
| 856 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) | ||
| 857 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) | ||
| 858 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) | ||
| 859 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) | ||
| 860 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) | ||
| 861 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) | ||
| 862 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) | ||
| 863 | |||
| 864 | |||
| 865 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 866 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) | ||
| 867 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) | ||
| 868 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) | ||
| 869 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) | ||
| 870 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) | ||
| 871 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) | ||
| 872 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) | ||
| 873 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) | ||
| 874 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) | ||
| 875 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) | ||
| 876 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) | ||
| 877 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) | ||
| 878 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) | ||
| 879 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) | ||
| 880 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) | ||
| 881 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) | ||
| 882 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) | ||
| 883 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) | ||
| 884 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) | ||
| 885 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) | ||
| 886 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) | ||
| 887 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) | ||
| 888 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) | ||
| 889 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) | ||
| 890 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) | ||
| 891 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) | ||
| 892 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) | ||
| 893 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) | ||
| 894 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) | ||
| 895 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) | ||
| 896 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) | ||
| 897 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) | ||
| 898 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) | ||
| 899 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) | ||
| 900 | |||
| 901 | |||
| 902 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 903 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | ||
| 904 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | ||
| 905 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | ||
| 906 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | ||
| 907 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | ||
| 908 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | ||
| 909 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) | ||
| 910 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) | ||
| 911 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | ||
| 912 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | ||
| 913 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) | ||
| 914 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) | ||
| 915 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | ||
| 916 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | ||
| 917 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | ||
| 918 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | ||
| 919 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | ||
| 920 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | ||
| 921 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) | ||
| 922 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) | ||
| 923 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | ||
| 924 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | ||
| 925 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | ||
| 926 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | ||
| 927 | |||
| 928 | /* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ | ||
| 929 | |||
| 930 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 931 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) | ||
| 932 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) | ||
| 933 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) | ||
| 934 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) | ||
| 935 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) | ||
| 936 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) | ||
| 937 | #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) | ||
| 938 | #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) | ||
| 939 | |||
| 940 | |||
| 941 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 942 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) | ||
| 943 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) | ||
| 944 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) | ||
| 945 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) | ||
| 946 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) | ||
| 947 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) | ||
| 948 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) | ||
| 949 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) | ||
| 950 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) | ||
| 951 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) | ||
| 952 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) | ||
| 953 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) | ||
| 954 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) | ||
| 955 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) | ||
| 956 | |||
| 957 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) | ||
| 958 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) | ||
| 959 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) | ||
| 960 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) | ||
| 961 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) | ||
| 962 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) | ||
| 963 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) | ||
| 964 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) | ||
| 965 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) | ||
| 966 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) | ||
| 967 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) | ||
| 968 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) | ||
| 969 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | ||
| 970 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) | ||
| 971 | |||
| 972 | /* ==== end from cdefBF534.h ==== */ | ||
| 973 | |||
| 974 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 975 | |||
| 976 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) | ||
| 977 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) | ||
| 978 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) | ||
| 979 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) | ||
| 980 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) | ||
| 981 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) | ||
| 982 | |||
| 983 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) | ||
| 984 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) | ||
| 985 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) | ||
| 986 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) | ||
| 987 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) | ||
| 988 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) | ||
| 989 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) | ||
| 990 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) | ||
| 991 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) | ||
| 992 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) | ||
| 993 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) | ||
| 994 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) | ||
| 995 | #define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) | ||
| 996 | #define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) | ||
| 997 | #define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) | ||
| 998 | #define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) | ||
| 999 | #define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) | ||
| 1000 | #define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) | ||
| 1001 | #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) | ||
| 1002 | #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) | ||
| 1003 | #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) | ||
| 1004 | #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) | ||
| 1005 | #define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) | ||
| 1006 | #define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) | ||
| 1007 | |||
| 1008 | /* HOST Port Registers */ | ||
| 1009 | |||
| 1010 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) | ||
| 1011 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) | ||
| 1012 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) | ||
| 1013 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) | ||
| 1014 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) | ||
| 1015 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) | ||
| 1016 | |||
| 1017 | /* Counter Registers */ | ||
| 1018 | |||
| 1019 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) | ||
| 1020 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) | ||
| 1021 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) | ||
| 1022 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) | ||
| 1023 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) | ||
| 1024 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) | ||
| 1025 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) | ||
| 1026 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) | ||
| 1027 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) | ||
| 1028 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) | ||
| 1029 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) | ||
| 1030 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) | ||
| 1031 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) | ||
| 1032 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) | ||
| 1033 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) | ||
| 1034 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) | ||
| 1035 | |||
| 1036 | /* Security Registers */ | ||
| 1037 | |||
| 1038 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) | ||
| 1039 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) | ||
| 1040 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) | ||
| 1041 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) | ||
| 1042 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) | ||
| 1043 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) | ||
| 1044 | |||
| 1045 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1046 | #include <asm/irq.h> | ||
| 1047 | |||
| 1048 | #endif /* _CDEF_BF52X_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h index a2b3c2ebc6e0..27285823fb25 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h | |||
| @@ -7,7 +7,1388 @@ | |||
| 7 | #ifndef _DEF_BF512_H | 7 | #ifndef _DEF_BF512_H |
| 8 | #define _DEF_BF512_H | 8 | #define _DEF_BF512_H |
| 9 | 9 | ||
| 10 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | 10 | /* ************************************************************** */ |
| 11 | #include "defBF51x_base.h" | 11 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ |
| 12 | /* ************************************************************** */ | ||
| 13 | |||
| 14 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 15 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ | ||
| 16 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ | ||
| 17 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ | ||
| 18 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ | ||
| 19 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ | ||
| 20 | #define CHIPID 0xFFC00014 /* Device ID Register */ | ||
| 21 | |||
| 22 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 23 | #define SWRST 0xFFC00100 /* Software Reset Register */ | ||
| 24 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | ||
| 25 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | ||
| 26 | |||
| 27 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | ||
| 28 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | ||
| 29 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | ||
| 30 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | ||
| 31 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | ||
| 32 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | ||
| 33 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | ||
| 34 | |||
| 35 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 36 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | ||
| 37 | #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ | ||
| 38 | #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ | ||
| 39 | #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ | ||
| 40 | #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ | ||
| 41 | #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ | ||
| 42 | #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ | ||
| 43 | |||
| 44 | |||
| 45 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 46 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | ||
| 47 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | ||
| 48 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | ||
| 49 | |||
| 50 | |||
| 51 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 52 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | ||
| 53 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | ||
| 54 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | ||
| 55 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | ||
| 56 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | ||
| 57 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | ||
| 58 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ | ||
| 59 | |||
| 60 | |||
| 61 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 62 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | ||
| 63 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | ||
| 64 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
| 65 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
| 66 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
| 67 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
| 68 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | ||
| 69 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | ||
| 70 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | ||
| 71 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ | ||
| 72 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
| 73 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | ||
| 74 | |||
| 75 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 76 | #define SPI0_REGBASE 0xFFC00500 | ||
| 77 | #define SPI0_CTL 0xFFC00500 /* SPI Control Register */ | ||
| 78 | #define SPI0_FLG 0xFFC00504 /* SPI Flag register */ | ||
| 79 | #define SPI0_STAT 0xFFC00508 /* SPI Status register */ | ||
| 80 | #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | ||
| 81 | #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | ||
| 82 | #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ | ||
| 83 | #define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | ||
| 84 | |||
| 85 | /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ | ||
| 86 | #define SPI1_REGBASE 0xFFC03400 | ||
| 87 | #define SPI1_CTL 0xFFC03400 /* SPI Control Register */ | ||
| 88 | #define SPI1_FLG 0xFFC03404 /* SPI Flag register */ | ||
| 89 | #define SPI1_STAT 0xFFC03408 /* SPI Status register */ | ||
| 90 | #define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ | ||
| 91 | #define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ | ||
| 92 | #define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ | ||
| 93 | #define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ | ||
| 94 | |||
| 95 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 96 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | ||
| 97 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | ||
| 98 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | ||
| 99 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | ||
| 100 | |||
| 101 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | ||
| 102 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | ||
| 103 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | ||
| 104 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | ||
| 105 | |||
| 106 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | ||
| 107 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | ||
| 108 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | ||
| 109 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | ||
| 110 | |||
| 111 | #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ | ||
| 112 | #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ | ||
| 113 | #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ | ||
| 114 | #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ | ||
| 115 | |||
| 116 | #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ | ||
| 117 | #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ | ||
| 118 | #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ | ||
| 119 | #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ | ||
| 120 | |||
| 121 | #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ | ||
| 122 | #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ | ||
| 123 | #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ | ||
| 124 | #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ | ||
| 125 | |||
| 126 | #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ | ||
| 127 | #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ | ||
| 128 | #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ | ||
| 129 | #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ | ||
| 130 | |||
| 131 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | ||
| 132 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | ||
| 133 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | ||
| 134 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | ||
| 135 | |||
| 136 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | ||
| 137 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | ||
| 138 | #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ | ||
| 139 | |||
| 140 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 141 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ | ||
| 142 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ | ||
| 143 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ | ||
| 144 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ | ||
| 145 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ | ||
| 146 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ | ||
| 147 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ | ||
| 148 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ | ||
| 149 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ | ||
| 150 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ | ||
| 151 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ | ||
| 152 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ | ||
| 153 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ | ||
| 154 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ | ||
| 155 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ | ||
| 156 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ | ||
| 157 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ | ||
| 158 | |||
| 159 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 160 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 161 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 162 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
| 163 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
| 164 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
| 165 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
| 166 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 167 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 168 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
| 169 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
| 170 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
| 171 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
| 172 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
| 173 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
| 174 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
| 175 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
| 176 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
| 177 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
| 178 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
| 179 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
| 180 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
| 181 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
| 182 | |||
| 183 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 184 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 185 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 186 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
| 187 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
| 188 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
| 189 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
| 190 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 191 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 192 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
| 193 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
| 194 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
| 195 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
| 196 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
| 197 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
| 198 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
| 199 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
| 200 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
| 201 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
| 202 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
| 203 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
| 204 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
| 205 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
| 206 | |||
| 207 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 208 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
| 209 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
| 210 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
| 211 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
| 212 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
| 213 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
| 214 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
| 215 | |||
| 216 | /* DMA Traffic Control Registers */ | ||
| 217 | #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 218 | #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 219 | |||
| 220 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | ||
| 221 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
| 222 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | ||
| 223 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | ||
| 224 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | ||
| 225 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | ||
| 226 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | ||
| 227 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | ||
| 228 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
| 229 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | ||
| 230 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | ||
| 231 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | ||
| 232 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | ||
| 233 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | ||
| 234 | |||
| 235 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
| 236 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | ||
| 237 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | ||
| 238 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | ||
| 239 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | ||
| 240 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | ||
| 241 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | ||
| 242 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
| 243 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | ||
| 244 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | ||
| 245 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | ||
| 246 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | ||
| 247 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | ||
| 248 | |||
| 249 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
| 250 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | ||
| 251 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | ||
| 252 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | ||
| 253 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | ||
| 254 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | ||
| 255 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | ||
| 256 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
| 257 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | ||
| 258 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | ||
| 259 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | ||
| 260 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | ||
| 261 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | ||
| 262 | |||
| 263 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
| 264 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | ||
| 265 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | ||
| 266 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | ||
| 267 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | ||
| 268 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | ||
| 269 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | ||
| 270 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
| 271 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | ||
| 272 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | ||
| 273 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | ||
| 274 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | ||
| 275 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | ||
| 276 | |||
| 277 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
| 278 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | ||
| 279 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | ||
| 280 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | ||
| 281 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | ||
| 282 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | ||
| 283 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | ||
| 284 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
| 285 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | ||
| 286 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | ||
| 287 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | ||
| 288 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | ||
| 289 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | ||
| 290 | |||
| 291 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
| 292 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | ||
| 293 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | ||
| 294 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | ||
| 295 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | ||
| 296 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | ||
| 297 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | ||
| 298 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
| 299 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | ||
| 300 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | ||
| 301 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | ||
| 302 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | ||
| 303 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | ||
| 304 | |||
| 305 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
| 306 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | ||
| 307 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | ||
| 308 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | ||
| 309 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | ||
| 310 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | ||
| 311 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | ||
| 312 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
| 313 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | ||
| 314 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | ||
| 315 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | ||
| 316 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | ||
| 317 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | ||
| 318 | |||
| 319 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
| 320 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | ||
| 321 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | ||
| 322 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | ||
| 323 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | ||
| 324 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | ||
| 325 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | ||
| 326 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
| 327 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | ||
| 328 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | ||
| 329 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | ||
| 330 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | ||
| 331 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | ||
| 332 | |||
| 333 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
| 334 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ | ||
| 335 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ | ||
| 336 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ | ||
| 337 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ | ||
| 338 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ | ||
| 339 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ | ||
| 340 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
| 341 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ | ||
| 342 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ | ||
| 343 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ | ||
| 344 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ | ||
| 345 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ | ||
| 346 | |||
| 347 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
| 348 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ | ||
| 349 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ | ||
| 350 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ | ||
| 351 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ | ||
| 352 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ | ||
| 353 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ | ||
| 354 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
| 355 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ | ||
| 356 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ | ||
| 357 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ | ||
| 358 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ | ||
| 359 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ | ||
| 360 | |||
| 361 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
| 362 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ | ||
| 363 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ | ||
| 364 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ | ||
| 365 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ | ||
| 366 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ | ||
| 367 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ | ||
| 368 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
| 369 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ | ||
| 370 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ | ||
| 371 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ | ||
| 372 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ | ||
| 373 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ | ||
| 374 | |||
| 375 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
| 376 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ | ||
| 377 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ | ||
| 378 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ | ||
| 379 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ | ||
| 380 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ | ||
| 381 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ | ||
| 382 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
| 383 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ | ||
| 384 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ | ||
| 385 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ | ||
| 386 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ | ||
| 387 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ | ||
| 388 | |||
| 389 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | ||
| 390 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ | ||
| 391 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ | ||
| 392 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ | ||
| 393 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ | ||
| 394 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ | ||
| 395 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ | ||
| 396 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | ||
| 397 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ | ||
| 398 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | ||
| 399 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | ||
| 400 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ | ||
| 401 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ | ||
| 402 | |||
| 403 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | ||
| 404 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ | ||
| 405 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ | ||
| 406 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ | ||
| 407 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ | ||
| 408 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ | ||
| 409 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ | ||
| 410 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | ||
| 411 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ | ||
| 412 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | ||
| 413 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ | ||
| 414 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ | ||
| 415 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ | ||
| 416 | |||
| 417 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | ||
| 418 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ | ||
| 419 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ | ||
| 420 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ | ||
| 421 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ | ||
| 422 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ | ||
| 423 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ | ||
| 424 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | ||
| 425 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ | ||
| 426 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | ||
| 427 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | ||
| 428 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ | ||
| 429 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | ||
| 430 | |||
| 431 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | ||
| 432 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ | ||
| 433 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ | ||
| 434 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ | ||
| 435 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ | ||
| 436 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ | ||
| 437 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ | ||
| 438 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | ||
| 439 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ | ||
| 440 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | ||
| 441 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ | ||
| 442 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ | ||
| 443 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ | ||
| 444 | |||
| 445 | |||
| 446 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 447 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | ||
| 448 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | ||
| 449 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | ||
| 450 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | ||
| 451 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | ||
| 452 | |||
| 453 | |||
| 454 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 455 | #define TWI0_REGBASE 0xFFC01400 | ||
| 456 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | ||
| 457 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ | ||
| 458 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | ||
| 459 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | ||
| 460 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | ||
| 461 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | ||
| 462 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | ||
| 463 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | ||
| 464 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | ||
| 465 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | ||
| 466 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | ||
| 467 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | ||
| 468 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | ||
| 469 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | ||
| 470 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | ||
| 471 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | ||
| 472 | |||
| 473 | |||
| 474 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 475 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | ||
| 476 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ | ||
| 477 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ | ||
| 478 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ | ||
| 479 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ | ||
| 480 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ | ||
| 481 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ | ||
| 482 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ | ||
| 483 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ | ||
| 484 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ | ||
| 485 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ | ||
| 486 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ | ||
| 487 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ | ||
| 488 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ | ||
| 489 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ | ||
| 490 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ | ||
| 491 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ | ||
| 492 | |||
| 493 | |||
| 494 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 495 | #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ | ||
| 496 | #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ | ||
| 497 | #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ | ||
| 498 | #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ | ||
| 499 | #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ | ||
| 500 | #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ | ||
| 501 | #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ | ||
| 502 | #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ | ||
| 503 | #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ | ||
| 504 | #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ | ||
| 505 | #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ | ||
| 506 | #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ | ||
| 507 | #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ | ||
| 508 | #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ | ||
| 509 | #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ | ||
| 510 | #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ | ||
| 511 | #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ | ||
| 512 | |||
| 513 | |||
| 514 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 515 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | ||
| 516 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | ||
| 517 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | ||
| 518 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | ||
| 519 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | ||
| 520 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | ||
| 521 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | ||
| 522 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | ||
| 523 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | ||
| 524 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ | ||
| 525 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | ||
| 526 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | ||
| 527 | |||
| 528 | |||
| 529 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 530 | #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ | ||
| 531 | #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ | ||
| 532 | #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ | ||
| 533 | #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ | ||
| 534 | |||
| 535 | |||
| 536 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 537 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | ||
| 538 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | ||
| 539 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | ||
| 540 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ | ||
| 541 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ | ||
| 542 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | ||
| 543 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | ||
| 544 | |||
| 545 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | ||
| 546 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | ||
| 547 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | ||
| 548 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ | ||
| 549 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ | ||
| 550 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | ||
| 551 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | ||
| 552 | |||
| 553 | |||
| 554 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 555 | #define PORTF_MUX 0xFFC03210 /* Port F mux control */ | ||
| 556 | #define PORTG_MUX 0xFFC03214 /* Port G mux control */ | ||
| 557 | #define PORTH_MUX 0xFFC03218 /* Port H mux control */ | ||
| 558 | #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ | ||
| 559 | #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ | ||
| 560 | #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ | ||
| 561 | #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ | ||
| 562 | #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ | ||
| 563 | #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ | ||
| 564 | #define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ | ||
| 565 | #define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ | ||
| 566 | #define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ | ||
| 567 | #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ | ||
| 568 | #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ | ||
| 569 | #define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ | ||
| 570 | |||
| 571 | |||
| 572 | /*********************************************************************************** | ||
| 573 | ** System MMR Register Bits And Macros | ||
| 574 | ** | ||
| 575 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 576 | ** Use these macros carefully, as any that do left shifts for field | ||
| 577 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 578 | ** macro that shifts left to properly position the bit-field should be | ||
| 579 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 580 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 581 | ** the macro is used. | ||
| 582 | *************************************************************************************/ | ||
| 583 | |||
| 584 | /* CHIPID Masks */ | ||
| 585 | #define CHIPID_VERSION 0xF0000000 | ||
| 586 | #define CHIPID_FAMILY 0x0FFFF000 | ||
| 587 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
| 588 | |||
| 589 | /* SWRST Masks */ | ||
| 590 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | ||
| 591 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | ||
| 592 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | ||
| 593 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | ||
| 594 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | ||
| 595 | |||
| 596 | /* SYSCR Masks */ | ||
| 597 | #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ | ||
| 598 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | ||
| 599 | |||
| 600 | |||
| 601 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | ||
| 602 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | ||
| 603 | |||
| 604 | #if 0 | ||
| 605 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | ||
| 606 | |||
| 607 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | ||
| 608 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | ||
| 609 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | ||
| 610 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | ||
| 611 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | ||
| 612 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | ||
| 613 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | ||
| 614 | |||
| 615 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | ||
| 616 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | ||
| 617 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | ||
| 618 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | ||
| 619 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | ||
| 620 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | ||
| 621 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | ||
| 622 | #define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ | ||
| 623 | |||
| 624 | #define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ | ||
| 625 | #define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ | ||
| 626 | #define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ | ||
| 627 | #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ | ||
| 628 | #define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ | ||
| 629 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ | ||
| 630 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ | ||
| 631 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ | ||
| 632 | #define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ | ||
| 633 | #define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ | ||
| 634 | |||
| 635 | #define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ | ||
| 636 | #define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ | ||
| 637 | #define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ | ||
| 638 | #define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ | ||
| 639 | #define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ | ||
| 640 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ | ||
| 641 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ | ||
| 642 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ | ||
| 643 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | ||
| 644 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | ||
| 645 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | ||
| 646 | #endif | ||
| 647 | |||
| 648 | /* SIC_IAR0 Macros */ | ||
| 649 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | ||
| 650 | #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | ||
| 651 | #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | ||
| 652 | #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | ||
| 653 | #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | ||
| 654 | #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | ||
| 655 | #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | ||
| 656 | #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | ||
| 657 | |||
| 658 | /* SIC_IAR1 Macros */ | ||
| 659 | #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ | ||
| 660 | #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | ||
| 661 | #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | ||
| 662 | #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | ||
| 663 | #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | ||
| 664 | #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | ||
| 665 | #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | ||
| 666 | #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | ||
| 667 | |||
| 668 | /* SIC_IAR2 Macros */ | ||
| 669 | #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ | ||
| 670 | #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | ||
| 671 | #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | ||
| 672 | #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | ||
| 673 | #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | ||
| 674 | #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | ||
| 675 | #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | ||
| 676 | #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | ||
| 677 | |||
| 678 | /* SIC_IAR3 Macros */ | ||
| 679 | #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ | ||
| 680 | #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ | ||
| 681 | #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ | ||
| 682 | #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ | ||
| 683 | #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ | ||
| 684 | #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ | ||
| 685 | #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ | ||
| 686 | #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ | ||
| 687 | |||
| 688 | |||
| 689 | /* SIC_IMASK Masks */ | ||
| 690 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 691 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 692 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | ||
| 693 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | ||
| 694 | |||
| 695 | /* SIC_IWR Masks */ | ||
| 696 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 697 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 698 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | ||
| 699 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | ||
| 700 | |||
| 701 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | ||
| 702 | /* TIMER_ENABLE Masks */ | ||
| 703 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | ||
| 704 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | ||
| 705 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | ||
| 706 | #define TIMEN3 0x0008 /* Enable Timer 3 */ | ||
| 707 | #define TIMEN4 0x0010 /* Enable Timer 4 */ | ||
| 708 | #define TIMEN5 0x0020 /* Enable Timer 5 */ | ||
| 709 | #define TIMEN6 0x0040 /* Enable Timer 6 */ | ||
| 710 | #define TIMEN7 0x0080 /* Enable Timer 7 */ | ||
| 711 | |||
| 712 | /* TIMER_DISABLE Masks */ | ||
| 713 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ | ||
| 714 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ | ||
| 715 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ | ||
| 716 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ | ||
| 717 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ | ||
| 718 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ | ||
| 719 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ | ||
| 720 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ | ||
| 721 | |||
| 722 | /* TIMER_STATUS Masks */ | ||
| 723 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ | ||
| 724 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ | ||
| 725 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ | ||
| 726 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ | ||
| 727 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ | ||
| 728 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ | ||
| 729 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ | ||
| 730 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ | ||
| 731 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ | ||
| 732 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ | ||
| 733 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ | ||
| 734 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ | ||
| 735 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ | ||
| 736 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ | ||
| 737 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ | ||
| 738 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ | ||
| 739 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ | ||
| 740 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ | ||
| 741 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ | ||
| 742 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ | ||
| 743 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | ||
| 744 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | ||
| 745 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | ||
| 746 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | ||
| 747 | |||
| 748 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 749 | #define TOVL_ERR0 TOVF_ERR0 | ||
| 750 | #define TOVL_ERR1 TOVF_ERR1 | ||
| 751 | #define TOVL_ERR2 TOVF_ERR2 | ||
| 752 | #define TOVL_ERR3 TOVF_ERR3 | ||
| 753 | #define TOVL_ERR4 TOVF_ERR4 | ||
| 754 | #define TOVL_ERR5 TOVF_ERR5 | ||
| 755 | #define TOVL_ERR6 TOVF_ERR6 | ||
| 756 | #define TOVL_ERR7 TOVF_ERR7 | ||
| 757 | |||
| 758 | /* TIMERx_CONFIG Masks */ | ||
| 759 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ | ||
| 760 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ | ||
| 761 | #define EXT_CLK 0x0003 /* External Clock Mode */ | ||
| 762 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ | ||
| 763 | #define PERIOD_CNT 0x0008 /* Period Count */ | ||
| 764 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ | ||
| 765 | #define TIN_SEL 0x0020 /* Timer Input Select */ | ||
| 766 | #define OUT_DIS 0x0040 /* Output Pad Disable */ | ||
| 767 | #define CLK_SEL 0x0080 /* Timer Clock Select */ | ||
| 768 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ | ||
| 769 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ | ||
| 770 | #define ERR_TYP 0xC000 /* Error Type */ | ||
| 771 | |||
| 772 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | ||
| 773 | /* EBIU_AMGCTL Masks */ | ||
| 774 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 775 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
| 776 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | ||
| 777 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | ||
| 778 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | ||
| 779 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 780 | |||
| 781 | /* EBIU_AMBCTL0 Masks */ | ||
| 782 | #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ | ||
| 783 | #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ | ||
| 784 | #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ | ||
| 785 | #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ | ||
| 786 | #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ | ||
| 787 | #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ | ||
| 788 | #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 789 | #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 790 | #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 791 | #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 792 | #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 793 | #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 794 | #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 795 | #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 796 | #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ | ||
| 797 | #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ | ||
| 798 | #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ | ||
| 799 | #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ | ||
| 800 | #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ | ||
| 801 | #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ | ||
| 802 | #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ | ||
| 803 | #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ | ||
| 804 | #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ | ||
| 805 | #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ | ||
| 806 | #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ | ||
| 807 | #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ | ||
| 808 | #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ | ||
| 809 | #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ | ||
| 810 | #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ | ||
| 811 | #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ | ||
| 812 | #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ | ||
| 813 | #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ | ||
| 814 | #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ | ||
| 815 | #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ | ||
| 816 | #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ | ||
| 817 | #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ | ||
| 818 | #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ | ||
| 819 | #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ | ||
| 820 | #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ | ||
| 821 | #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ | ||
| 822 | #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ | ||
| 823 | #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ | ||
| 824 | #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ | ||
| 825 | #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ | ||
| 826 | |||
| 827 | #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ | ||
| 828 | #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ | ||
| 829 | #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ | ||
| 830 | #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ | ||
| 831 | #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ | ||
| 832 | #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ | ||
| 833 | #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 834 | #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 835 | #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 836 | #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 837 | #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 838 | #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 839 | #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 840 | #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 841 | #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ | ||
| 842 | #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ | ||
| 843 | #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ | ||
| 844 | #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ | ||
| 845 | #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ | ||
| 846 | #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ | ||
| 847 | #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ | ||
| 848 | #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ | ||
| 849 | #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ | ||
| 850 | #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ | ||
| 851 | #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ | ||
| 852 | #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ | ||
| 853 | #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ | ||
| 854 | #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ | ||
| 855 | #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ | ||
| 856 | #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ | ||
| 857 | #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ | ||
| 858 | #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ | ||
| 859 | #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ | ||
| 860 | #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ | ||
| 861 | #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ | ||
| 862 | #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ | ||
| 863 | #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ | ||
| 864 | #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ | ||
| 865 | #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ | ||
| 866 | #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ | ||
| 867 | #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ | ||
| 868 | #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ | ||
| 869 | #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ | ||
| 870 | #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ | ||
| 871 | |||
| 872 | /* EBIU_AMBCTL1 Masks */ | ||
| 873 | #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ | ||
| 874 | #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ | ||
| 875 | #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ | ||
| 876 | #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ | ||
| 877 | #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ | ||
| 878 | #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ | ||
| 879 | #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 880 | #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 881 | #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 882 | #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 883 | #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 884 | #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 885 | #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 886 | #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 887 | #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ | ||
| 888 | #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ | ||
| 889 | #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ | ||
| 890 | #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ | ||
| 891 | #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ | ||
| 892 | #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ | ||
| 893 | #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ | ||
| 894 | #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ | ||
| 895 | #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ | ||
| 896 | #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ | ||
| 897 | #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ | ||
| 898 | #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ | ||
| 899 | #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ | ||
| 900 | #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ | ||
| 901 | #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ | ||
| 902 | #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ | ||
| 903 | #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ | ||
| 904 | #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ | ||
| 905 | #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ | ||
| 906 | #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ | ||
| 907 | #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ | ||
| 908 | #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ | ||
| 909 | #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ | ||
| 910 | #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ | ||
| 911 | #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ | ||
| 912 | #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ | ||
| 913 | #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ | ||
| 914 | #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ | ||
| 915 | #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ | ||
| 916 | #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ | ||
| 917 | |||
| 918 | #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ | ||
| 919 | #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ | ||
| 920 | #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ | ||
| 921 | #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ | ||
| 922 | #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ | ||
| 923 | #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ | ||
| 924 | #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 925 | #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 926 | #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 927 | #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 928 | #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 929 | #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 930 | #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 931 | #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 932 | #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ | ||
| 933 | #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ | ||
| 934 | #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ | ||
| 935 | #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ | ||
| 936 | #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ | ||
| 937 | #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ | ||
| 938 | #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ | ||
| 939 | #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ | ||
| 940 | #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ | ||
| 941 | #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ | ||
| 942 | #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ | ||
| 943 | #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ | ||
| 944 | #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ | ||
| 945 | #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ | ||
| 946 | #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ | ||
| 947 | #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ | ||
| 948 | #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ | ||
| 949 | #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ | ||
| 950 | #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ | ||
| 951 | #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ | ||
| 952 | #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ | ||
| 953 | #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ | ||
| 954 | #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ | ||
| 955 | #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ | ||
| 956 | #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ | ||
| 957 | #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ | ||
| 958 | #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ | ||
| 959 | #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ | ||
| 960 | #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ | ||
| 961 | #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ | ||
| 962 | |||
| 963 | |||
| 964 | /* ********************** SDRAM CONTROLLER MASKS **********************************************/ | ||
| 965 | /* EBIU_SDGCTL Masks */ | ||
| 966 | #define SCTLE 0x00000001 /* Enable SDRAM Signals */ | ||
| 967 | #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ | ||
| 968 | #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ | ||
| 969 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | ||
| 970 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | ||
| 971 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | ||
| 972 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
| 973 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
| 974 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
| 975 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
| 976 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
| 977 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
| 978 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
| 979 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
| 980 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
| 981 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
| 982 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
| 983 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
| 984 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
| 985 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
| 986 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
| 987 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
| 988 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
| 989 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
| 990 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
| 991 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
| 992 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
| 993 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
| 994 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
| 995 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
| 996 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
| 997 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
| 998 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
| 999 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
| 1000 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
| 1001 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
| 1002 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
| 1003 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
| 1004 | #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ | ||
| 1005 | #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ | ||
| 1006 | #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ | ||
| 1007 | #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ | ||
| 1008 | #define EBUFE 0x02000000 /* Enable External Buffering Timing */ | ||
| 1009 | #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ | ||
| 1010 | #define EMREN 0x10000000 /* Extended Mode Register Enable */ | ||
| 1011 | #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ | ||
| 1012 | #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ | ||
| 1013 | |||
| 1014 | /* EBIU_SDBCTL Masks */ | ||
| 1015 | #define EBE 0x0001 /* Enable SDRAM External Bank */ | ||
| 1016 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ | ||
| 1017 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ | ||
| 1018 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ | ||
| 1019 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ | ||
| 1020 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ | ||
| 1021 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ | ||
| 1022 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ | ||
| 1023 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ | ||
| 1024 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ | ||
| 1025 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ | ||
| 1026 | |||
| 1027 | /* EBIU_SDSTAT Masks */ | ||
| 1028 | #define SDCI 0x0001 /* SDRAM Controller Idle */ | ||
| 1029 | #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ | ||
| 1030 | #define SDPUA 0x0004 /* SDRAM Power-Up Active */ | ||
| 1031 | #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ | ||
| 1032 | #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ | ||
| 1033 | #define BGSTAT 0x0020 /* Bus Grant Status */ | ||
| 1034 | |||
| 1035 | |||
| 1036 | /* ************************** DMA CONTROLLER MASKS ********************************/ | ||
| 1037 | |||
| 1038 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | ||
| 1039 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | ||
| 1040 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ | ||
| 1041 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ | ||
| 1042 | #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ | ||
| 1043 | #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ | ||
| 1044 | #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ | ||
| 1045 | #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ | ||
| 1046 | #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ | ||
| 1047 | #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ | ||
| 1048 | #define PMAP_SPI 0x7000 /* SPI Port DMA */ | ||
| 1049 | #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ | ||
| 1050 | #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ | ||
| 1051 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | ||
| 1052 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | ||
| 1053 | |||
| 1054 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | ||
| 1055 | /* PPI_CONTROL Masks */ | ||
| 1056 | #define PORT_EN 0x0001 /* PPI Port Enable */ | ||
| 1057 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | ||
| 1058 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | ||
| 1059 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | ||
| 1060 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | ||
| 1061 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | ||
| 1062 | #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ | ||
| 1063 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | ||
| 1064 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | ||
| 1065 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | ||
| 1066 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | ||
| 1067 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | ||
| 1068 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | ||
| 1069 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | ||
| 1070 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | ||
| 1071 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | ||
| 1072 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | ||
| 1073 | #define DLENGTH 0x3800 /* PPI Data Length */ | ||
| 1074 | #define POLC 0x4000 /* PPI Clock Polarity */ | ||
| 1075 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | ||
| 1076 | |||
| 1077 | /* PPI_STATUS Masks */ | ||
| 1078 | #define FLD 0x0400 /* Field Indicator */ | ||
| 1079 | #define FT_ERR 0x0800 /* Frame Track Error */ | ||
| 1080 | #define OVR 0x1000 /* FIFO Overflow Error */ | ||
| 1081 | #define UNDR 0x2000 /* FIFO Underrun Error */ | ||
| 1082 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | ||
| 1083 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | ||
| 1084 | |||
| 1085 | |||
| 1086 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
| 1087 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 1088 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 1089 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 1090 | |||
| 1091 | /* TWI_PRESCALE Masks */ | ||
| 1092 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 1093 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 1094 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 1095 | |||
| 1096 | /* TWI_SLAVE_CTL Masks */ | ||
| 1097 | #define SEN 0x0001 /* Slave Enable */ | ||
| 1098 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 1099 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 1100 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 1101 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
| 1102 | |||
| 1103 | /* TWI_SLAVE_STAT Masks */ | ||
| 1104 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 1105 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 1106 | |||
| 1107 | /* TWI_MASTER_CTL Masks */ | ||
| 1108 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 1109 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 1110 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 1111 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 1112 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 1113 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 1114 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 1115 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 1116 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 1117 | |||
| 1118 | /* TWI_MASTER_STAT Masks */ | ||
| 1119 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 1120 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 1121 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 1122 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 1123 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 1124 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 1125 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 1126 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 1127 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 1128 | |||
| 1129 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
| 1130 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 1131 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 1132 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 1133 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 1134 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 1135 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 1136 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 1137 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 1138 | |||
| 1139 | /* TWI_FIFO_CTRL Masks */ | ||
| 1140 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 1141 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 1142 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 1143 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 1144 | |||
| 1145 | /* TWI_FIFO_STAT Masks */ | ||
| 1146 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 1147 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 1148 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 1149 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 1150 | |||
| 1151 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 1152 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 1153 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 1154 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 1155 | |||
| 1156 | |||
| 1157 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | ||
| 1158 | /* PORT_MUX Masks */ | ||
| 1159 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | ||
| 1160 | #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ | ||
| 1161 | #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ | ||
| 1162 | |||
| 1163 | #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ | ||
| 1164 | #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ | ||
| 1165 | #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ | ||
| 1166 | #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ | ||
| 1167 | |||
| 1168 | #define PFDE 0x0008 /* Port F DMA Request Enable */ | ||
| 1169 | #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ | ||
| 1170 | #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ | ||
| 1171 | |||
| 1172 | #define PFTE 0x0010 /* Port F Timer Enable */ | ||
| 1173 | #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ | ||
| 1174 | #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ | ||
| 1175 | |||
| 1176 | #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ | ||
| 1177 | #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ | ||
| 1178 | #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ | ||
| 1179 | |||
| 1180 | #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ | ||
| 1181 | #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ | ||
| 1182 | #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ | ||
| 1183 | |||
| 1184 | #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ | ||
| 1185 | #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ | ||
| 1186 | #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ | ||
| 1187 | |||
| 1188 | #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ | ||
| 1189 | #define PFFE_TIMER 0x0000 /* Enable TMR2 */ | ||
| 1190 | #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ | ||
| 1191 | |||
| 1192 | #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ | ||
| 1193 | #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ | ||
| 1194 | #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ | ||
| 1195 | |||
| 1196 | #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ | ||
| 1197 | #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ | ||
| 1198 | #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ | ||
| 1199 | |||
| 1200 | #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ | ||
| 1201 | #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ | ||
| 1202 | #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ | ||
| 1203 | |||
| 1204 | |||
| 1205 | /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ | ||
| 1206 | /* HDMAx_CTL Masks */ | ||
| 1207 | #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ | ||
| 1208 | #define REP 0x0002 /* HDMA Request Polarity */ | ||
| 1209 | #define UTE 0x0004 /* Urgency Threshold Enable */ | ||
| 1210 | #define OIE 0x0010 /* Overflow Interrupt Enable */ | ||
| 1211 | #define BDIE 0x0020 /* Block Done Interrupt Enable */ | ||
| 1212 | #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ | ||
| 1213 | #define DRQ 0x0300 /* HDMA Request Type */ | ||
| 1214 | #define DRQ_NONE 0x0000 /* No Request */ | ||
| 1215 | #define DRQ_SINGLE 0x0100 /* Channels Request Single */ | ||
| 1216 | #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ | ||
| 1217 | #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ | ||
| 1218 | #define RBC 0x1000 /* Reload BCNT With IBCNT */ | ||
| 1219 | #define PS 0x2000 /* HDMA Pin Status */ | ||
| 1220 | #define OI 0x4000 /* Overflow Interrupt Generated */ | ||
| 1221 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | ||
| 1222 | |||
| 1223 | /* entry addresses of the user-callable Boot ROM functions */ | ||
| 1224 | |||
| 1225 | #define _BOOTROM_RESET 0xEF000000 | ||
| 1226 | #define _BOOTROM_FINAL_INIT 0xEF000002 | ||
| 1227 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | ||
| 1228 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | ||
| 1229 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | ||
| 1230 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | ||
| 1231 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | ||
| 1232 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | ||
| 1233 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | ||
| 1234 | |||
| 1235 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 1236 | #define PGDE_UART PFDE_UART | ||
| 1237 | #define PGDE_DMA PFDE_DMA | ||
| 1238 | #define CKELOW SCKELOW | ||
| 1239 | |||
| 1240 | /* HOST Port Registers */ | ||
| 1241 | |||
| 1242 | #define HOST_CONTROL 0xffc03400 /* HOST Control Register */ | ||
| 1243 | #define HOST_STATUS 0xffc03404 /* HOST Status Register */ | ||
| 1244 | #define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ | ||
| 1245 | |||
| 1246 | /* Counter Registers */ | ||
| 1247 | |||
| 1248 | #define CNT_CONFIG 0xffc03500 /* Configuration Register */ | ||
| 1249 | #define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ | ||
| 1250 | #define CNT_STATUS 0xffc03508 /* Status Register */ | ||
| 1251 | #define CNT_COMMAND 0xffc0350c /* Command Register */ | ||
| 1252 | #define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ | ||
| 1253 | #define CNT_COUNTER 0xffc03514 /* Counter Register */ | ||
| 1254 | #define CNT_MAX 0xffc03518 /* Maximal Count Register */ | ||
| 1255 | #define CNT_MIN 0xffc0351c /* Minimal Count Register */ | ||
| 1256 | |||
| 1257 | /* OTP/FUSE Registers */ | ||
| 1258 | |||
| 1259 | #define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ | ||
| 1260 | #define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ | ||
| 1261 | #define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ | ||
| 1262 | #define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ | ||
| 1263 | |||
| 1264 | /* Security Registers */ | ||
| 1265 | |||
| 1266 | #define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ | ||
| 1267 | #define SECURE_CONTROL 0xffc03624 /* Secure Control */ | ||
| 1268 | #define SECURE_STATUS 0xffc03628 /* Secure Status */ | ||
| 1269 | |||
| 1270 | /* OTP Read/Write Data Buffer Registers */ | ||
| 1271 | |||
| 1272 | #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1273 | #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1274 | #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1275 | #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1276 | |||
| 1277 | /* Motor Control PWM Registers */ | ||
| 1278 | |||
| 1279 | #define PWM_CTRL 0xffc03700 /* PWM Control Register */ | ||
| 1280 | #define PWM_STAT 0xffc03704 /* PWM Status Register */ | ||
| 1281 | #define PWM_TM 0xffc03708 /* PWM Period Register */ | ||
| 1282 | #define PWM_DT 0xffc0370c /* PWM Dead Time Register */ | ||
| 1283 | #define PWM_GATE 0xffc03710 /* PWM Chopping Control */ | ||
| 1284 | #define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ | ||
| 1285 | #define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ | ||
| 1286 | #define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ | ||
| 1287 | #define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ | ||
| 1288 | #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ | ||
| 1289 | #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ | ||
| 1290 | #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ | ||
| 1291 | #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ | ||
| 1292 | #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ | ||
| 1293 | #define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ | ||
| 1294 | |||
| 1295 | |||
| 1296 | /* ********************************************************** */ | ||
| 1297 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
| 1298 | /* and MULTI BIT READ MACROS */ | ||
| 1299 | /* ********************************************************** */ | ||
| 1300 | |||
| 1301 | /* Bit masks for HOST_CONTROL */ | ||
| 1302 | |||
| 1303 | #define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ | ||
| 1304 | #define HOST_CNTR_nHOST_EN 0x0 | ||
| 1305 | #define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ | ||
| 1306 | #define HOST_CNTR_nHOST_END 0x0 | ||
| 1307 | #define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ | ||
| 1308 | #define HOST_CNTR_nDATA_SIZE 0x0 | ||
| 1309 | #define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ | ||
| 1310 | #define HOST_CNTR_nHOST_RST 0x0 | ||
| 1311 | #define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 1312 | #define HOST_CNTR_nHRDY_OVR 0x0 | ||
| 1313 | #define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ | ||
| 1314 | #define HOST_CNTR_nINT_MODE 0x0 | ||
| 1315 | #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 1316 | #define HOST_CNTR_ nBT_EN 0x0 | ||
| 1317 | #define HOST_CNTR_EHW 0x100 /* Enable Host Write */ | ||
| 1318 | #define HOST_CNTR_nEHW 0x0 | ||
| 1319 | #define HOST_CNTR_EHR 0x200 /* Enable Host Read */ | ||
| 1320 | #define HOST_CNTR_nEHR 0x0 | ||
| 1321 | #define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ | ||
| 1322 | #define HOST_CNTR_nBDR 0x0 | ||
| 1323 | |||
| 1324 | /* Bit masks for HOST_STATUS */ | ||
| 1325 | |||
| 1326 | #define HOST_STAT_READY 0x1 /* DMA Ready */ | ||
| 1327 | #define HOST_STAT_nREADY 0x0 | ||
| 1328 | #define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ | ||
| 1329 | #define HOST_STAT_nFIFOFULL 0x0 | ||
| 1330 | #define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 1331 | #define HOST_STAT_nFIFOEMPTY 0x0 | ||
| 1332 | #define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ | ||
| 1333 | #define HOST_STAT_nCOMPLETE 0x0 | ||
| 1334 | #define HOST_STAT_HSHK 0x10 /* Host Handshake */ | ||
| 1335 | #define HOST_STAT_nHSHK 0x0 | ||
| 1336 | #define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ | ||
| 1337 | #define HOST_STAT_nTIMEOUT 0x0 | ||
| 1338 | #define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ | ||
| 1339 | #define HOST_STAT_nHIRQ 0x0 | ||
| 1340 | #define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 1341 | #define HOST_STAT_nALLOW_CNFG 0x0 | ||
| 1342 | #define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ | ||
| 1343 | #define HOST_STAT_nDMA_DIR 0x0 | ||
| 1344 | #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ | ||
| 1345 | #define HOST_STAT_nBTE 0x0 | ||
| 1346 | #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ | ||
| 1347 | #define HOST_STAT_nHOSTRD_DONE 0x0 | ||
| 1348 | |||
| 1349 | /* Bit masks for HOST_TIMEOUT */ | ||
| 1350 | |||
| 1351 | #define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 1352 | |||
| 1353 | /* Bit masks for SECURE_SYSSWT */ | ||
| 1354 | |||
| 1355 | #define EMUDABL 0x1 /* Emulation Disable. */ | ||
| 1356 | #define nEMUDABL 0x0 | ||
| 1357 | #define RSTDABL 0x2 /* Reset Disable */ | ||
| 1358 | #define nRSTDABL 0x0 | ||
| 1359 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | ||
| 1360 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | ||
| 1361 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | ||
| 1362 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | ||
| 1363 | #define nDMA0OVR 0x0 | ||
| 1364 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | ||
| 1365 | #define nDMA1OVR 0x0 | ||
| 1366 | #define EMUOVR 0x4000 /* Emulation Override */ | ||
| 1367 | #define nEMUOVR 0x0 | ||
| 1368 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | ||
| 1369 | #define nOTPSEN 0x0 | ||
| 1370 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | ||
| 1371 | |||
| 1372 | /* Bit masks for SECURE_CONTROL */ | ||
| 1373 | |||
| 1374 | #define SECURE0 0x1 /* SECURE 0 */ | ||
| 1375 | #define nSECURE0 0x0 | ||
| 1376 | #define SECURE1 0x2 /* SECURE 1 */ | ||
| 1377 | #define nSECURE1 0x0 | ||
| 1378 | #define SECURE2 0x4 /* SECURE 2 */ | ||
| 1379 | #define nSECURE2 0x0 | ||
| 1380 | #define SECURE3 0x8 /* SECURE 3 */ | ||
| 1381 | #define nSECURE3 0x0 | ||
| 1382 | |||
| 1383 | /* Bit masks for SECURE_STATUS */ | ||
| 1384 | |||
| 1385 | #define SECMODE 0x3 /* Secured Mode Control State */ | ||
| 1386 | #define NMI 0x4 /* Non Maskable Interrupt */ | ||
| 1387 | #define nNMI 0x0 | ||
| 1388 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | ||
| 1389 | #define nAFVALID 0x0 | ||
| 1390 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | ||
| 1391 | #define nAFEXIT 0x0 | ||
| 1392 | #define SECSTAT 0xe0 /* Secure Status */ | ||
| 12 | 1393 | ||
| 13 | #endif /* _DEF_BF512_H */ | 1394 | #endif /* _DEF_BF512_H */ |
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h deleted file mode 100644 index bd2be4e93859..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ /dev/null | |||
| @@ -1,1397 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Analog Devices Inc. | ||
| 3 | * | ||
| 4 | * Licensed under the ADI BSD license or the GPL-2 (or later) | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _DEF_BF51X_H | ||
| 8 | #define _DEF_BF51X_H | ||
| 9 | |||
| 10 | |||
| 11 | /* ************************************************************** */ | ||
| 12 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ | ||
| 13 | /* ************************************************************** */ | ||
| 14 | |||
| 15 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 16 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ | ||
| 17 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ | ||
| 18 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ | ||
| 19 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ | ||
| 20 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ | ||
| 21 | #define CHIPID 0xFFC00014 /* Device ID Register */ | ||
| 22 | |||
| 23 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 24 | #define SWRST 0xFFC00100 /* Software Reset Register */ | ||
| 25 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | ||
| 26 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | ||
| 27 | |||
| 28 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | ||
| 29 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | ||
| 30 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | ||
| 31 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | ||
| 32 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | ||
| 33 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | ||
| 34 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | ||
| 35 | |||
| 36 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 37 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | ||
| 38 | #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ | ||
| 39 | #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ | ||
| 40 | #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ | ||
| 41 | #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ | ||
| 42 | #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ | ||
| 43 | #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ | ||
| 44 | |||
| 45 | |||
| 46 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 47 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | ||
| 48 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | ||
| 49 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | ||
| 50 | |||
| 51 | |||
| 52 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 53 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | ||
| 54 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | ||
| 55 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | ||
| 56 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | ||
| 57 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | ||
| 58 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | ||
| 59 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ | ||
| 60 | |||
| 61 | |||
| 62 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 63 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | ||
| 64 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | ||
| 65 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
| 66 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
| 67 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
| 68 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
| 69 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | ||
| 70 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | ||
| 71 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | ||
| 72 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ | ||
| 73 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
| 74 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | ||
| 75 | |||
| 76 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 77 | #define SPI0_REGBASE 0xFFC00500 | ||
| 78 | #define SPI0_CTL 0xFFC00500 /* SPI Control Register */ | ||
| 79 | #define SPI0_FLG 0xFFC00504 /* SPI Flag register */ | ||
| 80 | #define SPI0_STAT 0xFFC00508 /* SPI Status register */ | ||
| 81 | #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | ||
| 82 | #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | ||
| 83 | #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ | ||
| 84 | #define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | ||
| 85 | |||
| 86 | /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ | ||
| 87 | #define SPI1_REGBASE 0xFFC03400 | ||
| 88 | #define SPI1_CTL 0xFFC03400 /* SPI Control Register */ | ||
| 89 | #define SPI1_FLG 0xFFC03404 /* SPI Flag register */ | ||
| 90 | #define SPI1_STAT 0xFFC03408 /* SPI Status register */ | ||
| 91 | #define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ | ||
| 92 | #define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ | ||
| 93 | #define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ | ||
| 94 | #define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ | ||
| 95 | |||
| 96 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 97 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | ||
| 98 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | ||
| 99 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | ||
| 100 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | ||
| 101 | |||
| 102 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | ||
| 103 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | ||
| 104 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | ||
| 105 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | ||
| 106 | |||
| 107 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | ||
| 108 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | ||
| 109 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | ||
| 110 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | ||
| 111 | |||
| 112 | #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ | ||
| 113 | #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ | ||
| 114 | #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ | ||
| 115 | #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ | ||
| 116 | |||
| 117 | #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ | ||
| 118 | #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ | ||
| 119 | #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ | ||
| 120 | #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ | ||
| 121 | |||
| 122 | #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ | ||
| 123 | #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ | ||
| 124 | #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ | ||
| 125 | #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ | ||
| 126 | |||
| 127 | #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ | ||
| 128 | #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ | ||
| 129 | #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ | ||
| 130 | #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ | ||
| 131 | |||
| 132 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | ||
| 133 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | ||
| 134 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | ||
| 135 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | ||
| 136 | |||
| 137 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | ||
| 138 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | ||
| 139 | #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ | ||
| 140 | |||
| 141 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 142 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ | ||
| 143 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ | ||
| 144 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ | ||
| 145 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ | ||
| 146 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ | ||
| 147 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ | ||
| 148 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ | ||
| 149 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ | ||
| 150 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ | ||
| 151 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ | ||
| 152 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ | ||
| 153 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ | ||
| 154 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ | ||
| 155 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ | ||
| 156 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ | ||
| 157 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ | ||
| 158 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ | ||
| 159 | |||
| 160 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 161 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 162 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 163 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
| 164 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
| 165 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
| 166 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
| 167 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 168 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 169 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
| 170 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
| 171 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
| 172 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
| 173 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
| 174 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
| 175 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
| 176 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
| 177 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
| 178 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
| 179 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
| 180 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
| 181 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
| 182 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
| 183 | |||
| 184 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 185 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 186 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 187 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
| 188 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
| 189 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
| 190 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
| 191 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 192 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 193 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
| 194 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
| 195 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
| 196 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
| 197 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
| 198 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
| 199 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
| 200 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
| 201 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
| 202 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
| 203 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
| 204 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
| 205 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
| 206 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
| 207 | |||
| 208 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 209 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
| 210 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
| 211 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
| 212 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
| 213 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
| 214 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
| 215 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
| 216 | |||
| 217 | /* DMA Traffic Control Registers */ | ||
| 218 | #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 219 | #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 220 | |||
| 221 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | ||
| 222 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
| 223 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | ||
| 224 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | ||
| 225 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | ||
| 226 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | ||
| 227 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | ||
| 228 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | ||
| 229 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
| 230 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | ||
| 231 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | ||
| 232 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | ||
| 233 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | ||
| 234 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | ||
| 235 | |||
| 236 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
| 237 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | ||
| 238 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | ||
| 239 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | ||
| 240 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | ||
| 241 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | ||
| 242 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | ||
| 243 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
| 244 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | ||
| 245 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | ||
| 246 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | ||
| 247 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | ||
| 248 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | ||
| 249 | |||
| 250 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
| 251 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | ||
| 252 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | ||
| 253 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | ||
| 254 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | ||
| 255 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | ||
| 256 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | ||
| 257 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
| 258 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | ||
| 259 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | ||
| 260 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | ||
| 261 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | ||
| 262 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | ||
| 263 | |||
| 264 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
| 265 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | ||
| 266 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | ||
| 267 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | ||
| 268 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | ||
| 269 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | ||
| 270 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | ||
| 271 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
| 272 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | ||
| 273 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | ||
| 274 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | ||
| 275 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | ||
| 276 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | ||
| 277 | |||
| 278 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
| 279 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | ||
| 280 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | ||
| 281 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | ||
| 282 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | ||
| 283 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | ||
| 284 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | ||
| 285 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
| 286 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | ||
| 287 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | ||
| 288 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | ||
| 289 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | ||
| 290 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | ||
| 291 | |||
| 292 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
| 293 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | ||
| 294 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | ||
| 295 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | ||
| 296 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | ||
| 297 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | ||
| 298 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | ||
| 299 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
| 300 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | ||
| 301 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | ||
| 302 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | ||
| 303 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | ||
| 304 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | ||
| 305 | |||
| 306 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
| 307 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | ||
| 308 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | ||
| 309 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | ||
| 310 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | ||
| 311 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | ||
| 312 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | ||
| 313 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
| 314 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | ||
| 315 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | ||
| 316 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | ||
| 317 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | ||
| 318 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | ||
| 319 | |||
| 320 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
| 321 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | ||
| 322 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | ||
| 323 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | ||
| 324 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | ||
| 325 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | ||
| 326 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | ||
| 327 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
| 328 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | ||
| 329 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | ||
| 330 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | ||
| 331 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | ||
| 332 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | ||
| 333 | |||
| 334 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
| 335 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ | ||
| 336 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ | ||
| 337 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ | ||
| 338 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ | ||
| 339 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ | ||
| 340 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ | ||
| 341 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
| 342 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ | ||
| 343 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ | ||
| 344 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ | ||
| 345 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ | ||
| 346 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ | ||
| 347 | |||
| 348 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
| 349 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ | ||
| 350 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ | ||
| 351 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ | ||
| 352 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ | ||
| 353 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ | ||
| 354 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ | ||
| 355 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
| 356 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ | ||
| 357 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ | ||
| 358 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ | ||
| 359 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ | ||
| 360 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ | ||
| 361 | |||
| 362 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
| 363 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ | ||
| 364 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ | ||
| 365 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ | ||
| 366 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ | ||
| 367 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ | ||
| 368 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ | ||
| 369 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
| 370 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ | ||
| 371 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ | ||
| 372 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ | ||
| 373 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ | ||
| 374 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ | ||
| 375 | |||
| 376 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
| 377 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ | ||
| 378 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ | ||
| 379 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ | ||
| 380 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ | ||
| 381 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ | ||
| 382 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ | ||
| 383 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
| 384 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ | ||
| 385 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ | ||
| 386 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ | ||
| 387 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ | ||
| 388 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ | ||
| 389 | |||
| 390 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | ||
| 391 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ | ||
| 392 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ | ||
| 393 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ | ||
| 394 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ | ||
| 395 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ | ||
| 396 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ | ||
| 397 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | ||
| 398 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ | ||
| 399 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | ||
| 400 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | ||
| 401 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ | ||
| 402 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ | ||
| 403 | |||
| 404 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | ||
| 405 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ | ||
| 406 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ | ||
| 407 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ | ||
| 408 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ | ||
| 409 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ | ||
| 410 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ | ||
| 411 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | ||
| 412 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ | ||
| 413 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | ||
| 414 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ | ||
| 415 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ | ||
| 416 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ | ||
| 417 | |||
| 418 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | ||
| 419 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ | ||
| 420 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ | ||
| 421 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ | ||
| 422 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ | ||
| 423 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ | ||
| 424 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ | ||
| 425 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | ||
| 426 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ | ||
| 427 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | ||
| 428 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | ||
| 429 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ | ||
| 430 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | ||
| 431 | |||
| 432 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | ||
| 433 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ | ||
| 434 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ | ||
| 435 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ | ||
| 436 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ | ||
| 437 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ | ||
| 438 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ | ||
| 439 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | ||
| 440 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ | ||
| 441 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | ||
| 442 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ | ||
| 443 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ | ||
| 444 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ | ||
| 445 | |||
| 446 | |||
| 447 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 448 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | ||
| 449 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | ||
| 450 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | ||
| 451 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | ||
| 452 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | ||
| 453 | |||
| 454 | |||
| 455 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 456 | #define TWI0_REGBASE 0xFFC01400 | ||
| 457 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | ||
| 458 | #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ | ||
| 459 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | ||
| 460 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | ||
| 461 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | ||
| 462 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | ||
| 463 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | ||
| 464 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | ||
| 465 | #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | ||
| 466 | #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | ||
| 467 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | ||
| 468 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | ||
| 469 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | ||
| 470 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | ||
| 471 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | ||
| 472 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | ||
| 473 | |||
| 474 | |||
| 475 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 476 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | ||
| 477 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ | ||
| 478 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ | ||
| 479 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ | ||
| 480 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ | ||
| 481 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ | ||
| 482 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ | ||
| 483 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ | ||
| 484 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ | ||
| 485 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ | ||
| 486 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ | ||
| 487 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ | ||
| 488 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ | ||
| 489 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ | ||
| 490 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ | ||
| 491 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ | ||
| 492 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ | ||
| 493 | |||
| 494 | |||
| 495 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 496 | #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ | ||
| 497 | #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ | ||
| 498 | #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ | ||
| 499 | #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ | ||
| 500 | #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ | ||
| 501 | #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ | ||
| 502 | #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ | ||
| 503 | #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ | ||
| 504 | #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ | ||
| 505 | #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ | ||
| 506 | #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ | ||
| 507 | #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ | ||
| 508 | #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ | ||
| 509 | #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ | ||
| 510 | #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ | ||
| 511 | #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ | ||
| 512 | #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ | ||
| 513 | |||
| 514 | |||
| 515 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 516 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | ||
| 517 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | ||
| 518 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | ||
| 519 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | ||
| 520 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | ||
| 521 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | ||
| 522 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | ||
| 523 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | ||
| 524 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | ||
| 525 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ | ||
| 526 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | ||
| 527 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | ||
| 528 | |||
| 529 | |||
| 530 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 531 | #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ | ||
| 532 | #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ | ||
| 533 | #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ | ||
| 534 | #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ | ||
| 535 | |||
| 536 | |||
| 537 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 538 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | ||
| 539 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | ||
| 540 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | ||
| 541 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ | ||
| 542 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ | ||
| 543 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | ||
| 544 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | ||
| 545 | |||
| 546 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | ||
| 547 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | ||
| 548 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | ||
| 549 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ | ||
| 550 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ | ||
| 551 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | ||
| 552 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | ||
| 553 | |||
| 554 | |||
| 555 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 556 | #define PORTF_MUX 0xFFC03210 /* Port F mux control */ | ||
| 557 | #define PORTG_MUX 0xFFC03214 /* Port G mux control */ | ||
| 558 | #define PORTH_MUX 0xFFC03218 /* Port H mux control */ | ||
| 559 | #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ | ||
| 560 | #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ | ||
| 561 | #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ | ||
| 562 | #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ | ||
| 563 | #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ | ||
| 564 | #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ | ||
| 565 | #define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ | ||
| 566 | #define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ | ||
| 567 | #define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ | ||
| 568 | #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ | ||
| 569 | #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ | ||
| 570 | #define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ | ||
| 571 | |||
| 572 | |||
| 573 | /*********************************************************************************** | ||
| 574 | ** System MMR Register Bits And Macros | ||
| 575 | ** | ||
| 576 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 577 | ** Use these macros carefully, as any that do left shifts for field | ||
| 578 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 579 | ** macro that shifts left to properly position the bit-field should be | ||
| 580 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 581 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 582 | ** the macro is used. | ||
| 583 | *************************************************************************************/ | ||
| 584 | |||
| 585 | /* CHIPID Masks */ | ||
| 586 | #define CHIPID_VERSION 0xF0000000 | ||
| 587 | #define CHIPID_FAMILY 0x0FFFF000 | ||
| 588 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
| 589 | |||
| 590 | /* SWRST Masks */ | ||
| 591 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | ||
| 592 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | ||
| 593 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | ||
| 594 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | ||
| 595 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | ||
| 596 | |||
| 597 | /* SYSCR Masks */ | ||
| 598 | #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ | ||
| 599 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | ||
| 600 | |||
| 601 | |||
| 602 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | ||
| 603 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | ||
| 604 | |||
| 605 | #if 0 | ||
| 606 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | ||
| 607 | |||
| 608 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | ||
| 609 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | ||
| 610 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | ||
| 611 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | ||
| 612 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | ||
| 613 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | ||
| 614 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | ||
| 615 | |||
| 616 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | ||
| 617 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | ||
| 618 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | ||
| 619 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | ||
| 620 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | ||
| 621 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | ||
| 622 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | ||
| 623 | #define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ | ||
| 624 | |||
| 625 | #define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ | ||
| 626 | #define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ | ||
| 627 | #define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ | ||
| 628 | #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ | ||
| 629 | #define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ | ||
| 630 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ | ||
| 631 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ | ||
| 632 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ | ||
| 633 | #define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ | ||
| 634 | #define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ | ||
| 635 | |||
| 636 | #define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ | ||
| 637 | #define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ | ||
| 638 | #define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ | ||
| 639 | #define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ | ||
| 640 | #define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ | ||
| 641 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ | ||
| 642 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ | ||
| 643 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ | ||
| 644 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | ||
| 645 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | ||
| 646 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | ||
| 647 | #endif | ||
| 648 | |||
| 649 | /* SIC_IAR0 Macros */ | ||
| 650 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | ||
| 651 | #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | ||
| 652 | #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | ||
| 653 | #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | ||
| 654 | #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | ||
| 655 | #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | ||
| 656 | #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | ||
| 657 | #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | ||
| 658 | |||
| 659 | /* SIC_IAR1 Macros */ | ||
| 660 | #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ | ||
| 661 | #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | ||
| 662 | #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | ||
| 663 | #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | ||
| 664 | #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | ||
| 665 | #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | ||
| 666 | #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | ||
| 667 | #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | ||
| 668 | |||
| 669 | /* SIC_IAR2 Macros */ | ||
| 670 | #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ | ||
| 671 | #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | ||
| 672 | #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | ||
| 673 | #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | ||
| 674 | #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | ||
| 675 | #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | ||
| 676 | #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | ||
| 677 | #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | ||
| 678 | |||
| 679 | /* SIC_IAR3 Macros */ | ||
| 680 | #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ | ||
| 681 | #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ | ||
| 682 | #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ | ||
| 683 | #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ | ||
| 684 | #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ | ||
| 685 | #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ | ||
| 686 | #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ | ||
| 687 | #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ | ||
| 688 | |||
| 689 | |||
| 690 | /* SIC_IMASK Masks */ | ||
| 691 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 692 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 693 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | ||
| 694 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | ||
| 695 | |||
| 696 | /* SIC_IWR Masks */ | ||
| 697 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 698 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 699 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | ||
| 700 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | ||
| 701 | |||
| 702 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | ||
| 703 | /* TIMER_ENABLE Masks */ | ||
| 704 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | ||
| 705 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | ||
| 706 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | ||
| 707 | #define TIMEN3 0x0008 /* Enable Timer 3 */ | ||
| 708 | #define TIMEN4 0x0010 /* Enable Timer 4 */ | ||
| 709 | #define TIMEN5 0x0020 /* Enable Timer 5 */ | ||
| 710 | #define TIMEN6 0x0040 /* Enable Timer 6 */ | ||
| 711 | #define TIMEN7 0x0080 /* Enable Timer 7 */ | ||
| 712 | |||
| 713 | /* TIMER_DISABLE Masks */ | ||
| 714 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ | ||
| 715 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ | ||
| 716 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ | ||
| 717 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ | ||
| 718 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ | ||
| 719 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ | ||
| 720 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ | ||
| 721 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ | ||
| 722 | |||
| 723 | /* TIMER_STATUS Masks */ | ||
| 724 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ | ||
| 725 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ | ||
| 726 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ | ||
| 727 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ | ||
| 728 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ | ||
| 729 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ | ||
| 730 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ | ||
| 731 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ | ||
| 732 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ | ||
| 733 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ | ||
| 734 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ | ||
| 735 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ | ||
| 736 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ | ||
| 737 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ | ||
| 738 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ | ||
| 739 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ | ||
| 740 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ | ||
| 741 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ | ||
| 742 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ | ||
| 743 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ | ||
| 744 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | ||
| 745 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | ||
| 746 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | ||
| 747 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | ||
| 748 | |||
| 749 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 750 | #define TOVL_ERR0 TOVF_ERR0 | ||
| 751 | #define TOVL_ERR1 TOVF_ERR1 | ||
| 752 | #define TOVL_ERR2 TOVF_ERR2 | ||
| 753 | #define TOVL_ERR3 TOVF_ERR3 | ||
| 754 | #define TOVL_ERR4 TOVF_ERR4 | ||
| 755 | #define TOVL_ERR5 TOVF_ERR5 | ||
| 756 | #define TOVL_ERR6 TOVF_ERR6 | ||
| 757 | #define TOVL_ERR7 TOVF_ERR7 | ||
| 758 | |||
| 759 | /* TIMERx_CONFIG Masks */ | ||
| 760 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ | ||
| 761 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ | ||
| 762 | #define EXT_CLK 0x0003 /* External Clock Mode */ | ||
| 763 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ | ||
| 764 | #define PERIOD_CNT 0x0008 /* Period Count */ | ||
| 765 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ | ||
| 766 | #define TIN_SEL 0x0020 /* Timer Input Select */ | ||
| 767 | #define OUT_DIS 0x0040 /* Output Pad Disable */ | ||
| 768 | #define CLK_SEL 0x0080 /* Timer Clock Select */ | ||
| 769 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ | ||
| 770 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ | ||
| 771 | #define ERR_TYP 0xC000 /* Error Type */ | ||
| 772 | |||
| 773 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | ||
| 774 | /* EBIU_AMGCTL Masks */ | ||
| 775 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 776 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
| 777 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | ||
| 778 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | ||
| 779 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | ||
| 780 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 781 | |||
| 782 | /* EBIU_AMBCTL0 Masks */ | ||
| 783 | #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ | ||
| 784 | #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ | ||
| 785 | #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ | ||
| 786 | #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ | ||
| 787 | #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ | ||
| 788 | #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ | ||
| 789 | #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 790 | #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 791 | #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 792 | #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 793 | #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 794 | #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 795 | #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 796 | #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 797 | #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ | ||
| 798 | #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ | ||
| 799 | #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ | ||
| 800 | #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ | ||
| 801 | #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ | ||
| 802 | #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ | ||
| 803 | #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ | ||
| 804 | #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ | ||
| 805 | #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ | ||
| 806 | #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ | ||
| 807 | #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ | ||
| 808 | #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ | ||
| 809 | #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ | ||
| 810 | #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ | ||
| 811 | #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ | ||
| 812 | #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ | ||
| 813 | #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ | ||
| 814 | #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ | ||
| 815 | #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ | ||
| 816 | #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ | ||
| 817 | #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ | ||
| 818 | #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ | ||
| 819 | #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ | ||
| 820 | #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ | ||
| 821 | #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ | ||
| 822 | #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ | ||
| 823 | #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ | ||
| 824 | #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ | ||
| 825 | #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ | ||
| 826 | #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ | ||
| 827 | |||
| 828 | #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ | ||
| 829 | #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ | ||
| 830 | #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ | ||
| 831 | #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ | ||
| 832 | #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ | ||
| 833 | #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ | ||
| 834 | #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 835 | #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 836 | #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 837 | #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 838 | #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 839 | #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 840 | #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 841 | #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 842 | #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ | ||
| 843 | #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ | ||
| 844 | #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ | ||
| 845 | #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ | ||
| 846 | #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ | ||
| 847 | #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ | ||
| 848 | #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ | ||
| 849 | #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ | ||
| 850 | #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ | ||
| 851 | #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ | ||
| 852 | #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ | ||
| 853 | #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ | ||
| 854 | #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ | ||
| 855 | #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ | ||
| 856 | #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ | ||
| 857 | #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ | ||
| 858 | #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ | ||
| 859 | #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ | ||
| 860 | #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ | ||
| 861 | #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ | ||
| 862 | #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ | ||
| 863 | #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ | ||
| 864 | #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ | ||
| 865 | #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ | ||
| 866 | #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ | ||
| 867 | #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ | ||
| 868 | #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ | ||
| 869 | #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ | ||
| 870 | #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ | ||
| 871 | #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ | ||
| 872 | |||
| 873 | /* EBIU_AMBCTL1 Masks */ | ||
| 874 | #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ | ||
| 875 | #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ | ||
| 876 | #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ | ||
| 877 | #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ | ||
| 878 | #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ | ||
| 879 | #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ | ||
| 880 | #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 881 | #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 882 | #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 883 | #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 884 | #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 885 | #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 886 | #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 887 | #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 888 | #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ | ||
| 889 | #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ | ||
| 890 | #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ | ||
| 891 | #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ | ||
| 892 | #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ | ||
| 893 | #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ | ||
| 894 | #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ | ||
| 895 | #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ | ||
| 896 | #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ | ||
| 897 | #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ | ||
| 898 | #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ | ||
| 899 | #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ | ||
| 900 | #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ | ||
| 901 | #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ | ||
| 902 | #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ | ||
| 903 | #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ | ||
| 904 | #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ | ||
| 905 | #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ | ||
| 906 | #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ | ||
| 907 | #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ | ||
| 908 | #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ | ||
| 909 | #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ | ||
| 910 | #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ | ||
| 911 | #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ | ||
| 912 | #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ | ||
| 913 | #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ | ||
| 914 | #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ | ||
| 915 | #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ | ||
| 916 | #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ | ||
| 917 | #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ | ||
| 918 | |||
| 919 | #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ | ||
| 920 | #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ | ||
| 921 | #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ | ||
| 922 | #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ | ||
| 923 | #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ | ||
| 924 | #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ | ||
| 925 | #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 926 | #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 927 | #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 928 | #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 929 | #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 930 | #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 931 | #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 932 | #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 933 | #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ | ||
| 934 | #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ | ||
| 935 | #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ | ||
| 936 | #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ | ||
| 937 | #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ | ||
| 938 | #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ | ||
| 939 | #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ | ||
| 940 | #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ | ||
| 941 | #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ | ||
| 942 | #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ | ||
| 943 | #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ | ||
| 944 | #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ | ||
| 945 | #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ | ||
| 946 | #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ | ||
| 947 | #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ | ||
| 948 | #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ | ||
| 949 | #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ | ||
| 950 | #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ | ||
| 951 | #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ | ||
| 952 | #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ | ||
| 953 | #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ | ||
| 954 | #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ | ||
| 955 | #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ | ||
| 956 | #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ | ||
| 957 | #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ | ||
| 958 | #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ | ||
| 959 | #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ | ||
| 960 | #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ | ||
| 961 | #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ | ||
| 962 | #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ | ||
| 963 | |||
| 964 | |||
| 965 | /* ********************** SDRAM CONTROLLER MASKS **********************************************/ | ||
| 966 | /* EBIU_SDGCTL Masks */ | ||
| 967 | #define SCTLE 0x00000001 /* Enable SDRAM Signals */ | ||
| 968 | #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ | ||
| 969 | #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ | ||
| 970 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | ||
| 971 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | ||
| 972 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | ||
| 973 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
| 974 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
| 975 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
| 976 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
| 977 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
| 978 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
| 979 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
| 980 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
| 981 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
| 982 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
| 983 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
| 984 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
| 985 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
| 986 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
| 987 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
| 988 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
| 989 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
| 990 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
| 991 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
| 992 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
| 993 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
| 994 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
| 995 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
| 996 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
| 997 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
| 998 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
| 999 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
| 1000 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
| 1001 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
| 1002 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
| 1003 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
| 1004 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
| 1005 | #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ | ||
| 1006 | #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ | ||
| 1007 | #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ | ||
| 1008 | #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ | ||
| 1009 | #define EBUFE 0x02000000 /* Enable External Buffering Timing */ | ||
| 1010 | #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ | ||
| 1011 | #define EMREN 0x10000000 /* Extended Mode Register Enable */ | ||
| 1012 | #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ | ||
| 1013 | #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ | ||
| 1014 | |||
| 1015 | /* EBIU_SDBCTL Masks */ | ||
| 1016 | #define EBE 0x0001 /* Enable SDRAM External Bank */ | ||
| 1017 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ | ||
| 1018 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ | ||
| 1019 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ | ||
| 1020 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ | ||
| 1021 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ | ||
| 1022 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ | ||
| 1023 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ | ||
| 1024 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ | ||
| 1025 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ | ||
| 1026 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ | ||
| 1027 | |||
| 1028 | /* EBIU_SDSTAT Masks */ | ||
| 1029 | #define SDCI 0x0001 /* SDRAM Controller Idle */ | ||
| 1030 | #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ | ||
| 1031 | #define SDPUA 0x0004 /* SDRAM Power-Up Active */ | ||
| 1032 | #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ | ||
| 1033 | #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ | ||
| 1034 | #define BGSTAT 0x0020 /* Bus Grant Status */ | ||
| 1035 | |||
| 1036 | |||
| 1037 | /* ************************** DMA CONTROLLER MASKS ********************************/ | ||
| 1038 | |||
| 1039 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | ||
| 1040 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | ||
| 1041 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ | ||
| 1042 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ | ||
| 1043 | #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ | ||
| 1044 | #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ | ||
| 1045 | #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ | ||
| 1046 | #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ | ||
| 1047 | #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ | ||
| 1048 | #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ | ||
| 1049 | #define PMAP_SPI 0x7000 /* SPI Port DMA */ | ||
| 1050 | #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ | ||
| 1051 | #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ | ||
| 1052 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | ||
| 1053 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | ||
| 1054 | |||
| 1055 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | ||
| 1056 | /* PPI_CONTROL Masks */ | ||
| 1057 | #define PORT_EN 0x0001 /* PPI Port Enable */ | ||
| 1058 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | ||
| 1059 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | ||
| 1060 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | ||
| 1061 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | ||
| 1062 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | ||
| 1063 | #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ | ||
| 1064 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | ||
| 1065 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | ||
| 1066 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | ||
| 1067 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | ||
| 1068 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | ||
| 1069 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | ||
| 1070 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | ||
| 1071 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | ||
| 1072 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | ||
| 1073 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | ||
| 1074 | #define DLENGTH 0x3800 /* PPI Data Length */ | ||
| 1075 | #define POLC 0x4000 /* PPI Clock Polarity */ | ||
| 1076 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | ||
| 1077 | |||
| 1078 | /* PPI_STATUS Masks */ | ||
| 1079 | #define FLD 0x0400 /* Field Indicator */ | ||
| 1080 | #define FT_ERR 0x0800 /* Frame Track Error */ | ||
| 1081 | #define OVR 0x1000 /* FIFO Overflow Error */ | ||
| 1082 | #define UNDR 0x2000 /* FIFO Underrun Error */ | ||
| 1083 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | ||
| 1084 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | ||
| 1085 | |||
| 1086 | |||
| 1087 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
| 1088 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 1089 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 1090 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 1091 | |||
| 1092 | /* TWI_PRESCALE Masks */ | ||
| 1093 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 1094 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 1095 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 1096 | |||
| 1097 | /* TWI_SLAVE_CTL Masks */ | ||
| 1098 | #define SEN 0x0001 /* Slave Enable */ | ||
| 1099 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 1100 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 1101 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 1102 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
| 1103 | |||
| 1104 | /* TWI_SLAVE_STAT Masks */ | ||
| 1105 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 1106 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 1107 | |||
| 1108 | /* TWI_MASTER_CTL Masks */ | ||
| 1109 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 1110 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 1111 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 1112 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 1113 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 1114 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 1115 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 1116 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 1117 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 1118 | |||
| 1119 | /* TWI_MASTER_STAT Masks */ | ||
| 1120 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 1121 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 1122 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 1123 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 1124 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 1125 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 1126 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 1127 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 1128 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 1129 | |||
| 1130 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
| 1131 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 1132 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 1133 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 1134 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 1135 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 1136 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 1137 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 1138 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 1139 | |||
| 1140 | /* TWI_FIFO_CTRL Masks */ | ||
| 1141 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 1142 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 1143 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 1144 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 1145 | |||
| 1146 | /* TWI_FIFO_STAT Masks */ | ||
| 1147 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 1148 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 1149 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 1150 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 1151 | |||
| 1152 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 1153 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 1154 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 1155 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 1156 | |||
| 1157 | |||
| 1158 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | ||
| 1159 | /* PORT_MUX Masks */ | ||
| 1160 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | ||
| 1161 | #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ | ||
| 1162 | #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ | ||
| 1163 | |||
| 1164 | #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ | ||
| 1165 | #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ | ||
| 1166 | #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ | ||
| 1167 | #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ | ||
| 1168 | |||
| 1169 | #define PFDE 0x0008 /* Port F DMA Request Enable */ | ||
| 1170 | #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ | ||
| 1171 | #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ | ||
| 1172 | |||
| 1173 | #define PFTE 0x0010 /* Port F Timer Enable */ | ||
| 1174 | #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ | ||
| 1175 | #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ | ||
| 1176 | |||
| 1177 | #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ | ||
| 1178 | #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ | ||
| 1179 | #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ | ||
| 1180 | |||
| 1181 | #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ | ||
| 1182 | #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ | ||
| 1183 | #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ | ||
| 1184 | |||
| 1185 | #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ | ||
| 1186 | #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ | ||
| 1187 | #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ | ||
| 1188 | |||
| 1189 | #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ | ||
| 1190 | #define PFFE_TIMER 0x0000 /* Enable TMR2 */ | ||
| 1191 | #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ | ||
| 1192 | |||
| 1193 | #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ | ||
| 1194 | #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ | ||
| 1195 | #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ | ||
| 1196 | |||
| 1197 | #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ | ||
| 1198 | #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ | ||
| 1199 | #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ | ||
| 1200 | |||
| 1201 | #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ | ||
| 1202 | #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ | ||
| 1203 | #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ | ||
| 1204 | |||
| 1205 | |||
| 1206 | /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ | ||
| 1207 | /* HDMAx_CTL Masks */ | ||
| 1208 | #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ | ||
| 1209 | #define REP 0x0002 /* HDMA Request Polarity */ | ||
| 1210 | #define UTE 0x0004 /* Urgency Threshold Enable */ | ||
| 1211 | #define OIE 0x0010 /* Overflow Interrupt Enable */ | ||
| 1212 | #define BDIE 0x0020 /* Block Done Interrupt Enable */ | ||
| 1213 | #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ | ||
| 1214 | #define DRQ 0x0300 /* HDMA Request Type */ | ||
| 1215 | #define DRQ_NONE 0x0000 /* No Request */ | ||
| 1216 | #define DRQ_SINGLE 0x0100 /* Channels Request Single */ | ||
| 1217 | #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ | ||
| 1218 | #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ | ||
| 1219 | #define RBC 0x1000 /* Reload BCNT With IBCNT */ | ||
| 1220 | #define PS 0x2000 /* HDMA Pin Status */ | ||
| 1221 | #define OI 0x4000 /* Overflow Interrupt Generated */ | ||
| 1222 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | ||
| 1223 | |||
| 1224 | /* entry addresses of the user-callable Boot ROM functions */ | ||
| 1225 | |||
| 1226 | #define _BOOTROM_RESET 0xEF000000 | ||
| 1227 | #define _BOOTROM_FINAL_INIT 0xEF000002 | ||
| 1228 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | ||
| 1229 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | ||
| 1230 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | ||
| 1231 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | ||
| 1232 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | ||
| 1233 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | ||
| 1234 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | ||
| 1235 | |||
| 1236 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 1237 | #define PGDE_UART PFDE_UART | ||
| 1238 | #define PGDE_DMA PFDE_DMA | ||
| 1239 | #define CKELOW SCKELOW | ||
| 1240 | |||
| 1241 | /* HOST Port Registers */ | ||
| 1242 | |||
| 1243 | #define HOST_CONTROL 0xffc03400 /* HOST Control Register */ | ||
| 1244 | #define HOST_STATUS 0xffc03404 /* HOST Status Register */ | ||
| 1245 | #define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ | ||
| 1246 | |||
| 1247 | /* Counter Registers */ | ||
| 1248 | |||
| 1249 | #define CNT_CONFIG 0xffc03500 /* Configuration Register */ | ||
| 1250 | #define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ | ||
| 1251 | #define CNT_STATUS 0xffc03508 /* Status Register */ | ||
| 1252 | #define CNT_COMMAND 0xffc0350c /* Command Register */ | ||
| 1253 | #define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ | ||
| 1254 | #define CNT_COUNTER 0xffc03514 /* Counter Register */ | ||
| 1255 | #define CNT_MAX 0xffc03518 /* Maximal Count Register */ | ||
| 1256 | #define CNT_MIN 0xffc0351c /* Minimal Count Register */ | ||
| 1257 | |||
| 1258 | /* OTP/FUSE Registers */ | ||
| 1259 | |||
| 1260 | #define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ | ||
| 1261 | #define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ | ||
| 1262 | #define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ | ||
| 1263 | #define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ | ||
| 1264 | |||
| 1265 | /* Security Registers */ | ||
| 1266 | |||
| 1267 | #define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ | ||
| 1268 | #define SECURE_CONTROL 0xffc03624 /* Secure Control */ | ||
| 1269 | #define SECURE_STATUS 0xffc03628 /* Secure Status */ | ||
| 1270 | |||
| 1271 | /* OTP Read/Write Data Buffer Registers */ | ||
| 1272 | |||
| 1273 | #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1274 | #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1275 | #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1276 | #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1277 | |||
| 1278 | /* Motor Control PWM Registers */ | ||
| 1279 | |||
| 1280 | #define PWM_CTRL 0xffc03700 /* PWM Control Register */ | ||
| 1281 | #define PWM_STAT 0xffc03704 /* PWM Status Register */ | ||
| 1282 | #define PWM_TM 0xffc03708 /* PWM Period Register */ | ||
| 1283 | #define PWM_DT 0xffc0370c /* PWM Dead Time Register */ | ||
| 1284 | #define PWM_GATE 0xffc03710 /* PWM Chopping Control */ | ||
| 1285 | #define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ | ||
| 1286 | #define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ | ||
| 1287 | #define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ | ||
| 1288 | #define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ | ||
| 1289 | #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ | ||
| 1290 | #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ | ||
| 1291 | #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ | ||
| 1292 | #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ | ||
| 1293 | #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ | ||
| 1294 | #define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ | ||
| 1295 | |||
| 1296 | |||
| 1297 | /* ********************************************************** */ | ||
| 1298 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
| 1299 | /* and MULTI BIT READ MACROS */ | ||
| 1300 | /* ********************************************************** */ | ||
| 1301 | |||
| 1302 | /* Bit masks for HOST_CONTROL */ | ||
| 1303 | |||
| 1304 | #define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ | ||
| 1305 | #define HOST_CNTR_nHOST_EN 0x0 | ||
| 1306 | #define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ | ||
| 1307 | #define HOST_CNTR_nHOST_END 0x0 | ||
| 1308 | #define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ | ||
| 1309 | #define HOST_CNTR_nDATA_SIZE 0x0 | ||
| 1310 | #define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ | ||
| 1311 | #define HOST_CNTR_nHOST_RST 0x0 | ||
| 1312 | #define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 1313 | #define HOST_CNTR_nHRDY_OVR 0x0 | ||
| 1314 | #define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ | ||
| 1315 | #define HOST_CNTR_nINT_MODE 0x0 | ||
| 1316 | #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 1317 | #define HOST_CNTR_ nBT_EN 0x0 | ||
| 1318 | #define HOST_CNTR_EHW 0x100 /* Enable Host Write */ | ||
| 1319 | #define HOST_CNTR_nEHW 0x0 | ||
| 1320 | #define HOST_CNTR_EHR 0x200 /* Enable Host Read */ | ||
| 1321 | #define HOST_CNTR_nEHR 0x0 | ||
| 1322 | #define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ | ||
| 1323 | #define HOST_CNTR_nBDR 0x0 | ||
| 1324 | |||
| 1325 | /* Bit masks for HOST_STATUS */ | ||
| 1326 | |||
| 1327 | #define HOST_STAT_READY 0x1 /* DMA Ready */ | ||
| 1328 | #define HOST_STAT_nREADY 0x0 | ||
| 1329 | #define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ | ||
| 1330 | #define HOST_STAT_nFIFOFULL 0x0 | ||
| 1331 | #define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 1332 | #define HOST_STAT_nFIFOEMPTY 0x0 | ||
| 1333 | #define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ | ||
| 1334 | #define HOST_STAT_nCOMPLETE 0x0 | ||
| 1335 | #define HOST_STAT_HSHK 0x10 /* Host Handshake */ | ||
| 1336 | #define HOST_STAT_nHSHK 0x0 | ||
| 1337 | #define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ | ||
| 1338 | #define HOST_STAT_nTIMEOUT 0x0 | ||
| 1339 | #define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ | ||
| 1340 | #define HOST_STAT_nHIRQ 0x0 | ||
| 1341 | #define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 1342 | #define HOST_STAT_nALLOW_CNFG 0x0 | ||
| 1343 | #define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ | ||
| 1344 | #define HOST_STAT_nDMA_DIR 0x0 | ||
| 1345 | #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ | ||
| 1346 | #define HOST_STAT_nBTE 0x0 | ||
| 1347 | #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ | ||
| 1348 | #define HOST_STAT_nHOSTRD_DONE 0x0 | ||
| 1349 | |||
| 1350 | /* Bit masks for HOST_TIMEOUT */ | ||
| 1351 | |||
| 1352 | #define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 1353 | |||
| 1354 | /* Bit masks for SECURE_SYSSWT */ | ||
| 1355 | |||
| 1356 | #define EMUDABL 0x1 /* Emulation Disable. */ | ||
| 1357 | #define nEMUDABL 0x0 | ||
| 1358 | #define RSTDABL 0x2 /* Reset Disable */ | ||
| 1359 | #define nRSTDABL 0x0 | ||
| 1360 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | ||
| 1361 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | ||
| 1362 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | ||
| 1363 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | ||
| 1364 | #define nDMA0OVR 0x0 | ||
| 1365 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | ||
| 1366 | #define nDMA1OVR 0x0 | ||
| 1367 | #define EMUOVR 0x4000 /* Emulation Override */ | ||
| 1368 | #define nEMUOVR 0x0 | ||
| 1369 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | ||
| 1370 | #define nOTPSEN 0x0 | ||
| 1371 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | ||
| 1372 | |||
| 1373 | /* Bit masks for SECURE_CONTROL */ | ||
| 1374 | |||
| 1375 | #define SECURE0 0x1 /* SECURE 0 */ | ||
| 1376 | #define nSECURE0 0x0 | ||
| 1377 | #define SECURE1 0x2 /* SECURE 1 */ | ||
| 1378 | #define nSECURE1 0x0 | ||
| 1379 | #define SECURE2 0x4 /* SECURE 2 */ | ||
| 1380 | #define nSECURE2 0x0 | ||
| 1381 | #define SECURE3 0x8 /* SECURE 3 */ | ||
| 1382 | #define nSECURE3 0x0 | ||
| 1383 | |||
| 1384 | /* Bit masks for SECURE_STATUS */ | ||
| 1385 | |||
| 1386 | #define SECMODE 0x3 /* Secured Mode Control State */ | ||
| 1387 | #define NMI 0x4 /* Non Maskable Interrupt */ | ||
| 1388 | #define nNMI 0x0 | ||
| 1389 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | ||
| 1390 | #define nAFVALID 0x0 | ||
| 1391 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | ||
| 1392 | #define nAFEXIT 0x0 | ||
| 1393 | #define SECSTAT 0xe0 /* Secure Status */ | ||
| 1394 | |||
| 1395 | |||
| 1396 | |||
| 1397 | #endif /* _DEF_BF51X_H */ | ||