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authorMike Frysinger <vapier.adi@gmail.com>2008-04-24 14:04:05 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-24 14:04:05 -0400
commita086ee2268abcfcbf80a114f4602e5b26aa80bf0 (patch)
treefe027181ea37e00e85040977788cad82aa3faea5 /arch/blackfin/kernel/cplb-nompu
parenta81501af19830ff43688781edad7e9c0cbd668af (diff)
[Blackfin] arch: detect the memory available in the system on the fly by default
detect the memory available in the system on the fly by default rather than forcing people to set this manually in the kconfig Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu')
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index f271f39d5655..917325bfbd84 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -26,6 +26,12 @@
26#include <asm/cplb.h> 26#include <asm/cplb.h>
27#include <asm/cplbinit.h> 27#include <asm/cplbinit.h>
28 28
29#ifdef CONFIG_MAX_MEM_SIZE
30# define CPLB_MEM CONFIG_MAX_MEM_SIZE
31#else
32# define CPLB_MEM CONFIG_MEM_SIZE
33#endif
34
29/* 35/*
30* Number of required data CPLB switchtable entries 36* Number of required data CPLB switchtable entries
31* MEMSIZE / 4 (we mostly install 4M page size CPLBs 37* MEMSIZE / 4 (we mostly install 4M page size CPLBs
@@ -35,7 +41,7 @@
35* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 41* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
36* 1 for ASYNC Memory 42* 1 for ASYNC Memory
37*/ 43*/
38#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ 44#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
39 + ASYNC_MEMORY_CPLB_COVERAGE) * 2) 45 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
40 46
41/* 47/*
@@ -46,7 +52,7 @@
46* possibly 1 for L2 Instruction Memory 52* possibly 1 for L2 Instruction Memory
47* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO 53* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
48*/ 54*/
49#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) 55#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
50 56
51 57
52u_long icplb_table[MAX_CPLBS + 1]; 58u_long icplb_table[MAX_CPLBS + 1];