diff options
author | Bob Liu <lliubbo@gmail.com> | 2012-05-16 05:37:24 -0400 |
---|---|---|
committer | Bob Liu <lliubbo@gmail.com> | 2012-05-21 02:54:12 -0400 |
commit | b5affb0147cee0ea05d909396f8e389092729236 (patch) | |
tree | 483471450269ac65f7748b5408c7f77520421d55 /arch/blackfin/include | |
parent | 22a826288522863fb748851824ce634eda4f1b07 (diff) |
blackfin: add bf60x to current framework
This patch added bf60x to current blackfin kernel framework.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r-- | arch/blackfin/include/asm/bfin-global.h | 5 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin_dma.h | 84 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin_serial.h | 168 | ||||
-rw-r--r-- | arch/blackfin/include/asm/dma.h | 137 | ||||
-rw-r--r-- | arch/blackfin/include/asm/fixed_code.h | 30 | ||||
-rw-r--r-- | arch/blackfin/include/asm/page.h | 5 |
6 files changed, 375 insertions, 54 deletions
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 17bcbf60bcae..a83e922a878d 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu); | |||
35 | 35 | ||
36 | extern unsigned long get_cclk(void); | 36 | extern unsigned long get_cclk(void); |
37 | extern unsigned long get_sclk(void); | 37 | extern unsigned long get_sclk(void); |
38 | #ifdef CONFIG_BF60x | ||
39 | extern unsigned long get_sclk0(void); | ||
40 | extern unsigned long get_sclk1(void); | ||
41 | extern unsigned long get_dramclk(void); | ||
42 | #endif | ||
38 | extern unsigned long sclk_to_usecs(unsigned long sclk); | 43 | extern unsigned long sclk_to_usecs(unsigned long sclk); |
39 | extern unsigned long usecs_to_sclk(unsigned long usecs); | 44 | extern unsigned long usecs_to_sclk(unsigned long usecs); |
40 | 45 | ||
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h index d51120744148..6319f4e49083 100644 --- a/arch/blackfin/include/asm/bfin_dma.h +++ b/arch/blackfin/include/asm/bfin_dma.h | |||
@@ -15,12 +15,55 @@ | |||
15 | #define DMAEN 0x0001 /* DMA Channel Enable */ | 15 | #define DMAEN 0x0001 /* DMA Channel Enable */ |
16 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | 16 | #define WNR 0x0002 /* Channel Direction (W/R*) */ |
17 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ | 17 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ |
18 | #define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ | ||
19 | |||
20 | #ifdef CONFIG_BF60x | ||
21 | |||
22 | #define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ | ||
23 | #define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ | ||
24 | #define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ | ||
25 | #define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ | ||
26 | #define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ | ||
27 | #define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ | ||
28 | #define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ | ||
29 | #define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ | ||
30 | #define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ | ||
31 | #define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ | ||
32 | #define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ | ||
33 | #define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ | ||
34 | #define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ | ||
35 | #define DI_EN DI_EN_X /* Data Interrupt Enable */ | ||
36 | #define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */ | ||
37 | #define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */ | ||
38 | #define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */ | ||
39 | #define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */ | ||
40 | #define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */ | ||
41 | #define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */ | ||
42 | #define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */ | ||
43 | #define NDSIZE 0x00070000 /* Next Descriptor Size */ | ||
44 | #define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ | ||
45 | #define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ | ||
46 | #define DMAFLOW_LARGE DMAFLOW_LIST | ||
47 | #define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ | ||
48 | #define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ | ||
49 | #define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ | ||
50 | #define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ | ||
51 | #define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ | ||
52 | #define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ | ||
53 | #define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ | ||
54 | |||
55 | #else | ||
56 | |||
57 | #define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ | ||
58 | #define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ | ||
18 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ | 59 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ |
19 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ | 60 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ |
20 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ | 61 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ |
21 | #define RESTART 0x0020 /* DMA Buffer Clear */ | 62 | #define RESTART 0x0020 /* DMA Buffer Clear */ |
22 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ | 63 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ |
23 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | 64 | #define DI_EN 0x0080 /* Data Interrupt Enable */ |
65 | #define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ | ||
66 | #define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ | ||
24 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | 67 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ |
25 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | 68 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ |
26 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | 69 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ |
@@ -32,18 +75,26 @@ | |||
32 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | 75 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ |
33 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | 76 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ |
34 | #define NDSIZE 0x0f00 /* Next Descriptor Size */ | 77 | #define NDSIZE 0x0f00 /* Next Descriptor Size */ |
35 | #define DMAFLOW 0x7000 /* Flow Control */ | 78 | #define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ |
36 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
37 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
38 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | 79 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ |
39 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | 80 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ |
40 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | 81 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ |
82 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | ||
83 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | ||
84 | |||
85 | #endif | ||
86 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
87 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
88 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
41 | 89 | ||
42 | /* DMA_IRQ_STATUS Masks */ | 90 | /* DMA_IRQ_STATUS Masks */ |
43 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ | 91 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ |
44 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ | 92 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ |
45 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | 93 | #ifdef CONFIG_BF60x |
46 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | 94 | #define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */ |
95 | #else | ||
96 | #define DMA_PIRQ 0 | ||
97 | #endif | ||
47 | 98 | ||
48 | /* | 99 | /* |
49 | * All Blackfin system MMRs are padded to 32bits even if the register | 100 | * All Blackfin system MMRs are padded to 32bits even if the register |
@@ -57,6 +108,26 @@ | |||
57 | struct bfin_dma_regs { | 108 | struct bfin_dma_regs { |
58 | u32 next_desc_ptr; | 109 | u32 next_desc_ptr; |
59 | u32 start_addr; | 110 | u32 start_addr; |
111 | #ifdef CONFIG_BF60x | ||
112 | u32 cfg; | ||
113 | u32 x_count; | ||
114 | u32 x_modify; | ||
115 | u32 y_count; | ||
116 | u32 y_modify; | ||
117 | u32 pad1; | ||
118 | u32 pad2; | ||
119 | u32 curr_desc_ptr; | ||
120 | u32 prev_desc_ptr; | ||
121 | u32 curr_addr; | ||
122 | u32 irq_status; | ||
123 | u32 curr_x_count; | ||
124 | u32 curr_y_count; | ||
125 | u32 pad3; | ||
126 | u32 bw_limit_count; | ||
127 | u32 curr_bw_limit_count; | ||
128 | u32 bw_monitor_count; | ||
129 | u32 curr_bw_monitor_count; | ||
130 | #else | ||
60 | __BFP(config); | 131 | __BFP(config); |
61 | u32 __pad0; | 132 | u32 __pad0; |
62 | __BFP(x_count); | 133 | __BFP(x_count); |
@@ -71,8 +142,10 @@ struct bfin_dma_regs { | |||
71 | u32 __pad1; | 142 | u32 __pad1; |
72 | __BFP(curr_y_count); | 143 | __BFP(curr_y_count); |
73 | u32 __pad2; | 144 | u32 __pad2; |
145 | #endif | ||
74 | }; | 146 | }; |
75 | 147 | ||
148 | #ifndef CONFIG_BF60x | ||
76 | /* | 149 | /* |
77 | * bfin handshake mdma registers layout | 150 | * bfin handshake mdma registers layout |
78 | */ | 151 | */ |
@@ -85,6 +158,7 @@ struct bfin_hmdma_regs { | |||
85 | __BFP(ecount); | 158 | __BFP(ecount); |
86 | __BFP(bcount); | 159 | __BFP(bcount); |
87 | }; | 160 | }; |
161 | #endif | ||
88 | 162 | ||
89 | #undef __BFP | 163 | #undef __BFP |
90 | 164 | ||
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 68bcc3d119b6..80a58488dbe7 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h | |||
@@ -18,7 +18,7 @@ | |||
18 | defined(CONFIG_BFIN_UART1_CTSRTS) || \ | 18 | defined(CONFIG_BFIN_UART1_CTSRTS) || \ |
19 | defined(CONFIG_BFIN_UART2_CTSRTS) || \ | 19 | defined(CONFIG_BFIN_UART2_CTSRTS) || \ |
20 | defined(CONFIG_BFIN_UART3_CTSRTS) | 20 | defined(CONFIG_BFIN_UART3_CTSRTS) |
21 | # ifdef BFIN_UART_BF54X_STYLE | 21 | # if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE) |
22 | # define CONFIG_SERIAL_BFIN_HARD_CTSRTS | 22 | # define CONFIG_SERIAL_BFIN_HARD_CTSRTS |
23 | # else | 23 | # else |
24 | # define CONFIG_SERIAL_BFIN_CTSRTS | 24 | # define CONFIG_SERIAL_BFIN_CTSRTS |
@@ -58,14 +58,67 @@ struct bfin_serial_port { | |||
58 | #endif | 58 | #endif |
59 | }; | 59 | }; |
60 | 60 | ||
61 | #ifdef BFIN_UART_BF60X_STYLE | ||
62 | |||
63 | /* UART_CTL Masks */ | ||
64 | #define UCEN 0x1 /* Enable UARTx Clocks */ | ||
65 | #define LOOP_ENA 0x2 /* Loopback Mode Enable */ | ||
66 | #define UMOD_MDB 0x10 /* Enable MDB Mode */ | ||
67 | #define UMOD_IRDA 0x20 /* Enable IrDA Mode */ | ||
68 | #define UMOD_MASK 0x30 /* Uart Mode Mask */ | ||
69 | #define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ | ||
70 | #define WLS_MASK 0x300 /* Word length Select Mask */ | ||
71 | #define STB 0x1000 /* Stop Bits */ | ||
72 | #define STBH 0x2000 /* Half Stop Bits */ | ||
73 | #define PEN 0x4000 /* Parity Enable */ | ||
74 | #define EPS 0x8000 /* Even Parity Select */ | ||
75 | #define STP 0x10000 /* Stick Parity */ | ||
76 | #define FPE 0x20000 /* Force Parity Error On Transmit */ | ||
77 | #define FFE 0x40000 /* Force Framing Error On Transmit */ | ||
78 | #define SB 0x80000 /* Set Break */ | ||
79 | #define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK) | ||
80 | #define FCPOL 0x400000 /* Flow Control Pin Polarity */ | ||
81 | #define RPOLC 0x800000 /* IrDA RX Polarity Change */ | ||
82 | #define TPOLC 0x1000000 /* IrDA TX Polarity Change */ | ||
83 | #define MRTS 0x2000000 /* Manual Request To Send */ | ||
84 | #define XOFF 0x4000000 /* Transmitter Off */ | ||
85 | #define ARTS 0x8000000 /* Automatic Request To Send */ | ||
86 | #define ACTS 0x10000000 /* Automatic Clear To Send */ | ||
87 | #define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */ | ||
88 | #define RFRT 0x40000000 /* Receive FIFO RTS Threshold */ | ||
89 | |||
90 | /* UART_STAT Masks */ | ||
91 | #define DR 0x01 /* Data Ready */ | ||
92 | #define OE 0x02 /* Overrun Error */ | ||
93 | #define PE 0x04 /* Parity Error */ | ||
94 | #define FE 0x08 /* Framing Error */ | ||
95 | #define BI 0x10 /* Break Interrupt */ | ||
96 | #define THRE 0x20 /* THR Empty */ | ||
97 | #define TEMT 0x80 /* TSR and UART_THR Empty */ | ||
98 | #define TFI 0x100 /* Transmission Finished Indicator */ | ||
99 | |||
100 | #define ASTKY 0x200 /* Address Sticky */ | ||
101 | #define ADDR 0x400 /* Address bit status */ | ||
102 | #define RO 0x800 /* Reception Ongoing */ | ||
103 | #define SCTS 0x1000 /* Sticky CTS */ | ||
104 | #define CTS 0x10000 /* Clear To Send */ | ||
105 | #define RFCS 0x20000 /* Receive FIFO Count Status */ | ||
106 | |||
107 | /* UART_CLOCK Masks */ | ||
108 | #define EDBO 0x80000000 /* Enable Devide by One */ | ||
109 | |||
110 | #else /* BFIN_UART_BF60X_STYLE */ | ||
111 | |||
61 | /* UART_LCR Masks */ | 112 | /* UART_LCR Masks */ |
62 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | 113 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ |
114 | #define WLS_MASK 0x03 /* Word length Select Mask */ | ||
63 | #define STB 0x04 /* Stop Bits */ | 115 | #define STB 0x04 /* Stop Bits */ |
64 | #define PEN 0x08 /* Parity Enable */ | 116 | #define PEN 0x08 /* Parity Enable */ |
65 | #define EPS 0x10 /* Even Parity Select */ | 117 | #define EPS 0x10 /* Even Parity Select */ |
66 | #define STP 0x20 /* Stick Parity */ | 118 | #define STP 0x20 /* Stick Parity */ |
67 | #define SB 0x40 /* Set Break */ | 119 | #define SB 0x40 /* Set Break */ |
68 | #define DLAB 0x80 /* Divisor Latch Access */ | 120 | #define DLAB 0x80 /* Divisor Latch Access */ |
121 | #define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK) | ||
69 | 122 | ||
70 | /* UART_LSR Masks */ | 123 | /* UART_LSR Masks */ |
71 | #define DR 0x01 /* Data Ready */ | 124 | #define DR 0x01 /* Data Ready */ |
@@ -77,15 +130,6 @@ struct bfin_serial_port { | |||
77 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | 130 | #define TEMT 0x40 /* TSR and UART_THR Empty */ |
78 | #define TFI 0x80 /* Transmission Finished Indicator */ | 131 | #define TFI 0x80 /* Transmission Finished Indicator */ |
79 | 132 | ||
80 | /* UART_IER Masks */ | ||
81 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | ||
82 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | ||
83 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | ||
84 | #define EDSSI 0x08 /* Enable Modem Status Interrupt */ | ||
85 | #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
86 | #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ | ||
87 | #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
88 | |||
89 | /* UART_MCR Masks */ | 133 | /* UART_MCR Masks */ |
90 | #define XOFF 0x01 /* Transmitter Off */ | 134 | #define XOFF 0x01 /* Transmitter Off */ |
91 | #define MRTS 0x02 /* Manual Request To Send */ | 135 | #define MRTS 0x02 /* Manual Request To Send */ |
@@ -103,13 +147,36 @@ struct bfin_serial_port { | |||
103 | 147 | ||
104 | /* UART_GCTL Masks */ | 148 | /* UART_GCTL Masks */ |
105 | #define UCEN 0x01 /* Enable UARTx Clocks */ | 149 | #define UCEN 0x01 /* Enable UARTx Clocks */ |
106 | #define IREN 0x02 /* Enable IrDA Mode */ | 150 | #define UMOD_IRDA 0x02 /* Enable IrDA Mode */ |
151 | #define UMOD_MASK 0x02 /* Uart Mode Mask */ | ||
107 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ | 152 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ |
108 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | 153 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ |
109 | #define FPE 0x10 /* Force Parity Error On Transmit */ | 154 | #define FPE 0x10 /* Force Parity Error On Transmit */ |
110 | #define FFE 0x20 /* Force Framing Error On Transmit */ | 155 | #define FFE 0x20 /* Force Framing Error On Transmit */ |
111 | 156 | ||
112 | #ifdef BFIN_UART_BF54X_STYLE | 157 | #endif /* BFIN_UART_BF60X_STYLE */ |
158 | |||
159 | /* UART_IER Masks */ | ||
160 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | ||
161 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | ||
162 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | ||
163 | #define EDSSI 0x08 /* Enable Modem Status Interrupt */ | ||
164 | #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
165 | #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ | ||
166 | #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
167 | |||
168 | #if defined(BFIN_UART_BF60X_STYLE) | ||
169 | # define OFFSET_REDIV 0x00 /* Version ID Register */ | ||
170 | # define OFFSET_CTL 0x04 /* Control Register */ | ||
171 | # define OFFSET_STAT 0x08 /* Status Register */ | ||
172 | # define OFFSET_SCR 0x0C /* SCR Scratch Register */ | ||
173 | # define OFFSET_CLK 0x10 /* Clock Rate Register */ | ||
174 | # define OFFSET_IER 0x14 /* Interrupt Enable Register */ | ||
175 | # define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */ | ||
176 | # define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */ | ||
177 | # define OFFSET_RBR 0x20 /* Receive Buffer register */ | ||
178 | # define OFFSET_THR 0x24 /* Transmit Holding register */ | ||
179 | #elif defined(BFIN_UART_BF54X_STYLE) | ||
113 | # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 180 | # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
114 | # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | 181 | # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ |
115 | # define OFFSET_GCTL 0x08 /* Global Control Register */ | 182 | # define OFFSET_GCTL 0x08 /* Global Control Register */ |
@@ -145,7 +212,23 @@ struct bfin_serial_port { | |||
145 | */ | 212 | */ |
146 | #define __BFP(m) u16 m; u16 __pad_##m | 213 | #define __BFP(m) u16 m; u16 __pad_##m |
147 | struct bfin_uart_regs { | 214 | struct bfin_uart_regs { |
148 | #ifdef BFIN_UART_BF54X_STYLE | 215 | #if defined(BFIN_UART_BF60X_STYLE) |
216 | u32 revid; | ||
217 | u32 ctl; | ||
218 | u32 stat; | ||
219 | u32 scr; | ||
220 | u32 clk; | ||
221 | u32 ier; | ||
222 | u32 ier_set; | ||
223 | u32 ier_clear; | ||
224 | u32 rbr; | ||
225 | u32 thr; | ||
226 | u32 taip; | ||
227 | u32 tsr; | ||
228 | u32 rsr; | ||
229 | u32 txdiv; | ||
230 | u32 rxdiv; | ||
231 | #elif defined(BFIN_UART_BF54X_STYLE) | ||
149 | __BFP(dll); | 232 | __BFP(dll); |
150 | __BFP(dlh); | 233 | __BFP(dlh); |
151 | __BFP(gctl); | 234 | __BFP(gctl); |
@@ -182,13 +265,58 @@ struct bfin_uart_regs { | |||
182 | }; | 265 | }; |
183 | #undef __BFP | 266 | #undef __BFP |
184 | 267 | ||
268 | #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) | ||
269 | |||
270 | /* | ||
185 | #ifndef port_membase | 271 | #ifndef port_membase |
186 | # define port_membase(p) 0 | 272 | # define port_membase(p) 0 |
187 | #endif | 273 | #endif |
274 | */ | ||
275 | #ifdef BFIN_UART_BF60X_STYLE | ||
276 | |||
277 | #define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR) | ||
278 | #define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK) | ||
279 | #define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL) | ||
280 | #define UART_GET_GCTL(p) UART_GET_CTL(p) | ||
281 | #define UART_GET_LCR(p) UART_GET_CTL(p) | ||
282 | #define UART_GET_MCR(p) UART_GET_CTL(p) | ||
283 | #define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT) | ||
284 | #define UART_GET_MSR(p) UART_GET_STAT(p) | ||
285 | |||
286 | #define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v) | ||
287 | #define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v) | ||
288 | #define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v) | ||
289 | #define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v) | ||
290 | #define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v) | ||
291 | #define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v) | ||
292 | #define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v) | ||
293 | |||
294 | #define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v) | ||
295 | #define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER) | ||
296 | #define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v) | ||
297 | |||
298 | #define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */ | ||
299 | #define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */ | ||
300 | |||
301 | #define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1) | ||
302 | #define UART_GET_LSR(p) UART_GET_STAT(p) | ||
303 | #define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v) | ||
304 | |||
305 | /* This handles hard CTS/RTS */ | ||
306 | #define BFIN_UART_CTSRTS_HARD | ||
307 | #define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS) | ||
308 | #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) | ||
309 | #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) | ||
310 | #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) | ||
311 | #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) | ||
312 | #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) | ||
313 | |||
314 | #else /* BFIN_UART_BF60X_STYLE */ | ||
188 | 315 | ||
189 | #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) | 316 | #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) |
190 | #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) | 317 | #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) |
191 | #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) | 318 | #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) |
319 | #define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p)) | ||
192 | #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) | 320 | #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) |
193 | #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) | 321 | #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) |
194 | #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) | 322 | #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) |
@@ -197,6 +325,11 @@ struct bfin_uart_regs { | |||
197 | #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) | 325 | #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) |
198 | #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) | 326 | #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) |
199 | #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) | 327 | #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) |
328 | #define UART_PUT_CLK(p, v) do \ | ||
329 | {\ | ||
330 | UART_PUT_DLL(p, v & 0xFF); \ | ||
331 | UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0); | ||
332 | |||
200 | #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) | 333 | #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) |
201 | #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) | 334 | #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) |
202 | #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) | 335 | #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) |
@@ -233,12 +366,17 @@ struct bfin_uart_regs { | |||
233 | #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) | 366 | #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) |
234 | #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) | 367 | #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) |
235 | 368 | ||
369 | #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) | ||
370 | #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) | ||
371 | |||
372 | /* | ||
236 | #ifndef put_lsr_cache | 373 | #ifndef put_lsr_cache |
237 | # define put_lsr_cache(p, v) | 374 | # define put_lsr_cache(p, v) |
238 | #endif | 375 | #endif |
239 | #ifndef get_lsr_cache | 376 | #ifndef get_lsr_cache |
240 | # define get_lsr_cache(p) 0 | 377 | # define get_lsr_cache(p) 0 |
241 | #endif | 378 | #endif |
379 | */ | ||
242 | 380 | ||
243 | /* The hardware clears the LSR bits upon read, so we need to cache | 381 | /* The hardware clears the LSR bits upon read, so we need to cache |
244 | * some of the more fun bits in software so they don't get lost | 382 | * some of the more fun bits in software so they don't get lost |
@@ -267,7 +405,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val) | |||
267 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | 405 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) |
268 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | 406 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) |
269 | 407 | ||
270 | #endif | 408 | #endif /* BFIN_UART_BF54X_STYLE */ |
409 | |||
410 | #endif /* BFIN_UART_BF60X_STYLE */ | ||
271 | 411 | ||
272 | #ifndef BFIN_UART_TX_FIFO_SIZE | 412 | #ifndef BFIN_UART_TX_FIFO_SIZE |
273 | # define BFIN_UART_TX_FIFO_SIZE 2 | 413 | # define BFIN_UART_TX_FIFO_SIZE 2 |
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index dac0c97242bb..40e9c2bbc6e3 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h | |||
@@ -22,12 +22,22 @@ | |||
22 | #define DATA_SIZE_8 0 | 22 | #define DATA_SIZE_8 0 |
23 | #define DATA_SIZE_16 1 | 23 | #define DATA_SIZE_16 1 |
24 | #define DATA_SIZE_32 2 | 24 | #define DATA_SIZE_32 2 |
25 | #ifdef CONFIG_BF60x | ||
26 | #define DATA_SIZE_64 3 | ||
27 | #endif | ||
25 | 28 | ||
26 | #define DMA_FLOW_STOP 0 | 29 | #define DMA_FLOW_STOP 0 |
27 | #define DMA_FLOW_AUTO 1 | 30 | #define DMA_FLOW_AUTO 1 |
31 | #ifdef CONFIG_BF60x | ||
32 | #define DMA_FLOW_LIST 4 | ||
33 | #define DMA_FLOW_ARRAY 5 | ||
34 | #define DMA_FLOW_LIST_DEMAND 6 | ||
35 | #define DMA_FLOW_ARRAY_DEMAND 7 | ||
36 | #else | ||
28 | #define DMA_FLOW_ARRAY 4 | 37 | #define DMA_FLOW_ARRAY 4 |
29 | #define DMA_FLOW_SMALL 6 | 38 | #define DMA_FLOW_SMALL 6 |
30 | #define DMA_FLOW_LARGE 7 | 39 | #define DMA_FLOW_LARGE 7 |
40 | #endif | ||
31 | 41 | ||
32 | #define DIMENSION_LINEAR 0 | 42 | #define DIMENSION_LINEAR 0 |
33 | #define DIMENSION_2D 1 | 43 | #define DIMENSION_2D 1 |
@@ -36,26 +46,80 @@ | |||
36 | #define DIR_WRITE 1 | 46 | #define DIR_WRITE 1 |
37 | 47 | ||
38 | #define INTR_DISABLE 0 | 48 | #define INTR_DISABLE 0 |
49 | #ifdef CONFIG_BF60x | ||
50 | #define INTR_ON_PERI 1 | ||
51 | #endif | ||
39 | #define INTR_ON_BUF 2 | 52 | #define INTR_ON_BUF 2 |
40 | #define INTR_ON_ROW 3 | 53 | #define INTR_ON_ROW 3 |
41 | 54 | ||
42 | #define DMA_NOSYNC_KEEP_DMA_BUF 0 | 55 | #define DMA_NOSYNC_KEEP_DMA_BUF 0 |
43 | #define DMA_SYNC_RESTART 1 | 56 | #define DMA_SYNC_RESTART 1 |
44 | 57 | ||
58 | #ifdef DMA_MMR_SIZE_32 | ||
59 | #define DMA_MMR_SIZE_TYPE long | ||
60 | #define DMA_MMR_READ bfin_read32 | ||
61 | #define DMA_MMR_WRITE bfin_write32 | ||
62 | #else | ||
63 | #define DMA_MMR_SIZE_TYPE short | ||
64 | #define DMA_MMR_READ bfin_read16 | ||
65 | #define DMA_MMR_WRITE bfin_write16 | ||
66 | #endif | ||
67 | |||
68 | struct dma_desc_array { | ||
69 | unsigned long start_addr; | ||
70 | unsigned DMA_MMR_SIZE_TYPE cfg; | ||
71 | unsigned DMA_MMR_SIZE_TYPE x_count; | ||
72 | DMA_MMR_SIZE_TYPE x_modify; | ||
73 | } __attribute__((packed)); | ||
74 | |||
45 | struct dmasg { | 75 | struct dmasg { |
46 | void *next_desc_addr; | 76 | void *next_desc_addr; |
47 | unsigned long start_addr; | 77 | unsigned long start_addr; |
48 | unsigned short cfg; | 78 | unsigned DMA_MMR_SIZE_TYPE cfg; |
49 | unsigned short x_count; | 79 | unsigned DMA_MMR_SIZE_TYPE x_count; |
50 | short x_modify; | 80 | DMA_MMR_SIZE_TYPE x_modify; |
51 | unsigned short y_count; | 81 | unsigned DMA_MMR_SIZE_TYPE y_count; |
52 | short y_modify; | 82 | DMA_MMR_SIZE_TYPE y_modify; |
53 | } __attribute__((packed)); | 83 | } __attribute__((packed)); |
54 | 84 | ||
55 | struct dma_register { | 85 | struct dma_register { |
56 | void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ | 86 | void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ |
57 | unsigned long start_addr; /* DMA Start address register */ | 87 | unsigned long start_addr; /* DMA Start address register */ |
88 | #ifdef CONFIG_BF60x | ||
89 | unsigned long cfg; /* DMA Configuration register */ | ||
58 | 90 | ||
91 | unsigned long x_count; /* DMA x_count register */ | ||
92 | |||
93 | long x_modify; /* DMA x_modify register */ | ||
94 | |||
95 | unsigned long y_count; /* DMA y_count register */ | ||
96 | |||
97 | long y_modify; /* DMA y_modify register */ | ||
98 | |||
99 | unsigned long reserved; | ||
100 | unsigned long reserved2; | ||
101 | |||
102 | void *curr_desc_ptr; /* DMA Current Descriptor Pointer | ||
103 | register */ | ||
104 | void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer | ||
105 | register */ | ||
106 | unsigned long curr_addr_ptr; /* DMA Current Address Pointer | ||
107 | register */ | ||
108 | unsigned long irq_status; /* DMA irq status register */ | ||
109 | |||
110 | unsigned long curr_x_count; /* DMA Current x-count register */ | ||
111 | |||
112 | unsigned long curr_y_count; /* DMA Current y-count register */ | ||
113 | |||
114 | unsigned long reserved3; | ||
115 | |||
116 | unsigned long bw_limit_count; /* DMA band width limit count register */ | ||
117 | unsigned long curr_bw_limit_count; /* DMA Current band width limit | ||
118 | count register */ | ||
119 | unsigned long bw_monitor_count; /* DMA band width limit count register */ | ||
120 | unsigned long curr_bw_monitor_count; /* DMA Current band width limit | ||
121 | count register */ | ||
122 | #else | ||
59 | unsigned short cfg; /* DMA Configuration register */ | 123 | unsigned short cfg; /* DMA Configuration register */ |
60 | unsigned short dummy1; /* DMA Configuration register */ | 124 | unsigned short dummy1; /* DMA Configuration register */ |
61 | 125 | ||
@@ -92,6 +156,7 @@ struct dma_register { | |||
92 | unsigned short dummy9; | 156 | unsigned short dummy9; |
93 | 157 | ||
94 | unsigned long reserved3; | 158 | unsigned long reserved3; |
159 | #endif | ||
95 | 160 | ||
96 | }; | 161 | }; |
97 | 162 | ||
@@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) | |||
131 | { | 196 | { |
132 | dma_ch[channel].regs->curr_desc_ptr = addr; | 197 | dma_ch[channel].regs->curr_desc_ptr = addr; |
133 | } | 198 | } |
134 | static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) | 199 | static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count) |
135 | { | 200 | { |
136 | dma_ch[channel].regs->x_count = x_count; | 201 | dma_ch[channel].regs->x_count = x_count; |
137 | } | 202 | } |
138 | static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) | 203 | static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count) |
139 | { | 204 | { |
140 | dma_ch[channel].regs->y_count = y_count; | 205 | dma_ch[channel].regs->y_count = y_count; |
141 | } | 206 | } |
142 | static inline void set_dma_x_modify(unsigned int channel, short x_modify) | 207 | static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify) |
143 | { | 208 | { |
144 | dma_ch[channel].regs->x_modify = x_modify; | 209 | dma_ch[channel].regs->x_modify = x_modify; |
145 | } | 210 | } |
146 | static inline void set_dma_y_modify(unsigned int channel, short y_modify) | 211 | static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify) |
147 | { | 212 | { |
148 | dma_ch[channel].regs->y_modify = y_modify; | 213 | dma_ch[channel].regs->y_modify = y_modify; |
149 | } | 214 | } |
150 | static inline void set_dma_config(unsigned int channel, unsigned short config) | 215 | static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config) |
151 | { | 216 | { |
152 | dma_ch[channel].regs->cfg = config; | 217 | dma_ch[channel].regs->cfg = config; |
153 | } | 218 | } |
@@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) | |||
156 | dma_ch[channel].regs->curr_addr_ptr = addr; | 221 | dma_ch[channel].regs->curr_addr_ptr = addr; |
157 | } | 222 | } |
158 | 223 | ||
159 | static inline unsigned short | 224 | #ifdef CONFIG_BF60x |
225 | static inline unsigned long | ||
226 | set_bfin_dma_config2(char direction, char flow_mode, char intr_mode, | ||
227 | char dma_mode, char mem_width, char syncmode, char peri_width) | ||
228 | { | ||
229 | unsigned long config = 0; | ||
230 | |||
231 | switch (intr_mode) { | ||
232 | case INTR_ON_BUF: | ||
233 | if (dma_mode == DIMENSION_2D) | ||
234 | config = DI_EN_Y; | ||
235 | else | ||
236 | config = DI_EN_X; | ||
237 | break; | ||
238 | case INTR_ON_ROW: | ||
239 | config = DI_EN_X; | ||
240 | break; | ||
241 | case INTR_ON_PERI: | ||
242 | config = DI_EN_P; | ||
243 | break; | ||
244 | }; | ||
245 | |||
246 | return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) | | ||
247 | (flow_mode << 12) | (syncmode << 2) | (peri_width << 4); | ||
248 | } | ||
249 | #endif | ||
250 | |||
251 | static inline unsigned DMA_MMR_SIZE_TYPE | ||
160 | set_bfin_dma_config(char direction, char flow_mode, | 252 | set_bfin_dma_config(char direction, char flow_mode, |
161 | char intr_mode, char dma_mode, char width, char syncmode) | 253 | char intr_mode, char dma_mode, char mem_width, char syncmode) |
162 | { | 254 | { |
163 | return (direction << 1) | (width << 2) | (dma_mode << 4) | | 255 | #ifdef CONFIG_BF60x |
256 | return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode, | ||
257 | mem_width, syncmode, mem_width); | ||
258 | #else | ||
259 | return (direction << 1) | (mem_width << 2) | (dma_mode << 4) | | ||
164 | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); | 260 | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); |
261 | #endif | ||
165 | } | 262 | } |
166 | 263 | ||
167 | static inline unsigned short get_dma_curr_irqstat(unsigned int channel) | 264 | static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel) |
168 | { | 265 | { |
169 | return dma_ch[channel].regs->irq_status; | 266 | return dma_ch[channel].regs->irq_status; |
170 | } | 267 | } |
171 | static inline unsigned short get_dma_curr_xcount(unsigned int channel) | 268 | static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel) |
172 | { | 269 | { |
173 | return dma_ch[channel].regs->curr_x_count; | 270 | return dma_ch[channel].regs->curr_x_count; |
174 | } | 271 | } |
175 | static inline unsigned short get_dma_curr_ycount(unsigned int channel) | 272 | static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel) |
176 | { | 273 | { |
177 | return dma_ch[channel].regs->curr_y_count; | 274 | return dma_ch[channel].regs->curr_y_count; |
178 | } | 275 | } |
@@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel) | |||
184 | { | 281 | { |
185 | return dma_ch[channel].regs->curr_desc_ptr; | 282 | return dma_ch[channel].regs->curr_desc_ptr; |
186 | } | 283 | } |
187 | static inline unsigned short get_dma_config(unsigned int channel) | 284 | static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel) |
188 | { | 285 | { |
189 | return dma_ch[channel].regs->cfg; | 286 | return dma_ch[channel].regs->cfg; |
190 | } | 287 | } |
@@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize | |||
203 | 300 | ||
204 | dma_ch[channel].regs->next_desc_ptr = sg; | 301 | dma_ch[channel].regs->next_desc_ptr = sg; |
205 | dma_ch[channel].regs->cfg = | 302 | dma_ch[channel].regs->cfg = |
206 | (dma_ch[channel].regs->cfg & ~(0xf << 8)) | | 303 | (dma_ch[channel].regs->cfg & ~NDSIZE) | |
207 | ((ndsize & 0xf) << 8); | 304 | ((ndsize << NDSIZE_OFFSET) & NDSIZE); |
208 | } | 305 | } |
209 | 306 | ||
210 | static inline int dma_channel_active(unsigned int channel) | 307 | static inline int dma_channel_active(unsigned int channel) |
@@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel) | |||
239 | } | 336 | } |
240 | static inline void clear_dma_irqstat(unsigned int channel) | 337 | static inline void clear_dma_irqstat(unsigned int channel) |
241 | { | 338 | { |
242 | dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; | 339 | dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ; |
243 | } | 340 | } |
244 | 341 | ||
245 | void *dma_memcpy(void *dest, const void *src, size_t count); | 342 | void *dma_memcpy(void *dest, const void *src, size_t count); |
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h index 73fe53e7fd24..5395088b2d0e 100644 --- a/arch/blackfin/include/asm/fixed_code.h +++ b/arch/blackfin/include/asm/fixed_code.h | |||
@@ -29,24 +29,28 @@ extern void sigreturn_stub(void); | |||
29 | #endif | 29 | #endif |
30 | #endif | 30 | #endif |
31 | 31 | ||
32 | #define FIXED_CODE_START 0x400 | 32 | #ifndef CONFIG_PHY_RAM_BASE_ADDRESS |
33 | #define CONFIG_PHY_RAM_BASE_ADDRESS 0x0 | ||
34 | #endif | ||
35 | |||
36 | #define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) | ||
33 | 37 | ||
34 | #define SIGRETURN_STUB 0x400 | 38 | #define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) |
35 | 39 | ||
36 | #define ATOMIC_SEQS_START 0x410 | 40 | #define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) |
37 | 41 | ||
38 | #define ATOMIC_XCHG32 0x410 | 42 | #define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) |
39 | #define ATOMIC_CAS32 0x420 | 43 | #define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420) |
40 | #define ATOMIC_ADD32 0x430 | 44 | #define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430) |
41 | #define ATOMIC_SUB32 0x440 | 45 | #define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440) |
42 | #define ATOMIC_IOR32 0x450 | 46 | #define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450) |
43 | #define ATOMIC_AND32 0x460 | 47 | #define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460) |
44 | #define ATOMIC_XOR32 0x470 | 48 | #define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470) |
45 | 49 | ||
46 | #define ATOMIC_SEQS_END 0x480 | 50 | #define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) |
47 | 51 | ||
48 | #define SAFE_USER_INSTRUCTION 0x480 | 52 | #define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) |
49 | 53 | ||
50 | #define FIXED_CODE_END 0x490 | 54 | #define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490) |
51 | 55 | ||
52 | #endif | 56 | #endif |
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h index 7202404966f6..b93474d5be75 100644 --- a/arch/blackfin/include/asm/page.h +++ b/arch/blackfin/include/asm/page.h | |||
@@ -7,14 +7,15 @@ | |||
7 | #ifndef _BLACKFIN_PAGE_H | 7 | #ifndef _BLACKFIN_PAGE_H |
8 | #define _BLACKFIN_PAGE_H | 8 | #define _BLACKFIN_PAGE_H |
9 | 9 | ||
10 | #include <asm-generic/page.h> | 10 | #define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT) |
11 | #define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) | 11 | #define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT) |
12 | 12 | ||
13 | #define VM_DATA_DEFAULT_FLAGS \ | 13 | #define VM_DATA_DEFAULT_FLAGS \ |
14 | (VM_READ | VM_WRITE | \ | 14 | (VM_READ | VM_WRITE | \ |
15 | ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ | 15 | ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ |
16 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | 16 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) |
17 | 17 | ||
18 | #include <asm-generic/page.h> | ||
18 | #include <asm-generic/memory_model.h> | 19 | #include <asm-generic/memory_model.h> |
19 | #include <asm-generic/getorder.h> | 20 | #include <asm-generic/getorder.h> |
20 | 21 | ||