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authorSonic Zhang <sonic.zhang@analog.com>2012-04-26 04:51:29 -0400
committerBob Liu <lliubbo@gmail.com>2012-05-21 02:54:31 -0400
commit8e2f524fd99d0f5574c4323006e29c1f3d5d564e (patch)
tree9f7536ddbac9ded6315151d34067e632eec6a39a /arch/blackfin/include/asm
parentde450838314cd96033b2d2c88b11323efb500fc9 (diff)
blackfin: bf60x: bfin_uart: Add more LCR bits masks
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 80a58488dbe7..235c72a1f92d 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -68,6 +68,7 @@ struct bfin_serial_port {
68#define UMOD_MASK 0x30 /* Uart Mode Mask */ 68#define UMOD_MASK 0x30 /* Uart Mode Mask */
69#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ 69#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
70#define WLS_MASK 0x300 /* Word length Select Mask */ 70#define WLS_MASK 0x300 /* Word length Select Mask */
71#define WLS_OFFSET 8 /* Word length Select Offset */
71#define STB 0x1000 /* Stop Bits */ 72#define STB 0x1000 /* Stop Bits */
72#define STBH 0x2000 /* Half Stop Bits */ 73#define STBH 0x2000 /* Half Stop Bits */
73#define PEN 0x4000 /* Parity Enable */ 74#define PEN 0x4000 /* Parity Enable */
@@ -76,7 +77,7 @@ struct bfin_serial_port {
76#define FPE 0x20000 /* Force Parity Error On Transmit */ 77#define FPE 0x20000 /* Force Parity Error On Transmit */
77#define FFE 0x40000 /* Force Framing Error On Transmit */ 78#define FFE 0x40000 /* Force Framing Error On Transmit */
78#define SB 0x80000 /* Set Break */ 79#define SB 0x80000 /* Set Break */
79#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK) 80#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
80#define FCPOL 0x400000 /* Flow Control Pin Polarity */ 81#define FCPOL 0x400000 /* Flow Control Pin Polarity */
81#define RPOLC 0x800000 /* IrDA RX Polarity Change */ 82#define RPOLC 0x800000 /* IrDA RX Polarity Change */
82#define TPOLC 0x1000000 /* IrDA TX Polarity Change */ 83#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
@@ -112,13 +113,14 @@ struct bfin_serial_port {
112/* UART_LCR Masks */ 113/* UART_LCR Masks */
113#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 114#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
114#define WLS_MASK 0x03 /* Word length Select Mask */ 115#define WLS_MASK 0x03 /* Word length Select Mask */
116#define WLS_OFFSET 0 /* Word length Select Offset */
115#define STB 0x04 /* Stop Bits */ 117#define STB 0x04 /* Stop Bits */
116#define PEN 0x08 /* Parity Enable */ 118#define PEN 0x08 /* Parity Enable */
117#define EPS 0x10 /* Even Parity Select */ 119#define EPS 0x10 /* Even Parity Select */
118#define STP 0x20 /* Stick Parity */ 120#define STP 0x20 /* Stick Parity */
119#define SB 0x40 /* Set Break */ 121#define SB 0x40 /* Set Break */
120#define DLAB 0x80 /* Divisor Latch Access */ 122#define DLAB 0x80 /* Divisor Latch Access */
121#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK) 123#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
122 124
123/* UART_LSR Masks */ 125/* UART_LSR Masks */
124#define DR 0x01 /* Data Ready */ 126#define DR 0x01 /* Data Ready */