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authorSonic Zhang <sonic.zhang@analog.com>2014-01-28 03:55:21 -0500
committerWolfram Sang <wsa@the-dreams.de>2014-03-09 03:40:41 -0400
commit45126da22452ac3d4685401a1e921a39ac0ff2f6 (patch)
tree2b8663693215065023c3571f30d106276bc4e6ec /arch/blackfin/include/asm
parent80c69915e5fbe6493119d87eee2a2a6a7115c74c (diff)
i2c: bfin-twi: move bits macros and structs in header from arch include to generic include
The ADI TWI peripheral is not binding to the Blackfin processor only. The bits macros and structs should be put in the generic include header. And update head file path in drivers accordingly. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h126
1 files changed, 1 insertions, 125 deletions
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index 90c3c006557d..34cc395f8b77 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -9,60 +9,7 @@
9#ifndef __ASM_BFIN_TWI_H__ 9#ifndef __ASM_BFIN_TWI_H__
10#define __ASM_BFIN_TWI_H__ 10#define __ASM_BFIN_TWI_H__
11 11
12#include <linux/types.h> 12#include <asm/blackfin.h>
13#include <linux/i2c.h>
14
15/*
16 * All Blackfin system MMRs are padded to 32bits even if the register
17 * itself is only 16bits. So use a helper macro to streamline this.
18 */
19#define __BFP(m) u16 m; u16 __pad_##m
20
21/*
22 * bfin twi registers layout
23 */
24struct bfin_twi_regs {
25 __BFP(clkdiv);
26 __BFP(control);
27 __BFP(slave_ctl);
28 __BFP(slave_stat);
29 __BFP(slave_addr);
30 __BFP(master_ctl);
31 __BFP(master_stat);
32 __BFP(master_addr);
33 __BFP(int_stat);
34 __BFP(int_mask);
35 __BFP(fifo_ctl);
36 __BFP(fifo_stat);
37 u32 __pad[20];
38 __BFP(xmt_data8);
39 __BFP(xmt_data16);
40 __BFP(rcv_data8);
41 __BFP(rcv_data16);
42};
43
44#undef __BFP
45
46struct bfin_twi_iface {
47 int irq;
48 spinlock_t lock;
49 char read_write;
50 u8 command;
51 u8 *transPtr;
52 int readNum;
53 int writeNum;
54 int cur_mode;
55 int manual_stop;
56 int result;
57 struct i2c_adapter adap;
58 struct completion complete;
59 struct i2c_msg *pmsg;
60 int msg_num;
61 int cur_msg;
62 u16 saved_clkdiv;
63 u16 saved_control;
64 struct bfin_twi_regs __iomem *regs_base;
65};
66 13
67#define DEFINE_TWI_REG(reg_name, reg) \ 14#define DEFINE_TWI_REG(reg_name, reg) \
68static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ 15static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
@@ -113,75 +60,4 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
113} 60}
114#endif 61#endif
115 62
116
117/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
118/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
119#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
120#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
121
122/* TWI_PRESCALE Masks */
123#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
124#define TWI_ENA 0x0080 /* TWI Enable */
125#define SCCB 0x0200 /* SCCB Compatibility Enable */
126
127/* TWI_SLAVE_CTL Masks */
128#define SEN 0x0001 /* Slave Enable */
129#define SADD_LEN 0x0002 /* Slave Address Length */
130#define STDVAL 0x0004 /* Slave Transmit Data Valid */
131#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
132#define GEN 0x0010 /* General Call Address Matching Enabled */
133
134/* TWI_SLAVE_STAT Masks */
135#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
136#define GCALL 0x0002 /* General Call Indicator */
137
138/* TWI_MASTER_CTL Masks */
139#define MEN 0x0001 /* Master Mode Enable */
140#define MADD_LEN 0x0002 /* Master Address Length */
141#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
142#define FAST 0x0008 /* Use Fast Mode Timing Specs */
143#define STOP 0x0010 /* Issue Stop Condition */
144#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
145#define DCNT 0x3FC0 /* Data Bytes To Transfer */
146#define SDAOVR 0x4000 /* Serial Data Override */
147#define SCLOVR 0x8000 /* Serial Clock Override */
148
149/* TWI_MASTER_STAT Masks */
150#define MPROG 0x0001 /* Master Transfer In Progress */
151#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
152#define ANAK 0x0004 /* Address Not Acknowledged */
153#define DNAK 0x0008 /* Data Not Acknowledged */
154#define BUFRDERR 0x0010 /* Buffer Read Error */
155#define BUFWRERR 0x0020 /* Buffer Write Error */
156#define SDASEN 0x0040 /* Serial Data Sense */
157#define SCLSEN 0x0080 /* Serial Clock Sense */
158#define BUSBUSY 0x0100 /* Bus Busy Indicator */
159
160/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
161#define SINIT 0x0001 /* Slave Transfer Initiated */
162#define SCOMP 0x0002 /* Slave Transfer Complete */
163#define SERR 0x0004 /* Slave Transfer Error */
164#define SOVF 0x0008 /* Slave Overflow */
165#define MCOMP 0x0010 /* Master Transfer Complete */
166#define MERR 0x0020 /* Master Transfer Error */
167#define XMTSERV 0x0040 /* Transmit FIFO Service */
168#define RCVSERV 0x0080 /* Receive FIFO Service */
169
170/* TWI_FIFO_CTRL Masks */
171#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
172#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
173#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
174#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
175
176/* TWI_FIFO_STAT Masks */
177#define XMTSTAT 0x0003 /* Transmit FIFO Status */
178#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
179#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
180#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
181
182#define RCVSTAT 0x000C /* Receive FIFO Status */
183#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
184#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
185#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
186
187#endif 63#endif