diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-07-04 05:00:38 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-07-04 05:00:42 -0400 |
commit | d7e57676e3ed7ab9b2c7c4bcb7873e51eacbdb84 (patch) | |
tree | f7433f38cd407a0c35a8cbf2b7e3fd756087bce7 /arch/blackfin/include/asm/traps.h | |
parent | feaa0457ec8351cae855edc9a3052ac49322538e (diff) | |
parent | 746a99a5af60ee676afa2ba469ccd1373493c7e7 (diff) |
Merge branch 'linus' into x86/cleanups
Merge reason: We were on an older pre-rc1 base, move to almost-rc2.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/blackfin/include/asm/traps.h')
-rw-r--r-- | arch/blackfin/include/asm/traps.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h | |||
@@ -111,9 +111,7 @@ | |||
111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" | 111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" |
112 | #define EXC_0x2A(level) \ | 112 | #define EXC_0x2A(level) \ |
113 | "Instruction fetch misaligned address violation\n" \ | 113 | "Instruction fetch misaligned address violation\n" \ |
114 | level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ | 114 | level " - Attempted misaligned instruction cache fetch.\n" |
115 | level " exception, the return address provided in RETX is the destination address which is\n" \ | ||
116 | level " misaligned, rather than the address of the offending instruction.\n" | ||
117 | #define EXC_0x2B(level) \ | 115 | #define EXC_0x2B(level) \ |
118 | "CPLB protection violation\n" \ | 116 | "CPLB protection violation\n" \ |
119 | level " - Illegal instruction fetch access (memory protection violation).\n" | 117 | level " - Illegal instruction fetch access (memory protection violation).\n" |