diff options
author | Matt LaPlante <kernel1@cyberdogtech.com> | 2007-10-19 19:34:40 -0400 |
---|---|---|
committer | Adrian Bunk <bunk@kernel.org> | 2007-10-19 19:34:40 -0400 |
commit | 01dd2fbf0da4019c380b6ca22a074538fb31db5a (patch) | |
tree | 210291bd341c4450c8c51d8db890af0978f4035d /arch/blackfin/Kconfig | |
parent | 0f035b8e8491f4ff87f6eec3e3f754d36b39d7a2 (diff) |
typo fixes
Most of these fixes were already submitted for old kernel versions, and were
approved, but for some reason they never made it into the releases.
Because this is a consolidation of a couple old missed patches, it touches both
Kconfigs and documentation texts.
Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Acked-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'arch/blackfin/Kconfig')
-rw-r--r-- | arch/blackfin/Kconfig | 71 |
1 files changed, 36 insertions, 35 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 4c5ca9d5e40f..ad28dc76fc97 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -613,85 +613,86 @@ config I_ENTRY_L1 | |||
613 | bool "Locate interrupt entry code in L1 Memory" | 613 | bool "Locate interrupt entry code in L1 Memory" |
614 | default y | 614 | default y |
615 | help | 615 | help |
616 | If enabled interrupt entry code (STORE/RESTORE CONTEXT) is linked | 616 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
617 | into L1 instruction memory.(less latency) | 617 | into L1 instruction memory. (less latency) |
618 | 618 | ||
619 | config EXCPT_IRQ_SYSC_L1 | 619 | config EXCPT_IRQ_SYSC_L1 |
620 | bool "Locate entire ASM lowlevel excepetion / interrupt - Syscall and CPLB handler code in L1 Memory" | 620 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
621 | default y | 621 | default y |
622 | help | 622 | help |
623 | If enabled entire ASM lowlevel exception and interrupt entry code (STORE/RESTORE CONTEXT) is linked | 623 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
624 | into L1 instruction memory.(less latency) | 624 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
625 | (less latency) | ||
625 | 626 | ||
626 | config DO_IRQ_L1 | 627 | config DO_IRQ_L1 |
627 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | 628 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" |
628 | default y | 629 | default y |
629 | help | 630 | help |
630 | If enabled frequently called do_irq dispatcher function is linked | 631 | If enabled, the frequently called do_irq dispatcher function is linked |
631 | into L1 instruction memory.(less latency) | 632 | into L1 instruction memory. (less latency) |
632 | 633 | ||
633 | config CORE_TIMER_IRQ_L1 | 634 | config CORE_TIMER_IRQ_L1 |
634 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | 635 | bool "Locate frequently called timer_interrupt() function in L1 Memory" |
635 | default y | 636 | default y |
636 | help | 637 | help |
637 | If enabled frequently called timer_interrupt() function is linked | 638 | If enabled, the frequently called timer_interrupt() function is linked |
638 | into L1 instruction memory.(less latency) | 639 | into L1 instruction memory. (less latency) |
639 | 640 | ||
640 | config IDLE_L1 | 641 | config IDLE_L1 |
641 | bool "Locate frequently idle function in L1 Memory" | 642 | bool "Locate frequently idle function in L1 Memory" |
642 | default y | 643 | default y |
643 | help | 644 | help |
644 | If enabled frequently called idle function is linked | 645 | If enabled, the frequently called idle function is linked |
645 | into L1 instruction memory.(less latency) | 646 | into L1 instruction memory. (less latency) |
646 | 647 | ||
647 | config SCHEDULE_L1 | 648 | config SCHEDULE_L1 |
648 | bool "Locate kernel schedule function in L1 Memory" | 649 | bool "Locate kernel schedule function in L1 Memory" |
649 | default y | 650 | default y |
650 | help | 651 | help |
651 | If enabled frequently called kernel schedule is linked | 652 | If enabled, the frequently called kernel schedule is linked |
652 | into L1 instruction memory.(less latency) | 653 | into L1 instruction memory. (less latency) |
653 | 654 | ||
654 | config ARITHMETIC_OPS_L1 | 655 | config ARITHMETIC_OPS_L1 |
655 | bool "Locate kernel owned arithmetic functions in L1 Memory" | 656 | bool "Locate kernel owned arithmetic functions in L1 Memory" |
656 | default y | 657 | default y |
657 | help | 658 | help |
658 | If enabled arithmetic functions are linked | 659 | If enabled, arithmetic functions are linked |
659 | into L1 instruction memory.(less latency) | 660 | into L1 instruction memory. (less latency) |
660 | 661 | ||
661 | config ACCESS_OK_L1 | 662 | config ACCESS_OK_L1 |
662 | bool "Locate access_ok function in L1 Memory" | 663 | bool "Locate access_ok function in L1 Memory" |
663 | default y | 664 | default y |
664 | help | 665 | help |
665 | If enabled access_ok function is linked | 666 | If enabled, the access_ok function is linked |
666 | into L1 instruction memory.(less latency) | 667 | into L1 instruction memory. (less latency) |
667 | 668 | ||
668 | config MEMSET_L1 | 669 | config MEMSET_L1 |
669 | bool "Locate memset function in L1 Memory" | 670 | bool "Locate memset function in L1 Memory" |
670 | default y | 671 | default y |
671 | help | 672 | help |
672 | If enabled memset function is linked | 673 | If enabled, the memset function is linked |
673 | into L1 instruction memory.(less latency) | 674 | into L1 instruction memory. (less latency) |
674 | 675 | ||
675 | config MEMCPY_L1 | 676 | config MEMCPY_L1 |
676 | bool "Locate memcpy function in L1 Memory" | 677 | bool "Locate memcpy function in L1 Memory" |
677 | default y | 678 | default y |
678 | help | 679 | help |
679 | If enabled memcpy function is linked | 680 | If enabled, the memcpy function is linked |
680 | into L1 instruction memory.(less latency) | 681 | into L1 instruction memory. (less latency) |
681 | 682 | ||
682 | config SYS_BFIN_SPINLOCK_L1 | 683 | config SYS_BFIN_SPINLOCK_L1 |
683 | bool "Locate sys_bfin_spinlock function in L1 Memory" | 684 | bool "Locate sys_bfin_spinlock function in L1 Memory" |
684 | default y | 685 | default y |
685 | help | 686 | help |
686 | If enabled sys_bfin_spinlock function is linked | 687 | If enabled, sys_bfin_spinlock function is linked |
687 | into L1 instruction memory.(less latency) | 688 | into L1 instruction memory. (less latency) |
688 | 689 | ||
689 | config IP_CHECKSUM_L1 | 690 | config IP_CHECKSUM_L1 |
690 | bool "Locate IP Checksum function in L1 Memory" | 691 | bool "Locate IP Checksum function in L1 Memory" |
691 | default n | 692 | default n |
692 | help | 693 | help |
693 | If enabled IP Checksum function is linked | 694 | If enabled, the IP Checksum function is linked |
694 | into L1 instruction memory.(less latency) | 695 | into L1 instruction memory. (less latency) |
695 | 696 | ||
696 | config CACHELINE_ALIGNED_L1 | 697 | config CACHELINE_ALIGNED_L1 |
697 | bool "Locate cacheline_aligned data to L1 Data Memory" | 698 | bool "Locate cacheline_aligned data to L1 Data Memory" |
@@ -699,24 +700,24 @@ config CACHELINE_ALIGNED_L1 | |||
699 | default n if BF54x | 700 | default n if BF54x |
700 | depends on !BF531 | 701 | depends on !BF531 |
701 | help | 702 | help |
702 | If enabled cacheline_anligned data is linked | 703 | If enabled, cacheline_anligned data is linked |
703 | into L1 data memory.(less latency) | 704 | into L1 data memory. (less latency) |
704 | 705 | ||
705 | config SYSCALL_TAB_L1 | 706 | config SYSCALL_TAB_L1 |
706 | bool "Locate Syscall Table L1 Data Memory" | 707 | bool "Locate Syscall Table L1 Data Memory" |
707 | default n | 708 | default n |
708 | depends on !BF531 | 709 | depends on !BF531 |
709 | help | 710 | help |
710 | If enabled the Syscall LUT is linked | 711 | If enabled, the Syscall LUT is linked |
711 | into L1 data memory.(less latency) | 712 | into L1 data memory. (less latency) |
712 | 713 | ||
713 | config CPLB_SWITCH_TAB_L1 | 714 | config CPLB_SWITCH_TAB_L1 |
714 | bool "Locate CPLB Switch Tables L1 Data Memory" | 715 | bool "Locate CPLB Switch Tables L1 Data Memory" |
715 | default n | 716 | default n |
716 | depends on !BF531 | 717 | depends on !BF531 |
717 | help | 718 | help |
718 | If enabled the CPLB Switch Tables are linked | 719 | If enabled, the CPLB Switch Tables are linked |
719 | into L1 data memory.(less latency) | 720 | into L1 data memory. (less latency) |
720 | 721 | ||
721 | endmenu | 722 | endmenu |
722 | 723 | ||
@@ -1029,13 +1030,13 @@ config DEBUG_HWERR | |||
1029 | from. | 1030 | from. |
1030 | 1031 | ||
1031 | config DEBUG_ICACHE_CHECK | 1032 | config DEBUG_ICACHE_CHECK |
1032 | bool "Check Instruction cache coherancy" | 1033 | bool "Check Instruction cache coherency" |
1033 | depends on DEBUG_KERNEL | 1034 | depends on DEBUG_KERNEL |
1034 | depends on DEBUG_HWERR | 1035 | depends on DEBUG_HWERR |
1035 | help | 1036 | help |
1036 | Say Y here if you are getting wierd unexplained errors. This will | 1037 | Say Y here if you are getting weird unexplained errors. This will |
1037 | ensure that icache is what SDRAM says it should be, by doing a | 1038 | ensure that icache is what SDRAM says it should be by doing a |
1038 | byte wise comparision between SDRAM and instruction cache. This | 1039 | byte wise comparison between SDRAM and instruction cache. This |
1039 | also relocates the irq_panic() function to L1 memory, (which is | 1040 | also relocates the irq_panic() function to L1 memory, (which is |
1040 | un-cached). | 1041 | un-cached). |
1041 | 1042 | ||