Merge upstream kernel changes into 'C/H/S support' branch of libata.

70 files changed, 2300 insertions, 983 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf397a9f8ac2..ee8a9ad7bbd9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -67,10 +67,6 @@ config GENERIC_BUST_SPINLOCK
 config GENERIC_ISA_DMA
         bool
 
-config GENERIC_IOMAP
-        bool
-        default y
-
 config FIQ
         bool
 
@@ -202,6 +198,11 @@ config ARCH_H720X
         help
           This enables support for systems based on the Hynix HMS720x
 
+config ARCH_AAEC2000
+        bool "Agilent AAEC-2000 based"
+        help
+          This enables support for systems based on the Agilent AAEC-2000
+
 endchoice
 
 source "arch/arm/mach-clps711x/Kconfig"
@@ -234,6 +235,8 @@ source "arch/arm/mach-h720x/Kconfig"
 
 source "arch/arm/mach-versatile/Kconfig"
 
+source "arch/arm/mach-aaec2000/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
         bool
@@ -277,7 +280,7 @@ config ISA_DMA_API
         default y
 
 config PCI
-        bool "PCI support" if ARCH_INTEGRATOR_AP
+        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
@@ -497,7 +500,7 @@ source "drivers/cpufreq/Kconfig"
 
 config CPU_FREQ_SA1100
         bool
-        depends on CPU_FREQ && (SA1100_LART || SA1100_PLEB)
+        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
         default y
 
 config CPU_FREQ_SA1110
@@ -689,7 +692,9 @@ source "drivers/block/Kconfig"
 
 source "drivers/acorn/block/Kconfig"
 
-if ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE
+if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
+        || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
+        || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE
 source "drivers/ide/Kconfig"
 endif
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2277e3d179cc..8330495e2448 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -97,6 +97,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_VERSATILE)  := versatile
  machine-$(CONFIG_ARCH_IMX)        := imx
  machine-$(CONFIG_ARCH_H720X)      := h720x
+ machine-$(CONFIG_ARCH_AAEC2000)   := aaec2000
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index 665bd2c20743..d3fe2533907e 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -47,3 +47,10 @@ __XScale_start:
                orr     r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
 #endif
 
+#ifdef CONFIG_ARCH_IXP2000
+                mov     r1, #-1
+                mov     r0, #0xd6000000
+                str     r1, [r0, #0x14]
+                str     r1, [r0, #0x18]
+#endif
+
diff --git a/arch/arm/common/amba.c b/arch/arm/common/amba.c
index a0507f8c33fe..c6beb751f2a9 100644
--- a/arch/arm/common/amba.c
+++ b/arch/arm/common/amba.c
@@ -169,7 +169,7 @@ static void amba_device_release(struct device *dev)
 }
 
 #define amba_attr(name,fmt,arg...)                              \
-static ssize_t show_##name(struct device *_dev, char *buf)      \
+static ssize_t show_##name(struct device *_dev, struct device_attribute *attr, char *buf)       \
 {                                                               \
         struct amba_device *dev = to_amba_device(_dev);         \
         return sprintf(buf, fmt, arg);                          \
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 5797b1b100a1..9d63a01214eb 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -30,6 +30,8 @@
 #include <linux/dmapool.h>
 #include <linux/list.h>
 
+#include <asm/cacheflush.h>
+
 #undef DEBUG
 
 #undef STATS
@@ -302,12 +304,24 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 
                 DO_STATS ( device_info->bounce_count++ );
 
-                if ((dir == DMA_FROM_DEVICE) ||
-                    (dir == DMA_BIDIRECTIONAL)) {
+                if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
+                        unsigned long ptr;
+
                         dev_dbg(dev,
                                 "%s: copy back safe %p to unsafe %p size %d\n",
                                 __func__, buf->safe, buf->ptr, size);
                         memcpy(buf->ptr, buf->safe, size);
+
+                        /*
+                         * DMA buffers must have the same cache properties
+                         * as if they were really used for DMA - which means
+                         * data must be written back to RAM.  Note that
+                         * we don't use dmac_flush_range() here for the
+                         * bidirectional case because we know the cache
+                         * lines will be coherent with the data written.
+                         */
+                        ptr = (unsigned long)buf->ptr;
+                        dmac_clean_range(ptr, ptr + size);
                 }
                 free_safe_buffer(device_info, buf);
         }
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
index c2c557a224c2..c94864c5b1af 100644
--- a/arch/arm/common/sharpsl_param.c
+++ b/arch/arm/common/sharpsl_param.c
@@ -22,7 +22,7 @@
  * them early in the boot process, then pass them to the appropriate drivers.
  * Not all devices use all paramaters but the format is common to all.
  */
-#ifdef ARCH_SA1100
+#ifdef CONFIG_ARCH_SA1100
 #define PARAM_BASE      0xe8ffc000
 #else
 #define PARAM_BASE      0xa0000a00
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 2b4059d2f8e4..5d92af975d87 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sat Mar 26 21:32:26 2005
+# Linux kernel version: 2.6.12-rc6-git3
+# Thu Jun  9 19:00:50 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -34,6 +35,8 @@ CONFIG_EMBEDDED=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -109,7 +112,6 @@ CONFIG_CPU_ABRT_EV4=y
 CONFIG_CPU_CACHE_V4WB=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WB=y
-CONFIG_CPU_MINICACHE=y
 
 #
 # Processor Features
@@ -122,6 +124,7 @@ CONFIG_FORCE_MAX_ZONEORDER=9
 # Bus support
 #
 CONFIG_ISA=y
+CONFIG_ISA_DMA_API=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -131,6 +134,7 @@ CONFIG_ISA=y
 #
 # Kernel Features
 #
+# CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
 CONFIG_DISCONTIGMEM=y
 # CONFIG_LEDS is not set
@@ -152,12 +156,14 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_SA1100=y
 
 #
 # Floating point emulation
@@ -294,7 +300,6 @@ CONFIG_PARPORT_NOT_PC=y
 #
 # Block devices
 #
-# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_XD is not set
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -428,7 +433,6 @@ CONFIG_NET=y
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
@@ -526,6 +530,7 @@ CONFIG_IRDA_ULTRA=y
 # CONFIG_SMC_IRCC_FIR is not set
 # CONFIG_ALI_FIR is not set
 CONFIG_SA1100_FIR=y
+# CONFIG_VIA_FIR is not set
 CONFIG_BT=m
 CONFIG_BT_L2CAP=m
 # CONFIG_BT_SCO is not set
@@ -618,7 +623,6 @@ CONFIG_NET_WIRELESS=y
 #
 # CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
@@ -687,7 +691,6 @@ CONFIG_RTC=m
 #
 # TPM devices
 #
-# CONFIG_TCG_TPM is not set
 
 #
 # I2C support
@@ -736,6 +739,7 @@ CONFIG_I2C_ELEKTOR=m
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
@@ -747,6 +751,7 @@ CONFIG_I2C_ELEKTOR=m
 #
 # Other I2C Chip support
 #
+# CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCF8591 is not set
@@ -871,7 +876,6 @@ CONFIG_USB_PRINTER=m
 #
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
-# CONFIG_USB_STORAGE_RW_DETECT is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
@@ -954,9 +958,11 @@ CONFIG_USB_USS720=m
 #
 CONFIG_USB_SERIAL=m
 CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRPRIME is not set
 CONFIG_USB_SERIAL_BELKIN=m
 CONFIG_USB_SERIAL_WHITEHEAT=m
 CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+# CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 CONFIG_USB_SERIAL_EMPEG=m
 CONFIG_USB_SERIAL_FTDI_SIO=m
@@ -985,6 +991,7 @@ CONFIG_USB_SERIAL_KEYSPAN=m
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 CONFIG_USB_SERIAL_MCT_U232=m
 CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
 # CONFIG_USB_SERIAL_TI is not set
 CONFIG_USB_SERIAL_CYBERJACK=m
diff --git a/arch/arm/configs/enp2611_defconfig b/arch/arm/configs/enp2611_defconfig
index e8f9fccffe84..06fae4b62774 100644
--- a/arch/arm/configs/enp2611_defconfig
+++ b/arch/arm/configs/enp2611_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
 #
 # Loadable module support
 #
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 
 #
 # System Type
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index b4e297dd54b2..b9de07de80fe 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Mon Mar 28 00:02:26 2005
+# Linux kernel version: 2.6.12-rc4
+# Thu Jun  9 01:59:03 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -33,6 +34,8 @@ CONFIG_KOBJECT_UEVENT=y
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -120,6 +123,7 @@ CONFIG_CPU_MINICACHE=y
 # Bus support
 #
 CONFIG_ISA=y
+CONFIG_ISA_DMA_API=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -138,6 +142,7 @@ CONFIG_PCMCIA_SA1100=y
 #
 # Kernel Features
 #
+# CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
 CONFIG_DISCONTIGMEM=y
 # CONFIG_LEDS is not set
@@ -159,12 +164,13 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_SA1100=y
 
 #
 # Floating point emulation
@@ -298,7 +304,6 @@ CONFIG_MTD_SA1100=y
 #
 # Block devices
 #
-# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_XD is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=m
@@ -379,7 +384,6 @@ CONFIG_NET=y
 # Networking options
 #
 # CONFIG_PACKET is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
@@ -476,6 +480,7 @@ CONFIG_IRCOMM=m
 # CONFIG_SMC_IRCC_FIR is not set
 # CONFIG_ALI_FIR is not set
 CONFIG_SA1100_FIR=m
+# CONFIG_VIA_FIR is not set
 # CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
@@ -647,7 +652,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # TPM devices
 #
-# CONFIG_TCG_TPM is not set
 
 #
 # I2C support
@@ -676,9 +680,11 @@ CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_MACMODES is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
 CONFIG_FB_SA1100=y
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 
 #
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index 6987c8c5ddb4..fb41a36a5a68 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Mon Mar 28 00:22:34 2005
+# Linux kernel version: 2.6.12-rc6-git3
+# Thu Jun  9 20:58:58 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -34,6 +35,8 @@ CONFIG_KOBJECT_UEVENT=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -109,7 +112,6 @@ CONFIG_CPU_ABRT_EV4=y
 CONFIG_CPU_CACHE_V4WB=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WB=y
-CONFIG_CPU_MINICACHE=y
 
 #
 # Processor Features
@@ -119,6 +121,7 @@ CONFIG_CPU_MINICACHE=y
 # Bus support
 #
 CONFIG_ISA=y
+CONFIG_ISA_DMA_API=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -128,6 +131,7 @@ CONFIG_ISA=y
 #
 # Kernel Features
 #
+# CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
 CONFIG_DISCONTIGMEM=y
 CONFIG_LEDS=y
@@ -151,12 +155,14 @@ CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_SA1100=y
 
 #
 # Floating point emulation
@@ -280,7 +286,6 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # Block devices
 #
-# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_XD is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
@@ -338,7 +343,6 @@ CONFIG_NET=y
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
@@ -484,7 +488,6 @@ CONFIG_SERIO=y
 CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
@@ -533,7 +536,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # TPM devices
 #
-# CONFIG_TCG_TPM is not set
 
 #
 # I2C support
diff --git a/arch/arm/configs/ixdp2400_defconfig b/arch/arm/configs/ixdp2400_defconfig
index 4fd663ecbe39..810a450a55d2 100644
--- a/arch/arm/configs/ixdp2400_defconfig
+++ b/arch/arm/configs/ixdp2400_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
 #
 # Loadable module support
 #
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 
 #
 # System Type
diff --git a/arch/arm/configs/ixdp2401_defconfig b/arch/arm/configs/ixdp2401_defconfig
index 6f51c98084a3..72e1b940e975 100644
--- a/arch/arm/configs/ixdp2401_defconfig
+++ b/arch/arm/configs/ixdp2401_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
 #
 # Loadable module support
 #
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 
 #
 # System Type
diff --git a/arch/arm/configs/ixdp2800_defconfig b/arch/arm/configs/ixdp2800_defconfig
index 7be3521f91fc..1592e45f0278 100644
--- a/arch/arm/configs/ixdp2800_defconfig
+++ b/arch/arm/configs/ixdp2800_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
 #
 # Loadable module support
 #
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 
 #
 # System Type
diff --git a/arch/arm/configs/ixdp2801_defconfig b/arch/arm/configs/ixdp2801_defconfig
index cd84a20f30f1..f1afe3d09ec6 100644
--- a/arch/arm/configs/ixdp2801_defconfig
+++ b/arch/arm/configs/ixdp2801_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
 #
 # Loadable module support
 #
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 
 #
 # System Type
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 4a2af55e134b..3e1b0327e4d7 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -6,7 +6,7 @@ AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) -DDATAADDR=$(DATAADDR)
 
 # Object file lists.
 
-obj-y           := arch.o compat.o dma.o entry-armv.o entry-common.o irq.o   \
+obj-y           := compat.o dma.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o semaphore.o setup.o signal.o sys_arm.o \
                    time.o traps.o
 
diff --git a/arch/arm/kernel/arch.c b/arch/arm/kernel/arch.c
deleted file mode 100644
index 4e02fbeb10a6..000000000000
--- a/arch/arm/kernel/arch.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/arch/arm/kernel/arch.c
- *
- *  Architecture specific fixups.
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/types.h>
-
-#include <asm/elf.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-
-unsigned int vram_size;
-
-#ifdef CONFIG_ARCH_ACORN
-
-unsigned int memc_ctrl_reg;
-unsigned int number_mfm_drives;
-
-static int __init parse_tag_acorn(const struct tag *tag)
-{
-        memc_ctrl_reg = tag->u.acorn.memc_control_reg;
-        number_mfm_drives = tag->u.acorn.adfsdrives;
-
-        switch (tag->u.acorn.vram_pages) {
-        case 512:
-                vram_size += PAGE_SIZE * 256;
-        case 256:
-                vram_size += PAGE_SIZE * 256;
-        default:
-                break;
-        }
-#if 0
-        if (vram_size) {
-                desc->video_start = 0x02000000;
-                desc->video_end   = 0x02000000 + vram_size;
-        }
-#endif
-        return 0;
-}
-
-__tagtable(ATAG_ACORN, parse_tag_acorn);
-
-#endif
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 3dc15b131f53..6540db691338 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -866,19 +866,19 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot)
         return ec;
 }
 
-static ssize_t ecard_show_irq(struct device *dev, char *buf)
+static ssize_t ecard_show_irq(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         return sprintf(buf, "%u\n", ec->irq);
 }
 
-static ssize_t ecard_show_dma(struct device *dev, char *buf)
+static ssize_t ecard_show_dma(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         return sprintf(buf, "%u\n", ec->dma);
 }
 
-static ssize_t ecard_show_resources(struct device *dev, char *buf)
+static ssize_t ecard_show_resources(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         char *str = buf;
@@ -893,19 +893,19 @@ static ssize_t ecard_show_resources(struct device *dev, char *buf)
         return str - buf;
 }
 
-static ssize_t ecard_show_vendor(struct device *dev, char *buf)
+static ssize_t ecard_show_vendor(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         return sprintf(buf, "%u\n", ec->cid.manufacturer);
 }
 
-static ssize_t ecard_show_device(struct device *dev, char *buf)
+static ssize_t ecard_show_device(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         return sprintf(buf, "%u\n", ec->cid.product);
 }
 
-static ssize_t ecard_show_type(struct device *dev, char *buf)
+static ssize_t ecard_show_type(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct expansion_card *ec = ECARD_DEV(dev);
         return sprintf(buf, "%s\n", ec->type == ECARD_EASI ? "EASI" : "IOC");
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 4eb36155dc93..39a6c1b0b9a3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -24,48 +24,91 @@
 #include "entry-header.S"
 
 /*
+ * Interrupt handling.  Preserves r7, r8, r9
+ */
+        .macro  irq_handler
+1:      get_irqnr_and_base r0, r6, r5, lr
+        movne   r1, sp
+        @
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        @
+        adrne   lr, 1b
+        bne     asm_do_IRQ
+
+#ifdef CONFIG_SMP
+        /*
+         * XXX
+         *
+         * this macro assumes that irqstat (r6) and base (r5) are
+         * preserved from get_irqnr_and_base above
+         */
+        test_for_ipi r0, r6, r5, lr
+        movne   r0, sp
+        adrne   lr, 1b
+        bne     do_IPI
+#endif
+
+        .endm
+
+/*
  * Invalid mode handlers
  */
-        .macro  inv_entry, sym, reason
-        sub     sp, sp, #S_FRAME_SIZE           @ Allocate frame size in one go
-        stmia   sp, {r0 - lr}                   @ Save XXX r0 - lr
-        ldr     r4, .LC\sym
+        .macro  inv_entry, reason
+        sub     sp, sp, #S_FRAME_SIZE
+        stmib   sp, {r1 - lr}
         mov     r1, #\reason
         .endm
 
 __pabt_invalid:
-        inv_entry abt, BAD_PREFETCH
-        b       1f
+        inv_entry BAD_PREFETCH
+        b       common_invalid
 
 __dabt_invalid:
-        inv_entry abt, BAD_DATA
-        b       1f
+        inv_entry BAD_DATA
+        b       common_invalid
 
 __irq_invalid:
-        inv_entry irq, BAD_IRQ
-        b       1f
+        inv_entry BAD_IRQ
+        b       common_invalid
 
 __und_invalid:
-        inv_entry und, BAD_UNDEFINSTR
+        inv_entry BAD_UNDEFINSTR
+
+        @
+        @ XXX fall through to common_invalid
+        @
+
+@
+@ common_invalid - generic code for failed exception (re-entrant version of handlers)
+@
+common_invalid:
+        zero_fp
+
+        ldmia   r0, {r4 - r6}
+        add     r0, sp, #S_PC           @ here for interlock avoidance
+        mov     r7, #-1                 @  ""   ""    ""        ""
+        str     r4, [sp]                @ save preserved r0
+        stmia   r0, {r5 - r7}           @ lr_<exception>,
+                                        @ cpsr_<exception>, "old_r0"
 
-1:      zero_fp
-        ldmia   r4, {r5 - r7}                   @ Get XXX pc, cpsr, old_r0
-        add     r4, sp, #S_PC
-        stmia   r4, {r5 - r7}                   @ Save XXX pc, cpsr, old_r0
         mov     r0, sp
-        and     r2, r6, #31                     @ int mode
+        and     r2, r6, #0x1f
         b       bad_mode
 
 /*
  * SVC mode handlers
  */
-        .macro  svc_entry, sym
+        .macro  svc_entry
         sub     sp, sp, #S_FRAME_SIZE
-        stmia   sp, {r0 - r12}                  @ save r0 - r12
-        ldr     r2, .LC\sym
-        add     r0, sp, #S_FRAME_SIZE
-        ldmia   r2, {r2 - r4}                   @ get pc, cpsr
-        add     r5, sp, #S_SP
+        stmib   sp, {r1 - r12}
+
+        ldmia   r0, {r1 - r3}
+        add     r5, sp, #S_SP           @ here for interlock avoidance
+        mov     r4, #-1                 @  ""  ""      ""       ""
+        add     r0, sp, #S_FRAME_SIZE   @  ""  ""      ""       ""
+        str     r1, [sp]                @ save the "real" r0 copied
+                                        @ from the exception stack
+
         mov     r1, lr
 
         @
@@ -82,7 +125,7 @@ __und_invalid:
 
         .align  5
 __dabt_svc:
-        svc_entry abt
+        svc_entry
 
         @
         @ get ready to re-enable interrupts if appropriate
@@ -129,28 +172,24 @@ __dabt_svc:
 
         .align  5
 __irq_svc:
-        svc_entry irq
+        svc_entry
+
 #ifdef CONFIG_PREEMPT
-        get_thread_info r8
-        ldr     r9, [r8, #TI_PREEMPT]           @ get preempt count
-        add     r7, r9, #1                      @ increment it
-        str     r7, [r8, #TI_PREEMPT]
+        get_thread_info tsk
+        ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
+        add     r7, r8, #1                      @ increment it
+        str     r7, [tsk, #TI_PREEMPT]
 #endif
-1:      get_irqnr_and_base r0, r6, r5, lr
-        movne   r1, sp
-        @
-        @ routine called with r0 = irq number, r1 = struct pt_regs *
-        @
-        adrne   lr, 1b
-        bne     asm_do_IRQ
+
+        irq_handler
 #ifdef CONFIG_PREEMPT
-        ldr     r0, [r8, #TI_FLAGS]             @ get flags
+        ldr     r0, [tsk, #TI_FLAGS]            @ get flags
         tst     r0, #_TIF_NEED_RESCHED
         blne    svc_preempt
 preempt_return:
-        ldr     r0, [r8, #TI_PREEMPT]           @ read preempt value
+        ldr     r0, [tsk, #TI_PREEMPT]          @ read preempt value
+        str     r8, [tsk, #TI_PREEMPT]          @ restore preempt count
         teq     r0, r7
-        str     r9, [r8, #TI_PREEMPT]           @ restore preempt count
         strne   r0, [r0, -r0]                   @ bug()
 #endif
         ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
@@ -161,7 +200,7 @@ preempt_return:
 
 #ifdef CONFIG_PREEMPT
 svc_preempt:
-        teq     r9, #0                          @ was preempt count = 0
+        teq     r8, #0                          @ was preempt count = 0
         ldreq   r6, .LCirq_stat
         movne   pc, lr                          @ no
         ldr     r0, [r6, #4]                    @ local_irq_count
@@ -169,9 +208,9 @@ svc_preempt:
         adds    r0, r0, r1
         movne   pc, lr
         mov     r7, #0                          @ preempt_schedule_irq
-        str     r7, [r8, #TI_PREEMPT]           @ expects preempt_count == 0
+        str     r7, [tsk, #TI_PREEMPT]          @ expects preempt_count == 0
 1:      bl      preempt_schedule_irq            @ irq en/disable is done inside
-        ldr     r0, [r8, #TI_FLAGS]             @ get new tasks TI_FLAGS
+        ldr     r0, [tsk, #TI_FLAGS]            @ get new tasks TI_FLAGS
         tst     r0, #_TIF_NEED_RESCHED
         beq     preempt_return                  @ go again
         b       1b
@@ -179,7 +218,7 @@ svc_preempt:
 
         .align  5
 __und_svc:
-        svc_entry und
+        svc_entry
 
         @
         @ call emulation code, which returns using r9 if it has emulated
@@ -209,7 +248,7 @@ __und_svc:
 
         .align  5
 __pabt_svc:
-        svc_entry abt
+        svc_entry
 
         @
         @ re-enable interrupts if appropriate
@@ -242,12 +281,8 @@ __pabt_svc:
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
 
         .align  5
-.LCirq:
-        .word   __temp_irq
-.LCund:
-        .word   __temp_und
-.LCabt:
-        .word   __temp_abt
+.LCcralign:
+        .word   cr_alignment
 #ifdef MULTI_ABORT
 .LCprocfns:
         .word   processor
@@ -262,14 +297,18 @@ __pabt_svc:
 /*
  * User mode handlers
  */
-        .macro  usr_entry, sym
-        sub     sp, sp, #S_FRAME_SIZE           @ Allocate frame size in one go
-        stmia   sp, {r0 - r12}                  @ save r0 - r12
-        ldr     r7, .LC\sym
-        add     r5, sp, #S_PC
-        ldmia   r7, {r2 - r4}                   @ Get USR pc, cpsr
-
-#if __LINUX_ARM_ARCH__ < 6
+        .macro  usr_entry
+        sub     sp, sp, #S_FRAME_SIZE
+        stmib   sp, {r1 - r12}
+
+        ldmia   r0, {r1 - r3}
+        add     r0, sp, #S_PC           @ here for interlock avoidance
+        mov     r4, #-1                 @  ""  ""     ""        ""
+
+        str     r1, [sp]                @ save the "real" r0 copied
+                                        @ from the exception stack
+
+#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
         @ make sure our user space atomic helper is aborted
         cmp     r2, #VIRT_OFFSET
         bichs   r3, r3, #PSR_Z_BIT
@@ -284,13 +323,13 @@ __pabt_svc:
         @
         @ Also, separately save sp_usr and lr_usr
         @
-        stmia   r5, {r2 - r4}
-        stmdb   r5, {sp, lr}^
+        stmia   r0, {r2 - r4}
+        stmdb   r0, {sp, lr}^
 
         @
         @ Enable the alignment trap while in kernel mode
         @
-        alignment_trap r7, r0, __temp_\sym
+        alignment_trap r0
 
         @
         @ Clear FP to mark the first stack frame
@@ -300,7 +339,7 @@ __pabt_svc:
 
         .align  5
 __dabt_usr:
-        usr_entry abt
+        usr_entry
 
         @
         @ Call the processor-specific abort handler:
@@ -329,30 +368,23 @@ __dabt_usr:
 
         .align  5
 __irq_usr:
-        usr_entry irq
+        usr_entry
 
+        get_thread_info tsk
 #ifdef CONFIG_PREEMPT
-        get_thread_info r8
-        ldr     r9, [r8, #TI_PREEMPT]           @ get preempt count
-        add     r7, r9, #1                      @ increment it
-        str     r7, [r8, #TI_PREEMPT]
+        ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
+        add     r7, r8, #1                      @ increment it
+        str     r7, [tsk, #TI_PREEMPT]
 #endif
-1:      get_irqnr_and_base r0, r6, r5, lr
-        movne   r1, sp
-        adrne   lr, 1b
-        @
-        @ routine called with r0 = irq number, r1 = struct pt_regs *
-        @
-        bne     asm_do_IRQ
+
+        irq_handler
 #ifdef CONFIG_PREEMPT
-        ldr     r0, [r8, #TI_PREEMPT]
+        ldr     r0, [tsk, #TI_PREEMPT]
+        str     r8, [tsk, #TI_PREEMPT]
         teq     r0, r7
-        str     r9, [r8, #TI_PREEMPT]
         strne   r0, [r0, -r0]
-        mov     tsk, r8
-#else
-        get_thread_info tsk
 #endif
+
         mov     why, #0
         b       ret_to_user
 
@@ -360,7 +392,7 @@ __irq_usr:
 
         .align  5
 __und_usr:
-        usr_entry und
+        usr_entry
 
         tst     r3, #PSR_T_BIT                  @ Thumb mode?
         bne     fpundefinstr                    @ ignore FP
@@ -476,7 +508,7 @@ fpundefinstr:
 
         .align  5
 __pabt_usr:
-        usr_entry abt
+        usr_entry
 
         enable_irq                              @ Enable interrupts
         mov     r0, r2                          @ address (pc)
@@ -616,11 +648,17 @@ __kuser_helper_start:
 
 __kuser_cmpxchg:                                @ 0xffff0fc0
 
-#if __LINUX_ARM_ARCH__ < 6
+#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
 
-#ifdef CONFIG_SMP  /* sanity check */
-#error "CONFIG_SMP on a machine supporting pre-ARMv6 processors?"
-#endif
+        /*
+         * Poor you.  No fast solution possible...
+         * The kernel itself must perform the operation.
+         * A special ghost syscall is used for that (see traps.c).
+         */
+        swi     #0x9ffff0
+        mov     pc, lr
+
+#elif __LINUX_ARM_ARCH__ < 6
 
         /*
          * Theory of operation:
@@ -735,29 +773,41 @@ __kuser_helper_end:
  *
  * Common stub entry macro:
  *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
+ *
+ * SP points to a minimal amount of processor-private memory, the address
+ * of which is copied into r0 for the mode specific abort handler.
  */
-        .macro  vector_stub, name, sym, correction=0
+        .macro  vector_stub, name, correction=0
         .align  5
 
 vector_\name:
-        ldr     r13, .LCs\sym
         .if \correction
         sub     lr, lr, #\correction
         .endif
-        str     lr, [r13]                       @ save lr_IRQ
+
+        @
+        @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
+        @ (parent CPSR)
+        @
+        stmia   sp, {r0, lr}            @ save r0, lr
         mrs     lr, spsr
-        str     lr, [r13, #4]                   @ save spsr_IRQ
+        str     lr, [sp, #8]            @ save spsr
+
         @
-        @ now branch to the relevant MODE handling routine
+        @ Prepare for SVC32 mode.  IRQs remain disabled.
         @
-        mrs     r13, cpsr
-        bic     r13, r13, #MODE_MASK
-        orr     r13, r13, #SVC_MODE
-        msr     spsr_cxsf, r13                  @ switch to SVC_32 mode
+        mrs     r0, cpsr
+        bic     r0, r0, #MODE_MASK
+        orr     r0, r0, #SVC_MODE
+        msr     spsr_cxsf, r0
 
-        and     lr, lr, #15
+        @
+        @ the branch table must immediately follow this code
+        @
+        mov     r0, sp
+        and     lr, lr, #0x0f
         ldr     lr, [pc, lr, lsl #2]
-        movs    pc, lr                          @ Changes mode and branches
+        movs    pc, lr                  @ branch to handler in SVC mode
         .endm
 
         .globl  __stubs_start
@@ -765,7 +815,7 @@ __stubs_start:
 /*
  * Interrupt dispatcher
  */
-        vector_stub     irq, irq, 4
+        vector_stub     irq, 4
 
         .long   __irq_usr                       @  0  (USR_26 / USR_32)
         .long   __irq_invalid                   @  1  (FIQ_26 / FIQ_32)
@@ -788,7 +838,7 @@ __stubs_start:
  * Data abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
-        vector_stub     dabt, abt, 8
+        vector_stub     dabt, 8
 
         .long   __dabt_usr                      @  0  (USR_26 / USR_32)
         .long   __dabt_invalid                  @  1  (FIQ_26 / FIQ_32)
@@ -811,7 +861,7 @@ __stubs_start:
  * Prefetch abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
-        vector_stub     pabt, abt, 4
+        vector_stub     pabt, 4
 
         .long   __pabt_usr                      @  0 (USR_26 / USR_32)
         .long   __pabt_invalid                  @  1 (FIQ_26 / FIQ_32)
@@ -834,7 +884,7 @@ __stubs_start:
  * Undef instr entry dispatcher
  * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
  */
-        vector_stub     und, und
+        vector_stub     und
 
         .long   __und_usr                       @  0 (USR_26 / USR_32)
         .long   __und_invalid                   @  1 (FIQ_26 / FIQ_32)
@@ -888,13 +938,6 @@ vector_addrexcptn:
 .LCvswi:
         .word   vector_swi
 
-.LCsirq:
-        .word   __temp_irq
-.LCsund:
-        .word   __temp_und
-.LCsabt:
-        .word   __temp_abt
-
         .globl  __stubs_end
 __stubs_end:
 
@@ -916,23 +959,6 @@ __vectors_end:
 
         .data
 
-/*
- * Do not reorder these, and do not insert extra data between...
- */
-
-__temp_irq:
-        .word   0                               @ saved lr_irq
-        .word   0                               @ saved spsr_irq
-        .word   -1                              @ old_r0
-__temp_und:
-        .word   0                               @ Saved lr_und
-        .word   0                               @ Saved spsr_und
-        .word   -1                              @ old_r0
-__temp_abt:
-        .word   0                               @ Saved lr_abt
-        .word   0                               @ Saved spsr_abt
-        .word   -1                              @ old_r0
-
         .globl  cr_alignment
         .globl  cr_no_alignment
 cr_alignment:
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index a3d40a0e2b04..afef21273963 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -59,11 +59,10 @@
         mov     \rd, \rd, lsl #13
         .endm
 
-        .macro  alignment_trap, rbase, rtemp, sym
+        .macro  alignment_trap, rtemp
 #ifdef CONFIG_ALIGNMENT_TRAP
-#define OFF_CR_ALIGNMENT(x)     cr_alignment - x
-
-        ldr     \rtemp, [\rbase, #OFF_CR_ALIGNMENT(\sym)]
+        ldr     \rtemp, .LCcralign
+        ldr     \rtemp, [\rtemp]
         mcr     p15, 0, \rtemp, c1, c0
 #endif
         .endm
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4733877296d4..bd4823c74645 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -2,6 +2,8 @@
  *  linux/arch/arm/kernel/head.S
  *
  *  Copyright (C) 1994-2002 Russell King
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -165,6 +167,48 @@ __mmap_switched:
         stmia   r6, {r0, r4}                    @ Save control register values
         b       start_kernel
 
+#if defined(CONFIG_SMP)
+        .type   secondary_startup, #function
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+        bl      __lookup_processor_type
+        movs    r10, r5                         @ invalid processor?
+        moveq   r0, #'p'                        @ yes, error 'p'
+        beq     __error
+
+        /*
+         * Use the page tables supplied from  __cpu_up.
+         */
+        adr     r4, __secondary_data
+        ldmia   r4, {r5, r6, r13}               @ address to jump to after
+        sub     r4, r4, r5                      @ mmu has been enabled
+        ldr     r4, [r6, r4]                    @ get secondary_data.pgdir
+        adr     lr, __enable_mmu                @ return address
+        add     pc, r10, #12                    @ initialise processor
+                                                @ (return control reg)
+
+        /*
+         * r6  = &secondary_data
+         */
+ENTRY(__secondary_switched)
+        ldr     sp, [r6, #4]                    @ get secondary_data.stack
+        mov     fp, #0
+        b       secondary_start_kernel
+
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   .
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* defined(CONFIG_SMP) */
+
 
 
 /*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c2a7da3ac0f1..9fed5fa194d9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -92,6 +92,14 @@ struct cpu_user_fns cpu_user;
 struct cpu_cache_fns cpu_cache;
 #endif
 
+struct stack {
+        u32 irq[3];
+        u32 abt[3];
+        u32 und[3];
+} ____cacheline_aligned;
+
+static struct stack stacks[NR_CPUS];
+
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
 
@@ -307,8 +315,6 @@ static void __init setup_processor(void)
                cpu_name, processor_id, (int)processor_id & 15,
                proc_arch[cpu_architecture()]);
 
-        dump_cpu_info(smp_processor_id());
-
         sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS);
         sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
         elf_hwcap = list->elf_hwcap;
@@ -316,6 +322,46 @@ static void __init setup_processor(void)
         cpu_proc_init();
 }
 
+/*
+ * cpu_init - initialise one CPU.
+ *
+ * cpu_init dumps the cache information, initialises SMP specific
+ * information, and sets up the per-CPU stacks.
+ */
+void cpu_init(void)
+{
+        unsigned int cpu = smp_processor_id();
+        struct stack *stk = &stacks[cpu];
+
+        if (cpu >= NR_CPUS) {
+                printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
+                BUG();
+        }
+
+        dump_cpu_info(cpu);
+
+        /*
+         * setup stacks for re-entrant exception handlers
+         */
+        __asm__ (
+        "msr    cpsr_c, %1\n\t"
+        "add    sp, %0, %2\n\t"
+        "msr    cpsr_c, %3\n\t"
+        "add    sp, %0, %4\n\t"
+        "msr    cpsr_c, %5\n\t"
+        "add    sp, %0, %6\n\t"
+        "msr    cpsr_c, %7"
+            :
+            : "r" (stk),
+              "I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+              "I" (offsetof(struct stack, irq[0])),
+              "I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+              "I" (offsetof(struct stack, abt[0])),
+              "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+              "I" (offsetof(struct stack, und[0])),
+              "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE));
+}
+
 static struct machine_desc * __init setup_machine(unsigned int nr)
 {
         struct machine_desc *list;
@@ -715,6 +761,8 @@ void __init setup_arch(char **cmdline_p)
         paging_init(&meminfo, mdesc);
         request_standard_resources(&meminfo, mdesc);
 
+        cpu_init();
+
         /*
          * Set up various architecture-specific pointers
          */
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ecc8c3332408..34892758f098 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -24,6 +24,9 @@
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
@@ -37,6 +40,13 @@ cpumask_t cpu_present_mask;
 cpumask_t cpu_online_map;
 
 /*
+ * as from 2.5, kernels no longer have an init_tasks structure
+ * so we need some other way of telling a new secondary core
+ * where to place its SVC stack
+ */
+struct secondary_data secondary_data;
+
+/*
  * structures for inter-processor calls
  * - A collection of single bit ipi messages.
  */
@@ -71,6 +81,8 @@ static DEFINE_SPINLOCK(smp_call_function_lock);
 int __init __cpu_up(unsigned int cpu)
 {
         struct task_struct *idle;
+        pgd_t *pgd;
+        pmd_t *pmd;
         int ret;
 
         /*
@@ -84,11 +96,57 @@ int __init __cpu_up(unsigned int cpu)
         }
 
         /*
+         * Allocate initial page tables to allow the new CPU to
+         * enable the MMU safely.  This essentially means a set
+         * of our "standard" page tables, with the addition of
+         * a 1:1 mapping for the physical address of the kernel.
+         */
+        pgd = pgd_alloc(&init_mm);
+        pmd = pmd_offset(pgd, PHYS_OFFSET);
+        *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
+                     PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
+
+        /*
+         * We need to tell the secondary core where to find
+         * its stack and the page tables.
+         */
+        secondary_data.stack = (void *)idle->thread_info + THREAD_SIZE - 8;
+        secondary_data.pgdir = virt_to_phys(pgd);
+        wmb();
+
+        /*
          * Now bring the CPU into our world.
          */
         ret = boot_secondary(cpu, idle);
+        if (ret == 0) {
+                unsigned long timeout;
+
+                /*
+                 * CPU was successfully started, wait for it
+                 * to come online or time out.
+                 */
+                timeout = jiffies + HZ;
+                while (time_before(jiffies, timeout)) {
+                        if (cpu_online(cpu))
+                                break;
+
+                        udelay(10);
+                        barrier();
+                }
+
+                if (!cpu_online(cpu))
+                        ret = -EIO;
+        }
+
+        secondary_data.stack = 0;
+        secondary_data.pgdir = 0;
+
+        *pmd_offset(pgd, PHYS_OFFSET) = __pmd(0);
+        pgd_free(pgd);
+
         if (ret) {
-                printk(KERN_CRIT "cpu_up: processor %d failed to boot\n", cpu);
+                printk(KERN_CRIT "CPU%u: processor failed to boot\n", cpu);
+
                 /*
                  * FIXME: We need to clean up the new idle thread. --rmk
                  */
@@ -98,6 +156,56 @@ int __init __cpu_up(unsigned int cpu)
 }
 
 /*
+ * This is the secondary CPU boot entry.  We're using this CPUs
+ * idle thread stack, but a set of temporary page tables.
+ */
+asmlinkage void __init secondary_start_kernel(void)
+{
+        struct mm_struct *mm = &init_mm;
+        unsigned int cpu = smp_processor_id();
+
+        printk("CPU%u: Booted secondary processor\n", cpu);
+
+        /*
+         * All kernel threads share the same mm context; grab a
+         * reference and switch to it.
+         */
+        atomic_inc(&mm->mm_users);
+        atomic_inc(&mm->mm_count);
+        current->active_mm = mm;
+        cpu_set(cpu, mm->cpu_vm_mask);
+        cpu_switch_mm(mm->pgd, mm);
+        enter_lazy_tlb(mm, current);
+
+        cpu_init();
+
+        /*
+         * Give the platform a chance to do its own initialisation.
+         */
+        platform_secondary_init(cpu);
+
+        /*
+         * Enable local interrupts.
+         */
+        local_irq_enable();
+        local_fiq_enable();
+
+        calibrate_delay();
+
+        smp_store_cpu_info(cpu);
+
+        /*
+         * OK, now it's safe to let the boot CPU continue
+         */
+        cpu_set(cpu, cpu_online_map);
+
+        /*
+         * OK, it's off to the idle thread for us
+         */
+        cpu_idle();
+}
+
+/*
  * Called by both boot and secondaries to move global data into
  * per-processor storage.
  */
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 14df16b983f4..45d2a032d890 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -464,6 +464,55 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 #endif
                 return 0;
 
+#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
+        /*
+         * Atomically store r1 in *r2 if *r2 is equal to r0 for user space.
+         * Return zero in r0 if *MEM was changed or non-zero if no exchange
+         * happened.  Also set the user C flag accordingly.
+         * If access permissions have to be fixed up then non-zero is
+         * returned and the operation has to be re-attempted.
+         *
+         * *NOTE*: This is a ghost syscall private to the kernel.  Only the
+         * __kuser_cmpxchg code in entry-armv.S should be aware of its
+         * existence.  Don't ever use this from user code.
+         */
+        case 0xfff0:
+        {
+                extern void do_DataAbort(unsigned long addr, unsigned int fsr,
+                                         struct pt_regs *regs);
+                unsigned long val;
+                unsigned long addr = regs->ARM_r2;
+                struct mm_struct *mm = current->mm;
+                pgd_t *pgd; pmd_t *pmd; pte_t *pte;
+
+                regs->ARM_cpsr &= ~PSR_C_BIT;
+                spin_lock(&mm->page_table_lock);
+                pgd = pgd_offset(mm, addr);
+                if (!pgd_present(*pgd))
+                        goto bad_access;
+                pmd = pmd_offset(pgd, addr);
+                if (!pmd_present(*pmd))
+                        goto bad_access;
+                pte = pte_offset_map(pmd, addr);
+                if (!pte_present(*pte) || !pte_write(*pte))
+                        goto bad_access;
+                val = *(unsigned long *)addr;
+                val -= regs->ARM_r0;
+                if (val == 0) {
+                        *(unsigned long *)addr = regs->ARM_r1;
+                        regs->ARM_cpsr |= PSR_C_BIT;
+                }
+                spin_unlock(&mm->page_table_lock);
+                return val;
+
+                bad_access:
+                spin_unlock(&mm->page_table_lock);
+                /* simulate a read access fault */
+                do_DataAbort(addr, 15 + (1 << 11), regs);
+                return -1;
+        }
+#endif
+
         default:
                 /* Calls 9f00xx..9f07ff are defined to return -ENOSYS
                    if not implemented, rather than raising SIGILL.  This
diff --git a/arch/arm/lib/ashldi3.c b/arch/arm/lib/ashldi3.c
index 130f5a839669..b62875cfd8f8 100644
--- a/arch/arm/lib/ashldi3.c
+++ b/arch/arm/lib/ashldi3.c
@@ -31,31 +31,26 @@ Boston, MA 02111-1307, USA.  */
 
 #include "gcclib.h"
 
-DItype
-__ashldi3 (DItype u, word_type b)
+s64 __ashldi3(s64 u, int b)
 {
-  DIunion w;
-  word_type bm;
-  DIunion uu;
-
-  if (b == 0)
-    return u;
-
-  uu.ll = u;
-
-  bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
-  if (bm <= 0)
-    {
-      w.s.low = 0;
-      w.s.high = (USItype)uu.s.low << -bm;
-    }
-  else
-    {
-      USItype carries = (USItype)uu.s.low >> bm;
-      w.s.low = (USItype)uu.s.low << b;
-      w.s.high = ((USItype)uu.s.high << b) | carries;
-    }
-
-  return w.ll;
+        DIunion w;
+        int bm;
+        DIunion uu;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+
+        bm = (sizeof(s32) * BITS_PER_UNIT) - b;
+        if (bm <= 0) {
+                w.s.low = 0;
+                w.s.high = (u32) uu.s.low << -bm;
+        } else {
+                u32 carries = (u32) uu.s.low >> bm;
+                w.s.low = (u32) uu.s.low << b;
+                w.s.high = ((u32) uu.s.high << b) | carries;
+        }
+
+        return w.ll;
 }
-
diff --git a/arch/arm/lib/ashrdi3.c b/arch/arm/lib/ashrdi3.c
index 71625d218f8d..9a8600a7543f 100644
--- a/arch/arm/lib/ashrdi3.c
+++ b/arch/arm/lib/ashrdi3.c
@@ -31,31 +31,27 @@ Boston, MA 02111-1307, USA.  */
 
 #include "gcclib.h"
 
-DItype
-__ashrdi3 (DItype u, word_type b)
+s64 __ashrdi3(s64 u, int b)
 {
-  DIunion w;
-  word_type bm;
-  DIunion uu;
-
-  if (b == 0)
-    return u;
-
-  uu.ll = u;
-
-  bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
-  if (bm <= 0)
-    {
-      /* w.s.high = 1..1 or 0..0 */
-      w.s.high = uu.s.high >> (sizeof (SItype) * BITS_PER_UNIT - 1);
-      w.s.low = uu.s.high >> -bm;
-    }
-  else
-    {
-      USItype carries = (USItype)uu.s.high << bm;
-      w.s.high = uu.s.high >> b;
-      w.s.low = ((USItype)uu.s.low >> b) | carries;
-    }
-
-  return w.ll;
+        DIunion w;
+        int bm;
+        DIunion uu;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+
+        bm = (sizeof(s32) * BITS_PER_UNIT) - b;
+        if (bm <= 0) {
+                /* w.s.high = 1..1 or 0..0 */
+                w.s.high = uu.s.high >> (sizeof(s32) * BITS_PER_UNIT - 1);
+                w.s.low = uu.s.high >> -bm;
+        } else {
+                u32 carries = (u32) uu.s.high << bm;
+                w.s.high = uu.s.high >> b;
+                w.s.low = ((u32) uu.s.low >> b) | carries;
+        }
+
+        return w.ll;
 }
diff --git a/arch/arm/lib/gcclib.h b/arch/arm/lib/gcclib.h
index 65314a3d9e27..8b6dcc656de7 100644
--- a/arch/arm/lib/gcclib.h
+++ b/arch/arm/lib/gcclib.h
@@ -1,25 +1,22 @@
 /* gcclib.h -- definitions for various functions 'borrowed' from gcc-2.95.3 */
 /* I Molton     29/07/01 */
 
-#define BITS_PER_UNIT  8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
+#include <linux/types.h>
 
-typedef unsigned int UQItype    __attribute__ ((mode (QI)));
-typedef          int SItype     __attribute__ ((mode (SI)));
-typedef unsigned int USItype    __attribute__ ((mode (SI)));
-typedef          int DItype     __attribute__ ((mode (DI)));
-typedef          int word_type  __attribute__ ((mode (__word__)));
-typedef unsigned int UDItype    __attribute__ ((mode (DI)));
+#define BITS_PER_UNIT   8
+#define SI_TYPE_SIZE    (sizeof(s32) * BITS_PER_UNIT)
 
 #ifdef __ARMEB__
-  struct DIstruct {SItype high, low;};
+struct DIstruct {
+        s32 high, low;
+};
 #else
-  struct DIstruct {SItype low, high;};
+struct DIstruct {
+        s32 low, high;
+};
 #endif
 
-typedef union
-{
-  struct DIstruct s;
-  DItype ll;
+typedef union {
+        struct DIstruct s;
+        s64 ll;
 } DIunion;
-
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index 6d1d7c27806e..5e240e452af6 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -87,9 +87,9 @@ ENTRY(__raw_writesw)
                 subs    r2, r2, #2
                 orr     ip, ip, r3, push_hbyte1
                 strh    ip, [r0]
-                bpl     2b
+                bpl     1b
 
-3:              tst     r2, #1
-2:              movne   ip, r3, lsr #8
+                tst     r2, #1
+3:              movne   ip, r3, lsr #8
                 strneh  ip, [r0]
                 mov     pc, lr
diff --git a/arch/arm/lib/longlong.h b/arch/arm/lib/longlong.h
index 179eea4edc35..90ae647e4d76 100644
--- a/arch/arm/lib/longlong.h
+++ b/arch/arm/lib/longlong.h
@@ -26,18 +26,18 @@
 
 #define __BITS4 (SI_TYPE_SIZE / 4)
 #define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define __ll_lowpart(t) ((u32) (t) % __ll_B)
+#define __ll_highpart(t) ((u32) (t) / __ll_B)
 
 /* Define auxiliary asm macros.
 
    1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
-   multiplies two USItype integers MULTIPLER and MULTIPLICAND,
-   and generates a two-part USItype product in HIGH_PROD and
+   multiplies two u32 integers MULTIPLER and MULTIPLICAND,
+   and generates a two-part u32 product in HIGH_PROD and
    LOW_PROD.
 
-   2) __umulsidi3(a,b) multiplies two USItype integers A and B,
-   and returns a UDItype product.  This is just a variant of umul_ppmm.
+   2) __umulsidi3(a,b) multiplies two u32 integers A and B,
+   and returns a u64 product.  This is just a variant of umul_ppmm.
 
    3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
    denominator) divides a two-word unsigned integer, composed by the
@@ -77,23 +77,23 @@
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds        %1, %4, %5                                      \n\
         adc     %0, %2, %3"                                             \
-           : "=r" ((USItype) (sh)),                                     \
-             "=&r" ((USItype) (sl))                                     \
-           : "%r" ((USItype) (ah)),                                     \
-             "rI" ((USItype) (bh)),                                     \
-             "%r" ((USItype) (al)),                                     \
-             "rI" ((USItype) (bl)))
+           : "=r" ((u32) (sh)),                                 \
+             "=&r" ((u32) (sl))                                 \
+           : "%r" ((u32) (ah)),                                 \
+             "rI" ((u32) (bh)),                                 \
+             "%r" ((u32) (al)),                                 \
+             "rI" ((u32) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs        %1, %4, %5                                      \n\
         sbc     %0, %2, %3"                                             \
-           : "=r" ((USItype) (sh)),                                     \
-             "=&r" ((USItype) (sl))                                     \
-           : "r" ((USItype) (ah)),                                      \
-             "rI" ((USItype) (bh)),                                     \
-             "r" ((USItype) (al)),                                      \
-             "rI" ((USItype) (bl)))
+           : "=r" ((u32) (sh)),                                 \
+             "=&r" ((u32) (sl))                                 \
+           : "r" ((u32) (ah)),                                  \
+             "rI" ((u32) (bh)),                                 \
+             "r" ((u32) (al)),                                  \
+             "rI" ((u32) (bl)))
 #define umul_ppmm(xh, xl, a, b) \
-{register USItype __t0, __t1, __t2;                                     \
+{register u32 __t0, __t1, __t2;                                 \
   __asm__ ("%@ Inlined umul_ppmm                                        \n\
         mov     %2, %5, lsr #16                                         \n\
         mov     %0, %6, lsr #16                                         \n\
@@ -107,14 +107,14 @@
         addcs   %0, %0, #65536                                          \n\
         adds    %1, %1, %3, lsl #16                                     \n\
         adc     %0, %0, %3, lsr #16"                                    \
-           : "=&r" ((USItype) (xh)),                                    \
-             "=r" ((USItype) (xl)),                                     \
+           : "=&r" ((u32) (xh)),                                        \
+             "=r" ((u32) (xl)),                                 \
              "=&r" (__t0), "=&r" (__t1), "=r" (__t2)                    \
-           : "r" ((USItype) (a)),                                       \
-             "r" ((USItype) (b)));}
+           : "r" ((u32) (a)),                                   \
+             "r" ((u32) (b)));}
 #define UMUL_TIME 20
 #define UDIV_TIME 100
-#endif /* __arm__ */
+#endif                          /* __arm__ */
 
 #define __umulsidi3(u, v) \
   ({DIunion __w;                                                        \
@@ -123,14 +123,14 @@
 
 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
   do {                                                                  \
-    USItype __d1, __d0, __q1, __q0;                                     \
-    USItype __r1, __r0, __m;                                            \
+    u32 __d1, __d0, __q1, __q0;                                 \
+    u32 __r1, __r0, __m;                                                \
     __d1 = __ll_highpart (d);                                           \
     __d0 = __ll_lowpart (d);                                            \
                                                                         \
     __r1 = (n1) % __d1;                                                 \
     __q1 = (n1) / __d1;                                                 \
-    __m = (USItype) __q1 * __d0;                                        \
+    __m = (u32) __q1 * __d0;                                    \
     __r1 = __r1 * __ll_B | __ll_highpart (n0);                          \
     if (__r1 < __m)                                                     \
       {                                                                 \
@@ -143,7 +143,7 @@
                                                                         \
     __r0 = __r1 % __d1;                                                 \
     __q0 = __r1 / __d1;                                                 \
-    __m = (USItype) __q0 * __d0;                                        \
+    __m = (u32) __q0 * __d0;                                    \
     __r0 = __r0 * __ll_B | __ll_lowpart (n0);                           \
     if (__r0 < __m)                                                     \
       {                                                                 \
@@ -154,7 +154,7 @@
       }                                                                 \
     __r0 -= __m;                                                        \
                                                                         \
-    (q) = (USItype) __q1 * __ll_B | __q0;                               \
+    (q) = (u32) __q1 * __ll_B | __q0;                           \
     (r) = __r0;                                                         \
   } while (0)
 
@@ -163,14 +163,14 @@
 
 #define count_leading_zeros(count, x) \
   do {                                                                  \
-    USItype __xr = (x);                                                 \
-    USItype __a;                                                        \
+    u32 __xr = (x);                                                     \
+    u32 __a;                                                    \
                                                                         \
     if (SI_TYPE_SIZE <= 32)                                             \
       {                                                                 \
-        __a = __xr < ((USItype)1<<2*__BITS4)                            \
-          ? (__xr < ((USItype)1<<__BITS4) ? 0 : __BITS4)                \
-          : (__xr < ((USItype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);  \
+        __a = __xr < ((u32)1<<2*__BITS4)                                \
+          ? (__xr < ((u32)1<<__BITS4) ? 0 : __BITS4)            \
+          : (__xr < ((u32)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);      \
       }                                                                 \
     else                                                                \
       {                                                                 \
diff --git a/arch/arm/lib/lshrdi3.c b/arch/arm/lib/lshrdi3.c
index b666f1bad451..3681f49d2b6e 100644
--- a/arch/arm/lib/lshrdi3.c
+++ b/arch/arm/lib/lshrdi3.c
@@ -31,31 +31,26 @@ Boston, MA 02111-1307, USA.  */
 
 #include "gcclib.h"
 
-DItype
-__lshrdi3 (DItype u, word_type b)
+s64 __lshrdi3(s64 u, int b)
 {
-  DIunion w;
-  word_type bm;
-  DIunion uu;
-
-  if (b == 0)
-    return u;
-
-  uu.ll = u;
-
-  bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
-  if (bm <= 0)
-    {
-      w.s.high = 0;
-      w.s.low = (USItype)uu.s.high >> -bm;
-    }
-  else
-    {
-      USItype carries = (USItype)uu.s.high << bm;
-      w.s.high = (USItype)uu.s.high >> b;
-      w.s.low = ((USItype)uu.s.low >> b) | carries;
-    }
-
-  return w.ll;
+        DIunion w;
+        int bm;
+        DIunion uu;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+
+        bm = (sizeof(s32) * BITS_PER_UNIT) - b;
+        if (bm <= 0) {
+                w.s.high = 0;
+                w.s.low = (u32) uu.s.high >> -bm;
+        } else {
+                u32 carries = (u32) uu.s.high << bm;
+                w.s.high = (u32) uu.s.high >> b;
+                w.s.low = ((u32) uu.s.low >> b) | carries;
+        }
+
+        return w.ll;
 }
-
diff --git a/arch/arm/lib/muldi3.c b/arch/arm/lib/muldi3.c
index 44d611b1cfdb..0a3b93313f18 100644
--- a/arch/arm/lib/muldi3.c
+++ b/arch/arm/lib/muldi3.c
@@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA.  */
 #include "gcclib.h"
 
 #define umul_ppmm(xh, xl, a, b) \
-{register USItype __t0, __t1, __t2;                                     \
+{register u32 __t0, __t1, __t2;                                     \
   __asm__ ("%@ Inlined umul_ppmm                                        \n\
         mov     %2, %5, lsr #16                                         \n\
         mov     %0, %6, lsr #16                                         \n\
@@ -46,32 +46,27 @@ Boston, MA 02111-1307, USA.  */
         addcs   %0, %0, #65536                                          \n\
         adds    %1, %1, %3, lsl #16                                     \n\
         adc     %0, %0, %3, lsr #16"                                    \
-           : "=&r" ((USItype) (xh)),                                    \
-             "=r" ((USItype) (xl)),                                     \
+           : "=&r" ((u32) (xh)),                                    \
+             "=r" ((u32) (xl)),                                     \
              "=&r" (__t0), "=&r" (__t1), "=r" (__t2)                    \
-           : "r" ((USItype) (a)),                                       \
-             "r" ((USItype) (b)));}
-
+           : "r" ((u32) (a)),                                       \
+             "r" ((u32) (b)));}
 
 #define __umulsidi3(u, v) \
   ({DIunion __w;                                                        \
     umul_ppmm (__w.s.high, __w.s.low, u, v);                            \
     __w.ll; })
 
-
-DItype
-__muldi3 (DItype u, DItype v)
+s64 __muldi3(s64 u, s64 v)
 {
-  DIunion w;
-  DIunion uu, vv;
+        DIunion w;
+        DIunion uu, vv;
 
-  uu.ll = u,
-  vv.ll = v;
+        uu.ll = u, vv.ll = v;
 
-  w.ll = __umulsidi3 (uu.s.low, vv.s.low);
-  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-               + (USItype) uu.s.high * (USItype) vv.s.low);
+        w.ll = __umulsidi3(uu.s.low, vv.s.low);
+        w.s.high += ((u32) uu.s.low * (u32) vv.s.high
+                     + (u32) uu.s.high * (u32) vv.s.low);
 
-  return w.ll;
+        return w.ll;
 }
-
diff --git a/arch/arm/lib/ucmpdi2.c b/arch/arm/lib/ucmpdi2.c
index 6c6ae63efa02..57f3f2df3850 100644
--- a/arch/arm/lib/ucmpdi2.c
+++ b/arch/arm/lib/ucmpdi2.c
@@ -31,21 +31,19 @@ Boston, MA 02111-1307, USA.  */
 
 #include "gcclib.h"
 
-word_type
-__ucmpdi2 (DItype a, DItype b)
+int __ucmpdi2(s64 a, s64 b)
 {
-  DIunion au, bu;
-
-  au.ll = a, bu.ll = b;
-
-  if ((USItype) au.s.high < (USItype) bu.s.high)
-    return 0;
-  else if ((USItype) au.s.high > (USItype) bu.s.high)
-    return 2;
-  if ((USItype) au.s.low < (USItype) bu.s.low)
-    return 0;
-  else if ((USItype) au.s.low > (USItype) bu.s.low)
-    return 2;
-  return 1;
+        DIunion au, bu;
+
+        au.ll = a, bu.ll = b;
+
+        if ((u32) au.s.high < (u32) bu.s.high)
+                return 0;
+        else if ((u32) au.s.high > (u32) bu.s.high)
+                return 2;
+        if ((u32) au.s.low < (u32) bu.s.low)
+                return 0;
+        else if ((u32) au.s.low > (u32) bu.s.low)
+                return 2;
+        return 1;
 }
-
diff --git a/arch/arm/lib/udivdi3.c b/arch/arm/lib/udivdi3.c
index d25195f673f4..e343be4c6642 100644
--- a/arch/arm/lib/udivdi3.c
+++ b/arch/arm/lib/udivdi3.c
@@ -32,211 +32,191 @@ Boston, MA 02111-1307, USA.  */
 #include "gcclib.h"
 #include "longlong.h"
 
-static const UQItype __clz_tab[] =
-{
-  0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
-  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
-  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+static const u8 __clz_tab[] = {
+        0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5,
+            5, 5, 5, 5, 5, 5, 5, 5,
+        6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+            6, 6, 6, 6, 6, 6, 6, 6,
+        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+            7, 7, 7, 7, 7, 7, 7, 7,
+        7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+            7, 7, 7, 7, 7, 7, 7, 7,
+        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+            8, 8, 8, 8, 8, 8, 8, 8,
+        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+            8, 8, 8, 8, 8, 8, 8, 8,
+        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+            8, 8, 8, 8, 8, 8, 8, 8,
+        8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+            8, 8, 8, 8, 8, 8, 8, 8,
 };
 
-UDItype
-__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
+u64 __udivmoddi4(u64 n, u64 d, u64 * rp)
 {
-  DIunion ww;
-  DIunion nn, dd;
-  DIunion rr;
-  USItype d0, d1, n0, n1, n2;
-  USItype q0, q1;
-  USItype b, bm;
-
-  nn.ll = n;
-  dd.ll = d;
-
-  d0 = dd.s.low;
-  d1 = dd.s.high;
-  n0 = nn.s.low;
-  n1 = nn.s.high;
-
-  if (d1 == 0)
-    {
-      if (d0 > n1)
-        {
-          /* 0q = nn / 0D */
-
-          count_leading_zeros (bm, d0);
-
-          if (bm != 0)
-            {
-              /* Normalize, i.e. make the most significant bit of the
-                 denominator set.  */
-
-              d0 = d0 << bm;
-              n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
-              n0 = n0 << bm;
-            }
-
-          udiv_qrnnd (q0, n0, n1, n0, d0);
-          q1 = 0;
-
-          /* Remainder in n0 >> bm.  */
-        }
-      else
-        {
-          /* qq = NN / 0d */
-
-          if (d0 == 0)
-            d0 = 1 / d0;        /* Divide intentionally by zero.  */
-
-          count_leading_zeros (bm, d0);
-
-          if (bm == 0)
-            {
-              /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
-                 conclude (the most significant bit of n1 is set) /\ (the
-                 leading quotient digit q1 = 1).
-
-                 This special case is necessary, not an optimization.
-                 (Shifts counts of SI_TYPE_SIZE are undefined.)  */
-
-              n1 -= d0;
-              q1 = 1;
-            }
-          else
-            {
-              /* Normalize.  */
-
-              b = SI_TYPE_SIZE - bm;
-
-              d0 = d0 << bm;
-              n2 = n1 >> b;
-              n1 = (n1 << bm) | (n0 >> b);
-              n0 = n0 << bm;
-
-              udiv_qrnnd (q1, n1, n2, n1, d0);
-            }
-
-          /* n1 != d0...  */
-
-          udiv_qrnnd (q0, n0, n1, n0, d0);
-
-          /* Remainder in n0 >> bm.  */
-        }
-
-      if (rp != 0)
-        {
-          rr.s.low = n0 >> bm;
-          rr.s.high = 0;
-          *rp = rr.ll;
-        }
-    }
-  else
-    {
-      if (d1 > n1)
-        {
-          /* 00 = nn / DD */
-
-          q0 = 0;
-          q1 = 0;
-
-          /* Remainder in n1n0.  */
-          if (rp != 0)
-            {
-              rr.s.low = n0;
-              rr.s.high = n1;
-              *rp = rr.ll;
-            }
-        }
-      else
-        {
-          /* 0q = NN / dd */
-
-          count_leading_zeros (bm, d1);
-          if (bm == 0)
-            {
-              /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
-                 conclude (the most significant bit of n1 is set) /\ (the
-                 quotient digit q0 = 0 or 1).
-
-                 This special case is necessary, not an optimization.  */
-
-              /* The condition on the next line takes advantage of that
-                 n1 >= d1 (true due to program flow).  */
-              if (n1 > d1 || n0 >= d0)
-                {
-                  q0 = 1;
-                  sub_ddmmss (n1, n0, n1, n0, d1, d0);
-                }
-              else
-                q0 = 0;
-
-              q1 = 0;
-
-              if (rp != 0)
-                {
-                  rr.s.low = n0;
-                  rr.s.high = n1;
-                  *rp = rr.ll;
-                }
-            }
-          else
-            {
-              USItype m1, m0;
-              /* Normalize.  */
-
-              b = SI_TYPE_SIZE - bm;
-
-              d1 = (d1 << bm) | (d0 >> b);
-              d0 = d0 << bm;
-              n2 = n1 >> b;
-              n1 = (n1 << bm) | (n0 >> b);
-              n0 = n0 << bm;
-
-              udiv_qrnnd (q0, n1, n2, n1, d1);
-              umul_ppmm (m1, m0, q0, d0);
-
-              if (m1 > n1 || (m1 == n1 && m0 > n0))
-                {
-                  q0--;
-                  sub_ddmmss (m1, m0, m1, m0, d1, d0);
-                }
-
-              q1 = 0;
-
-              /* Remainder in (n1n0 - m1m0) >> bm.  */
-              if (rp != 0)
-                {
-                  sub_ddmmss (n1, n0, n1, n0, m1, m0);
-                  rr.s.low = (n1 << b) | (n0 >> bm);
-                  rr.s.high = n1 >> bm;
-                  *rp = rr.ll;
-                }
-            }
-        }
-    }
-
-  ww.s.low = q0;
-  ww.s.high = q1;
-  return ww.ll;
+        DIunion ww;
+        DIunion nn, dd;
+        DIunion rr;
+        u32 d0, d1, n0, n1, n2;
+        u32 q0, q1;
+        u32 b, bm;
+
+        nn.ll = n;
+        dd.ll = d;
+
+        d0 = dd.s.low;
+        d1 = dd.s.high;
+        n0 = nn.s.low;
+        n1 = nn.s.high;
+
+        if (d1 == 0) {
+                if (d0 > n1) {
+                        /* 0q = nn / 0D */
+
+                        count_leading_zeros(bm, d0);
+
+                        if (bm != 0) {
+                                /* Normalize, i.e. make the most significant bit of the
+                                   denominator set.  */
+
+                                d0 = d0 << bm;
+                                n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
+                                n0 = n0 << bm;
+                        }
+
+                        udiv_qrnnd(q0, n0, n1, n0, d0);
+                        q1 = 0;
+
+                        /* Remainder in n0 >> bm.  */
+                } else {
+                        /* qq = NN / 0d */
+
+                        if (d0 == 0)
+                                d0 = 1 / d0;    /* Divide intentionally by zero.  */
+
+                        count_leading_zeros(bm, d0);
+
+                        if (bm == 0) {
+                                /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
+                                   conclude (the most significant bit of n1 is set) /\ (the
+                                   leading quotient digit q1 = 1).
+
+                                   This special case is necessary, not an optimization.
+                                   (Shifts counts of SI_TYPE_SIZE are undefined.)  */
+
+                                n1 -= d0;
+                                q1 = 1;
+                        } else {
+                                /* Normalize.  */
+
+                                b = SI_TYPE_SIZE - bm;
+
+                                d0 = d0 << bm;
+                                n2 = n1 >> b;
+                                n1 = (n1 << bm) | (n0 >> b);
+                                n0 = n0 << bm;
+
+                                udiv_qrnnd(q1, n1, n2, n1, d0);
+                        }
+
+                        /* n1 != d0...  */
+
+                        udiv_qrnnd(q0, n0, n1, n0, d0);
+
+                        /* Remainder in n0 >> bm.  */
+                }
+
+                if (rp != 0) {
+                        rr.s.low = n0 >> bm;
+                        rr.s.high = 0;
+                        *rp = rr.ll;
+                }
+        } else {
+                if (d1 > n1) {
+                        /* 00 = nn / DD */
+
+                        q0 = 0;
+                        q1 = 0;
+
+                        /* Remainder in n1n0.  */
+                        if (rp != 0) {
+                                rr.s.low = n0;
+                                rr.s.high = n1;
+                                *rp = rr.ll;
+                        }
+                } else {
+                        /* 0q = NN / dd */
+
+                        count_leading_zeros(bm, d1);
+                        if (bm == 0) {
+                                /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
+                                   conclude (the most significant bit of n1 is set) /\ (the
+                                   quotient digit q0 = 0 or 1).
+
+                                   This special case is necessary, not an optimization.  */
+
+                                /* The condition on the next line takes advantage of that
+                                   n1 >= d1 (true due to program flow).  */
+                                if (n1 > d1 || n0 >= d0) {
+                                        q0 = 1;
+                                        sub_ddmmss(n1, n0, n1, n0, d1, d0);
+                                } else
+                                        q0 = 0;
+
+                                q1 = 0;
+
+                                if (rp != 0) {
+                                        rr.s.low = n0;
+                                        rr.s.high = n1;
+                                        *rp = rr.ll;
+                                }
+                        } else {
+                                u32 m1, m0;
+                                /* Normalize.  */
+
+                                b = SI_TYPE_SIZE - bm;
+
+                                d1 = (d1 << bm) | (d0 >> b);
+                                d0 = d0 << bm;
+                                n2 = n1 >> b;
+                                n1 = (n1 << bm) | (n0 >> b);
+                                n0 = n0 << bm;
+
+                                udiv_qrnnd(q0, n1, n2, n1, d1);
+                                umul_ppmm(m1, m0, q0, d0);
+
+                                if (m1 > n1 || (m1 == n1 && m0 > n0)) {
+                                        q0--;
+                                        sub_ddmmss(m1, m0, m1, m0, d1, d0);
+                                }
+
+                                q1 = 0;
+
+                                /* Remainder in (n1n0 - m1m0) >> bm.  */
+                                if (rp != 0) {
+                                        sub_ddmmss(n1, n0, n1, n0, m1, m0);
+                                        rr.s.low = (n1 << b) | (n0 >> bm);
+                                        rr.s.high = n1 >> bm;
+                                        *rp = rr.ll;
+                                }
+                        }
+                }
+        }
+
+        ww.s.low = q0;
+        ww.s.high = q1;
+        return ww.ll;
 }
 
-UDItype
-__udivdi3 (UDItype n, UDItype d)
+u64 __udivdi3(u64 n, u64 d)
 {
-  return __udivmoddi4 (n, d, (UDItype *) 0);
+        return __udivmoddi4(n, d, (u64 *) 0);
 }
 
-UDItype
-__umoddi3 (UDItype u, UDItype v)
+u64 __umoddi3(u64 u, u64 v)
 {
-  UDItype w;
+        u64 w;
 
-  (void) __udivmoddi4 (u ,v, &w);
+        (void)__udivmoddi4(u, v, &w);
 
-  return w;
+        return w;
 }
-
diff --git a/arch/arm/mach-aaec2000/Kconfig b/arch/arm/mach-aaec2000/Kconfig
new file mode 100644
index 000000000000..5e4bef93754c
--- /dev/null
+++ b/arch/arm/mach-aaec2000/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_AAEC2000
+
+menu "Agilent AAEC-2000 Implementations"
+
+config MACH_AAED2000
+        bool "Agilent AAED-2000 Development Platform"
+        select CPU_ARM920T
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-aaec2000/Makefile b/arch/arm/mach-aaec2000/Makefile
new file mode 100644
index 000000000000..20ec83896c37
--- /dev/null
+++ b/arch/arm/mach-aaec2000/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support (must be linked before board specific support)
+obj-y += core.o
+
+# Specific board support
+obj-$(CONFIG_MACH_AAED2000) += aaed2000.o
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
new file mode 100644
index 000000000000..5417ca3f4621
--- /dev/null
+++ b/arch/arm/mach-aaec2000/aaed2000.c
@@ -0,0 +1,48 @@
+/*
+ *  linux/arch/arm/mach-aaec2000/aaed2000.c
+ *
+ *  Support for the Agilent AAED-2000 Development Platform.
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/major.h>
+#include <linux/interrupt.h>
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "core.h"
+
+static void __init aaed2000_init_irq(void)
+{
+        aaec2000_init_irq();
+}
+
+static void __init aaed2000_map_io(void)
+{
+        aaec2000_map_io();
+}
+
+MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform")
+        MAINTAINER("Nicolas Bellido Y Ortega")
+        BOOT_MEM(0xf0000000, PIO_BASE, VIO_BASE)
+        MAPIO(aaed2000_map_io)
+        INITIRQ(aaed2000_init_irq)
+        .timer          = &aaec2000_timer,
+MACHINE_END
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
new file mode 100644
index 000000000000..fc145b3768fa
--- /dev/null
+++ b/arch/arm/mach-aaec2000/core.c
@@ -0,0 +1,157 @@
+/*
+ *  linux/arch/arm/mach-aaec2000/core.c
+ *
+ *  Code common to all AAEC-2000 machines
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/signal.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+/*
+ * Common I/O mapping:
+ *
+ * Static virtual address mappings are as follow:
+ *
+ * 0xf8000000-0xf8001ffff: Devices connected to APB bus
+ * 0xf8002000-0xf8003ffff: Devices connected to AHB bus
+ *
+ * Below 0xe8000000 is reserved for vm allocation.
+ *
+ * The machine specific code must provide the extra mapping beside the
+ * default mapping provided here.
+ */
+static struct map_desc standard_io_desc[] __initdata = {
+ /* virtual         physical       length           type */
+  { VIO_APB_BASE,   PIO_APB_BASE,  IO_APB_LENGTH,   MT_DEVICE },
+  { VIO_AHB_BASE,   PIO_AHB_BASE,  IO_AHB_LENGTH,   MT_DEVICE }
+};
+
+void __init aaec2000_map_io(void)
+{
+        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+}
+
+/*
+ * Interrupt handling routines
+ */
+static void aaec2000_int_ack(unsigned int irq)
+{
+        IRQ_INTSR = 1 << irq;
+}
+
+static void aaec2000_int_mask(unsigned int irq)
+{
+        IRQ_INTENC |= (1 << irq);
+}
+
+static void aaec2000_int_unmask(unsigned int irq)
+{
+        IRQ_INTENS |= (1 << irq);
+}
+
+static struct irqchip aaec2000_irq_chip = {
+        .ack    = aaec2000_int_ack,
+        .mask   = aaec2000_int_mask,
+        .unmask = aaec2000_int_unmask,
+};
+
+void __init aaec2000_init_irq(void)
+{
+        unsigned int i;
+
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_chip(i, &aaec2000_irq_chip);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        /* Disable all interrupts */
+        IRQ_INTENC = 0xffffffff;
+
+        /* Clear any pending interrupts */
+        IRQ_INTSR = IRQ_INTSR;
+}
+
+/*
+ * Time keeping
+ */
+/* IRQs are disabled before entering here from do_gettimeofday() */
+static unsigned long aaec2000_gettimeoffset(void)
+{
+        unsigned long ticks_to_match, elapsed, usec;
+
+        /* Get ticks before next timer match */
+        ticks_to_match = TIMER1_LOAD - TIMER1_VAL;
+
+        /* We need elapsed ticks since last match */
+        elapsed = LATCH - ticks_to_match;
+
+        /* Now, convert them to usec */
+        usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
+
+        return usec;
+}
+
+/* We enter here with IRQs enabled */
+static irqreturn_t
+aaec2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        /* TODO: Check timer accuracy */
+        write_seqlock(&xtime_lock);
+
+        timer_tick(regs);
+        TIMER1_CLEAR = 1;
+
+        write_sequnlock(&xtime_lock);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction aaec2000_timer_irq = {
+        .name           = "AAEC-2000 Timer Tick",
+        .flags          = SA_INTERRUPT,
+        .handler        = aaec2000_timer_interrupt
+};
+
+static void __init aaec2000_timer_init(void)
+{
+        /* Disable timer 1 */
+        TIMER1_CTRL = 0;
+
+        /* We have somehow to generate a 100Hz clock.
+         * We then use the 508KHz timer in periodic mode.
+         */
+        TIMER1_LOAD = LATCH;
+        TIMER1_CLEAR = 1; /* Clear interrupt */
+
+        setup_irq(INT_TMR1_OFL, &aaec2000_timer_irq);
+
+        TIMER1_CTRL = TIMER_CTRL_ENABLE |
+                        TIMER_CTRL_PERIODIC |
+                        TIMER_CTRL_CLKSEL_508K;
+}
+
+struct sys_timer aaec2000_timer = {
+        .init           = aaec2000_timer_init,
+        .offset         = aaec2000_gettimeoffset,
+};
+
diff --git a/arch/arm/mach-aaec2000/core.h b/arch/arm/mach-aaec2000/core.h
new file mode 100644
index 000000000000..91893d848c16
--- /dev/null
+++ b/arch/arm/mach-aaec2000/core.h
@@ -0,0 +1,16 @@
+/*
+ *  linux/arch/arm/mach-aaec2000/core.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+struct sys_timer;
+
+extern struct sys_timer aaec2000_timer;
+extern void __init aaec2000_map_io(void);
+extern void __init aaec2000_init_irq(void);
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..ebb255bdce8a 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_LEDS)			+= leds.o
 obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)       += cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index bd17b5154311..bd1e5e3c9d34 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
@@ -221,7 +222,23 @@ integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
          */
         timer1->TimerClear = 1;
 
-        timer_tick(regs);
+        /*
+         * the clock tick routines are only processed on the
+         * primary CPU
+         */
+        if (hard_smp_processor_id() == 0) {
+                timer_tick(regs);
+#ifdef CONFIG_SMP
+                smp_send_timer();
+#endif
+        }
+
+#ifdef CONFIG_SMP
+        /*
+         * this is the ARM equivalent of the APIC timer interrupt
+         */
+        update_process_times(user_mode(regs));
+#endif /* CONFIG_SMP */
 
         write_sequnlock(&xtime_lock);
 
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
new file mode 100644
index 000000000000..ceaa88e30d70
--- /dev/null
+++ b/arch/arm/mach-integrator/headsmp.S
@@ -0,0 +1,37 @@
+/*
+ *  linux/arch/arm/mach-integrator/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * Integrator specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(integrator_secondary_startup)
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        ldr     r6, [r6, r4]
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+1:      .long   .
+        .long   phys_pen_release
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3b948e8c2751..e0a01eef0993 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -83,7 +83,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
  { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K,  MT_DEVICE },
  { IO_ADDRESS(INTEGRATOR_DBG_BASE),   INTEGRATOR_DBG_BASE,   SZ_4K,  MT_DEVICE },
  { IO_ADDRESS(INTEGRATOR_GPIO_BASE),  INTEGRATOR_GPIO_BASE,  SZ_4K,  MT_DEVICE },
- { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
  { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
  { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
 };
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index d2c0ab21150c..f1436e683b49 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -22,6 +22,8 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -85,4 +87,4 @@ static int __init leds_init(void)
         return 0;
 }
 
-__initcall(leds_init);
+core_initcall(leds_init);
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
new file mode 100644
index 000000000000..ead15dfcb53d
--- /dev/null
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -0,0 +1,192 @@
+/*
+ *  linux/arch/arm/mach-cintegrator/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+
+#include <asm/atomic.h>
+#include <asm/delay.h>
+#include <asm/mmu_context.h>
+#include <asm/procinfo.h>
+#include <asm/ptrace.h>
+#include <asm/smp.h>
+
+extern void integrator_secondary_startup(void);
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __initdata pen_release = -1;
+unsigned long __initdata phys_pen_release = 0;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __init platform_secondary_init(unsigned int cpu)
+{
+        /*
+         * the primary core may have used a "cross call" soft interrupt
+         * to get this processor out of WFI in the BootMonitor - make
+         * sure that we are no longer being sent this soft interrupt
+         */
+        smp_cross_call_done(cpumask_of_cpu(cpu));
+
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        secondary_scan_irqs();
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu;
+
+        /*
+         * XXX
+         *
+         * This is a later addition to the booting protocol: the
+         * bootMonitor now puts secondary cores into WFI, so
+         * poke_milo() no longer gets the cores moving; we need
+         * to send a soft interrupt to wake the secondary core.
+         * Use smp_cross_call() for this, since there's little
+         * point duplicating the code here
+         */
+        smp_cross_call(cpumask_of_cpu(cpu));
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init poke_milo(void)
+{
+        extern void secondary_startup(void);
+
+        /* nobody is to be released from the pen yet */
+        pen_release = -1;
+
+        phys_pen_release = virt_to_phys(&pen_release);
+
+        /*
+         * write the address of secondary startup into the system-wide
+         * flags register, then clear the bottom two bits, which is what
+         * BootMonitor is waiting for
+         */
+#if 1
+#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
+        __raw_writel(virt_to_phys(integrator_secondary_startup),
+                     (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
+                      CINTEGRATOR_HDR_FLAGSS_OFFSET));
+#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
+        __raw_writel(3,
+                     (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
+                      CINTEGRATOR_HDR_FLAGSC_OFFSET));
+#endif
+
+        mb();
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        unsigned int ncores = get_core_count();
+        unsigned int cpu = smp_processor_id();
+        int i;
+
+        /* sanity check */
+        if (ncores == 0) {
+                printk(KERN_ERR
+                       "Integrator/CP: strange CM count of 0? Default to 1\n");
+
+                ncores = 1;
+        }
+
+        if (ncores > NR_CPUS) {
+                printk(KERN_WARNING
+                       "Integrator/CP: no. of cores (%d) greater than configured "
+                       "maximum of %d - clipping\n",
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
+        }
+
+        /*
+         * start with some more config for the Boot CPU, now that
+         * the world is a bit more alive (which was not the case
+         * when smp_prepare_boot_cpu() was called)
+         */
+        smp_store_cpu_info(cpu);
+
+        /*
+         * are we trying to boot more cores than exist?
+         */
+        if (max_cpus > ncores)
+                max_cpus = ncores;
+
+        /*
+         * Initialise the present mask - this tells us which CPUs should
+         * be present.
+         */
+        for (i = 0; i < max_cpus; i++) {
+                cpu_set(i, cpu_present_mask);
+        }
+
+        /*
+         * Do we need any more CPUs? If so, then let them know where
+         * to start. Note that, on modern versions of MILO, the "poke"
+         * doesn't actually do anything until each individual core is
+         * sent a soft interrupt to get it out of WFI
+         */
+        if (max_cpus > 1)
+                poke_milo();
+}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 4f3c3d5c781c..fc0555596d6d 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -162,12 +162,13 @@ void __init ixp2000_map_io(void)
 static unsigned ticks_per_jiffy;
 static unsigned ticks_per_usec;
 static unsigned next_jiffy_time;
+static volatile unsigned long *missing_jiffy_timer_csr;
 
 unsigned long ixp2000_gettimeoffset (void)
 {
         unsigned long offset;
 
-        offset = next_jiffy_time - *IXP2000_T4_CSR;
+        offset = next_jiffy_time - *missing_jiffy_timer_csr;
 
         return offset / ticks_per_usec;
 }
@@ -179,7 +180,7 @@ static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
         /* clear timer 1 */
         ixp2000_reg_write(IXP2000_T1_CLR, 1);
         
-        while ((next_jiffy_time - *IXP2000_T4_CSR) > ticks_per_jiffy) {
+        while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
                 timer_tick(regs);
                 next_jiffy_time -= ticks_per_jiffy;
         }
@@ -197,20 +198,37 @@ static struct irqaction ixp2000_timer_irq = {
 
 void __init ixp2000_init_time(unsigned long tick_rate)
 {
-        ixp2000_reg_write(IXP2000_T1_CLR, 0);
-        ixp2000_reg_write(IXP2000_T4_CLR, 0);
-
         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
         ticks_per_usec = tick_rate / 1000000;
 
+        /*
+         * We use timer 1 as our timer interrupt.
+         */
+        ixp2000_reg_write(IXP2000_T1_CLR, 0);
         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 
         /*
-         * We use T4 as a monotonic counter to track missed jiffies
+         * We use a second timer as a monotonic counter for tracking
+         * missed jiffies.  The IXP2000 has four timers, but if we're
+         * on an A-step IXP2800, timer 2 and 3 don't work, so on those
+         * chips we use timer 4.  Timer 4 is the only timer that can
+         * be used for the watchdog, so we use timer 2 if we're on a
+         * non-buggy chip.
          */
-        ixp2000_reg_write(IXP2000_T4_CLD, -1);
-        ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
+        if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
+                printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
+
+                ixp2000_reg_write(IXP2000_T4_CLR, 0);
+                ixp2000_reg_write(IXP2000_T4_CLD, -1);
+                ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
+                missing_jiffy_timer_csr = IXP2000_T4_CSR;
+        } else {
+                ixp2000_reg_write(IXP2000_T2_CLR, 0);
+                ixp2000_reg_write(IXP2000_T2_CLD, -1);
+                ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
+                missing_jiffy_timer_csr = IXP2000_T2_CSR;
+        }
         next_jiffy_time = 0xffffffff;
 
         /* register for interrupt */
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index dd012d6e2f5c..f2c9e0d2b24b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/sysdev.h>
 #include <linux/major.h>
 #include <linux/fb.h>
 #include <linux/interrupt.h>
@@ -106,6 +107,35 @@ static void __init lubbock_init_irq(void)
         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
 }
 
+#ifdef CONFIG_PM
+
+static int lubbock_irq_resume(struct sys_device *dev)
+{
+        LUB_IRQ_MASK_EN = lubbock_irq_enabled;
+        return 0;
+}
+
+static struct sysdev_class lubbock_irq_sysclass = {
+        set_kset_name("cpld_irq"),
+        .resume = lubbock_irq_resume,
+};
+
+static struct sys_device lubbock_irq_device = {
+        .cls = &lubbock_irq_sysclass,
+};
+
+static int __init lubbock_irq_device_init(void)
+{
+        int ret = sysdev_class_register(&lubbock_irq_sysclass);
+        if (ret == 0)
+                ret = sysdev_register(&lubbock_irq_device);
+        return ret;
+}
+
+device_initcall(lubbock_irq_device_init);
+
+#endif
+
 static int lubbock_udc_is_connected(void)
 {
         return (LUB_MISC_RD & (1 << 9)) == 0;
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 3f952237ae3d..9896afca751f 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -15,6 +15,7 @@
 
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/bitops.h>
@@ -62,7 +63,6 @@ static struct irqchip mainstone_irq_chip = {
         .unmask         = mainstone_unmask_irq,
 };
 
-
 static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
                                   struct pt_regs *regs)
 {
@@ -100,6 +100,35 @@ static void __init mainstone_init_irq(void)
         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
 }
 
+#ifdef CONFIG_PM
+
+static int mainstone_irq_resume(struct sys_device *dev)
+{
+        MST_INTMSKENA = mainstone_irq_enabled;
+        return 0;
+}
+
+static struct sysdev_class mainstone_irq_sysclass = {
+        set_kset_name("cpld_irq"),
+        .resume = mainstone_irq_resume,
+};
+
+static struct sys_device mainstone_irq_device = {
+        .cls = &mainstone_irq_sysclass,
+};
+
+static int __init mainstone_irq_device_init(void)
+{
+        int ret = sysdev_class_register(&mainstone_irq_sysclass);
+        if (ret == 0)
+                ret = sysdev_register(&mainstone_irq_device);
+        return ret;
+}
+
+device_initcall(mainstone_irq_device_init);
+
+#endif
+
 
 static struct resource smc91x_resources[] = {
         [0] = {
@@ -304,6 +333,15 @@ static void __init mainstone_map_io(void)
         PWER  = 0xC0000002;
         PRER  = 0x00000002;
         PFER  = 0x00000002;
+        /*      for use I SRAM as framebuffer.  */
+        PSLR |= 0xF04;
+        PCFR = 0x66;
+        /*      For Keypad wakeup.      */
+        KPC &=~KPC_ASACT;
+        KPC |=KPC_AS;
+        PKWR  = 0x000FD000;
+        /*      Need read PKWR back after set it.       */
+        PKWR;
 }
 
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 82a4bf34c251..ac4dd4336160 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -29,9 +29,6 @@
  */
 #undef DEBUG
 
-extern void pxa_cpu_suspend(void);
-extern void pxa_cpu_resume(void);
-
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 
@@ -63,6 +60,12 @@ enum {	SLEEP_SAVE_START = 0,
         SLEEP_SAVE_ICMR,
         SLEEP_SAVE_CKEN,
 
+#ifdef CONFIG_PXA27x
+        SLEEP_SAVE_MDREFR,
+        SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
+        SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
+#endif
+
         SLEEP_SAVE_CKSUM,
 
         SLEEP_SAVE_SIZE
@@ -75,9 +78,7 @@ static int pxa_pm_enter(suspend_state_t state)
         unsigned long checksum = 0;
         struct timespec delta, rtc;
         int i;
-
-        if (state != PM_SUSPEND_MEM)
-                return -EINVAL;
+        extern void pxa_cpu_pm_enter(suspend_state_t state);
 
 #ifdef CONFIG_IWMMXT
         /* force any iWMMXt context to ram **/
@@ -100,16 +101,17 @@ static int pxa_pm_enter(suspend_state_t state)
         SAVE(GAFR2_L); SAVE(GAFR2_U);
 
 #ifdef CONFIG_PXA27x
+        SAVE(MDREFR);
         SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
         SAVE(GAFR3_L); SAVE(GAFR3_U);
+        SAVE(PWER); SAVE(PCFR); SAVE(PRER);
+        SAVE(PFER); SAVE(PKWR);
 #endif
 
         SAVE(ICMR);
         ICMR = 0;
 
         SAVE(CKEN);
-        CKEN = 0;
-
         SAVE(PSTR);
 
         /* Note: wake up source are set up in each machine specific files */
@@ -123,16 +125,15 @@ static int pxa_pm_enter(suspend_state_t state)
         /* Clear sleep reset status */
         RCSR = RCSR_SMR;
 
-        /* set resume return address */
-        PSPR = virt_to_phys(pxa_cpu_resume);
-
         /* before sleeping, calculate and save a checksum */
         for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
                 checksum += sleep_save[i];
         sleep_save[SLEEP_SAVE_CKSUM] = checksum;
 
         /* *** go zzz *** */
-        pxa_cpu_suspend();
+        pxa_cpu_pm_enter(state);
+
+        cpu_init();
 
         /* after sleeping, validate the checksum */
         checksum = 0;
@@ -145,7 +146,7 @@ static int pxa_pm_enter(suspend_state_t state)
                 LUB_HEXLED = 0xbadbadc5;
 #endif
                 while (1)
-                        pxa_cpu_suspend();
+                        pxa_cpu_pm_enter(state);
         }
 
         /* ensure not to come back here if it wasn't intended */
@@ -162,8 +163,11 @@ static int pxa_pm_enter(suspend_state_t state)
         RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
 
 #ifdef CONFIG_PXA27x
+        RESTORE(MDREFR);
         RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3);
         RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
+        RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
+        RESTORE(PFER); RESTORE(PKWR);
 #endif
 
         PSSR = PSSR_RDH | PSSR_PH;
@@ -197,7 +201,9 @@ unsigned long sleep_phys_sp(void *sp)
  */
 static int pxa_pm_prepare(suspend_state_t state)
 {
-        return 0;
+        extern int pxa_cpu_pm_prepare(suspend_state_t state);
+
+        return pxa_cpu_pm_prepare(state);
 }
 
 /*
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index e887b7175ef3..7869c3b4e62f 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -16,6 +16,7 @@
  * initialization stuff for PXA machines which can be overridden later if
  * need be.
  */
+#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -102,3 +103,35 @@ unsigned int get_lcdclk_frequency_10khz(void)
 }
 
 EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
+
+#ifdef CONFIG_PM
+
+int pxa_cpu_pm_prepare(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+void pxa_cpu_pm_enter(suspend_state_t state)
+{
+        extern void pxa_cpu_suspend(unsigned int);
+        extern void pxa_cpu_resume(void);
+
+        CKEN = 0;
+
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                /* set resume return address */
+                PSPR = virt_to_phys(pxa_cpu_resume);
+                pxa_cpu_suspend(3);
+                break;
+        }
+}
+
+#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e863afefb53..893964fb9659 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -120,6 +120,42 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
 
+#ifdef CONFIG_PM
+
+int pxa_cpu_pm_prepare(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                return 0;
+        default:
+                return -EINVAL;
+        }
+}
+
+void pxa_cpu_pm_enter(suspend_state_t state)
+{
+        extern void pxa_cpu_standby(void);
+        extern void pxa_cpu_suspend(unsigned int);
+        extern void pxa_cpu_resume(void);
+
+        CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
+
+        /* ensure voltage-change sequencer not initiated, which hangs */
+        PCFR &= ~PCFR_FVC;
+
+        /* Clear edge-detect status register. */
+        PEDR = 0xDF12FE1B;
+
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                /* set resume return address */
+                PSPR = virt_to_phys(pxa_cpu_resume);
+                pxa_cpu_suspend(3);
+                break;
+        }
+}
+
+#endif
 
 /*
  * device registration specific to PXA27x.
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index e23f534d4e1d..8d986b8401c2 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -478,7 +478,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
 {
         unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
 
-        s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2;
+        s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate);
 
         printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
                print_mhz(s3c2440_clk_upll.rate));
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index bc229fab86d4..c7c28890d406 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -785,6 +785,10 @@ int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
         chan->client = NULL;
         chan->in_use = 0;
 
+        if (chan->irq_claimed)
+                free_irq(chan->irq, (void *)chan);
+        chan->irq_claimed = 0;
+
         local_irq_restore(flags);
 
         return 0;
diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c
index 9a8cc5ae2255..d4c8281b55f6 100644
--- a/arch/arm/mach-s3c2410/s3c2440.c
+++ b/arch/arm/mach-s3c2410/s3c2440.c
@@ -192,9 +192,11 @@ void __init s3c2440_map_io(struct map_desc *mach_desc, int size)
 
         iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc));
         iotable_init(mach_desc, size);
+
         /* rename any peripherals used differing from the s3c2410 */
 
-        s3c_device_i2c.name = "s3c2440-i2c";
+        s3c_device_i2c.name  = "s3c2440-i2c";
+        s3c_device_nand.name = "s3c2440-nand";
 
         /* change irq for watchdog */
 
@@ -225,7 +227,7 @@ void __init s3c2440_init_clocks(int xtal)
                 break;
 
         case S3C2440_CLKDIVN_HDIVN_2:
-                hdiv = 1;
+                hdiv = 2;
                 break;
 
         case S3C2440_CLKDIVN_HDIVN_4_8:
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 50cde576dadf..6923316b3d0d 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -150,7 +150,7 @@ config SA1100_SSP
 
 config H3600_SLEEVE
         tristate "Compaq iPAQ Handheld sleeve support"
-        depends on SA1100_H3600
+        depends on SA1100_H3100 || SA1100_H3600
         help
           Choose this option to enable support for extension packs (sleeves)
           for the Compaq iPAQ H3XXX series of handheld computers.  This option
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 379ea5e3950f..59c7964cfe11 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -88,6 +88,8 @@ static int sa11x0_pm_enter(suspend_state_t state)
         /* go zzz */
         sa1100_cpu_suspend();
 
+        cpu_init();
+
         /*
          * Ensure not to come back here if it wasn't intended
          */
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 5d608837757a..ba81e70ed813 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -5,3 +5,4 @@
 obj-y                                   := core.o clock.o
 obj-$(CONFIG_ARCH_VERSATILE_PB)         += versatile_pb.o
 obj-$(CONFIG_MACH_VERSATILE_AB)         += versatile_ab.o
+obj-$(CONFIG_PCI)                       += pci.o
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 554e1bd30d6e..6a7cbea5e098 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -196,11 +196,15 @@ static struct map_desc versatile_io_desc[] __initdata = {
 #ifdef CONFIG_DEBUG_LL
  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
 #endif
-#ifdef FIXME
- { PCI_MEMORY_VADDR,                 PHYS_PCI_MEM_BASE,    SZ_16M,     MT_DEVICE },
- { PCI_CONFIG_VADDR,                 PHYS_PCI_CONFIG_BASE, SZ_16M,     MT_DEVICE },
- { PCI_V3_VADDR,                     PHYS_PCI_V3_BASE,     SZ_512K,    MT_DEVICE },
- { PCI_IO_VADDR,                     PHYS_PCI_IO_BASE,     SZ_64K,     MT_DEVICE },
+#ifdef CONFIG_PCI
+ { IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
+ { VERSATILE_PCI_VIRT_BASE,          VERSATILE_PCI_BASE,   VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
+ { VERSATILE_PCI_CFG_VIRT_BASE,      VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
+#if 0
+ { VERSATILE_PCI_VIRT_MEM_BASE0,     VERSATILE_PCI_MEM_BASE0, SZ_16M,  MT_DEVICE },
+ { VERSATILE_PCI_VIRT_MEM_BASE1,     VERSATILE_PCI_MEM_BASE1, SZ_16M,  MT_DEVICE },
+ { VERSATILE_PCI_VIRT_MEM_BASE2,     VERSATILE_PCI_MEM_BASE2, SZ_16M,  MT_DEVICE },
+#endif
 #endif
 };
 
@@ -543,7 +547,7 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
                 val |= SYS_CLCD_MODE_5551;
                 break;
         case 6:
-                val |= SYS_CLCD_MODE_565_BLSB;
+                val |= SYS_CLCD_MODE_565_RLSB;
                 break;
         case 8:
                 val |= SYS_CLCD_MODE_888;
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
new file mode 100644
index 000000000000..d1565e851f0e
--- /dev/null
+++ b/arch/arm/mach-versatile/pci.c
@@ -0,0 +1,360 @@
+/*
+ *  linux/arch/arm/mach-versatile/pci.c
+ *
+ * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
+ * You can redistribute and/or modify this software under the terms of version 2
+ * of the GNU General Public License as published by the Free Software Foundation.
+ * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
+ * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
+ *
+ * ARM Versatile PCI driver.
+ *
+ * 14/04/2005 Initial version, colin.king@philips.com
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+/*
+ * these spaces are mapped using the following base registers:
+ *
+ * Usage Local Bus Memory         Base/Map registers used
+ *
+ * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
+ * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
+ * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
+ * Cfg   42000000 - 42FFFFFF      PCI config
+ *
+ */
+#define SYS_PCICTL                      IO_ADDRESS(VERSATILE_SYS_PCICTL)
+#define PCI_IMAP0                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
+#define PCI_IMAP1                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
+#define PCI_IMAP2                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
+#define PCI_SMAP0                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
+#define PCI_SMAP1                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
+#define PCI_SMAP2                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
+#define PCI_SELFID                      IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
+
+#define DEVICE_ID_OFFSET                0x00
+#define CSR_OFFSET                      0x04
+#define CLASS_ID_OFFSET                 0x08
+
+#define VP_PCI_DEVICE_ID                0x030010ee
+#define VP_PCI_CLASS_ID                 0x0b400000
+
+static unsigned long pci_slot_ignore = 0;
+
+static int __init versatile_pci_slot_ignore(char *str)
+{
+        int retval;
+        int slot;
+
+        while ((retval = get_option(&str,&slot))) {
+                if ((slot < 0) || (slot > 31)) {
+                        printk("Illegal slot value: %d\n",slot);
+                } else {
+                        pci_slot_ignore |= (1 << slot);
+                }
+        }
+        return 1;
+}
+
+__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
+
+
+static unsigned long __pci_addr(struct pci_bus *bus,
+                                unsigned int devfn, int offset)
+{
+        unsigned int busnr = bus->number;
+
+        /*
+         * Trap out illegal values
+         */
+        if (offset > 255)
+                BUG();
+        if (busnr > 255)
+                BUG();
+        if (devfn > 255)
+                BUG();
+
+        return (VERSATILE_PCI_CFG_VIRT_BASE | (busnr << 16) |
+                (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
+}
+
+static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+                                 int size, u32 *val)
+{
+        unsigned long addr = __pci_addr(bus, devfn, where);
+        u32 v;
+        int slot = PCI_SLOT(devfn);
+
+        if (pci_slot_ignore & (1 << slot)) {
+                /* Ignore this slot */
+                switch (size) {
+                case 1:
+                        v = 0xff;
+                        break;
+                case 2:
+                        v = 0xffff;
+                        break;
+                default:
+                        v = 0xffffffff;
+                }
+        } else {
+                switch (size) {
+                case 1:
+                        addr &= ~3;
+                        v = __raw_readb(addr);
+                        break;
+
+                case 2:
+                        v = __raw_readl(addr & ~3);
+                        if (addr & 2) v >>= 16;
+                        v &= 0xffff;
+                        break;
+
+                default:
+                        addr &= ~3;
+                        v = __raw_readl(addr);
+                        break;
+                }
+        }
+
+        *val = v;
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+                                  int size, u32 val)
+{
+        unsigned long addr = __pci_addr(bus, devfn, where);
+        int slot = PCI_SLOT(devfn);
+
+        if (pci_slot_ignore & (1 << slot)) {
+                return PCIBIOS_SUCCESSFUL;
+        }
+
+        switch (size) {
+        case 1:
+                __raw_writeb((u8)val, addr);
+                break;
+
+        case 2:
+                __raw_writew((u16)val, addr);
+                break;
+
+        case 4:
+                __raw_writel(val, addr);
+                break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops pci_versatile_ops = {
+        .read   = versatile_read_config,
+        .write  = versatile_write_config,
+};
+
+static struct resource io_mem = {
+        .name   = "PCI I/O space",
+        .start  = VERSATILE_PCI_MEM_BASE0,
+        .end    = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource non_mem = {
+        .name   = "PCI non-prefetchable",
+        .start  = VERSATILE_PCI_MEM_BASE1,
+        .end    = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource pre_mem = {
+        .name   = "PCI prefetchable",
+        .start  = VERSATILE_PCI_MEM_BASE2,
+        .end    = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
+        .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+};
+
+static int __init pci_versatile_setup_resources(struct resource **resource)
+{
+        int ret = 0;
+
+        ret = request_resource(&iomem_resource, &io_mem);
+        if (ret) {
+                printk(KERN_ERR "PCI: unable to allocate I/O "
+                       "memory region (%d)\n", ret);
+                goto out;
+        }
+        ret = request_resource(&iomem_resource, &non_mem);
+        if (ret) {
+                printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
+                       "memory region (%d)\n", ret);
+                goto release_io_mem;
+        }
+        ret = request_resource(&iomem_resource, &pre_mem);
+        if (ret) {
+                printk(KERN_ERR "PCI: unable to allocate prefetchable "
+                       "memory region (%d)\n", ret);
+                goto release_non_mem;
+        }
+
+        /*
+         * bus->resource[0] is the IO resource for this bus
+         * bus->resource[1] is the mem resource for this bus
+         * bus->resource[2] is the prefetch mem resource for this bus
+         */
+        resource[0] = &io_mem;
+        resource[1] = &non_mem;
+        resource[2] = &pre_mem;
+
+        goto out;
+
+ release_non_mem:
+        release_resource(&non_mem);
+ release_io_mem:
+        release_resource(&io_mem);
+ out:
+        return ret;
+}
+
+int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+        int i;
+        int myslot = -1;
+        unsigned long val;
+
+        if (nr == 0) {
+                sys->mem_offset = 0;
+                ret = pci_versatile_setup_resources(sys->resource);
+                if (ret < 0) {
+                        printk("pci_versatile_setup: resources... oops?\n");
+                        goto out;
+                }
+        } else {
+                printk("pci_versatile_setup: resources... nr == 0??\n");
+                goto out;
+        }
+
+        __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28,PCI_IMAP0);
+        __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28,PCI_IMAP1);
+        __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28,PCI_IMAP2);
+
+        __raw_writel(1, SYS_PCICTL);
+
+        val = __raw_readl(SYS_PCICTL);
+        if (!(val & 1)) {
+                printk("Not plugged into PCI backplane!\n");
+                ret = -EIO;
+                goto out;
+        }
+
+        /*
+         *  We need to discover the PCI core first to configure itself
+         *  before the main PCI probing is performed
+         */
+        for (i=0; i<32; i++) {
+                if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
+                    (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
+                        myslot = i;
+
+                        __raw_writel(myslot, PCI_SELFID);
+                        val = __raw_readl(VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
+                        val |= (1<<2);
+                        __raw_writel(val, VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
+                        break;
+                }
+        }
+
+        if (myslot == -1) {
+                printk("Cannot find PCI core!\n");
+                ret = -EIO;
+        } else {
+                printk("PCI core found (slot %d)\n",myslot);
+                /* Do not to map Versatile FPGA PCI device
+                   into memory space as we are short of
+                   mappable memory */
+                pci_slot_ignore |= (1 << myslot);
+                ret = 1;
+        }
+
+ out:
+        return ret;
+}
+
+
+struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
+}
+
+/*
+ * V3_LB_BASE? - local bus address
+ * V3_LB_MAP?  - pci bus address
+ */
+void __init pci_versatile_preinit(void)
+{
+}
+
+void __init pci_versatile_postinit(void)
+{
+}
+
+
+/*
+ * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
+ */
+static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+        int devslot = PCI_SLOT(dev->devfn);
+
+        /* slot,  pin,  irq
+            24    1     27
+            25    1     28      untested
+            26    1     29
+            27    1     30      untested
+        */
+
+        irq = 27 + ((slot + pin + 2) % 3);      /* Fudged */
+
+        printk("map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
+
+        return irq;
+}
+
+static struct hw_pci versatile_pci __initdata = {
+        .swizzle                = NULL,
+        .map_irq                = versatile_map_irq,
+        .nr_controllers         = 1,
+        .setup                  = pci_versatile_setup,
+        .scan                   = pci_versatile_scan_bus,
+        .preinit                = pci_versatile_preinit,
+        .postinit               = pci_versatile_postinit,
+};
+
+static int __init versatile_pci_init(void)
+{
+        pci_common_init(&versatile_pci);
+        return 0;
+}
+
+subsys_initcall(versatile_pci_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c4fc6be629de..95606b4a3ba6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,7 +62,7 @@ config CPU_ARM720T
 # ARM920T
 config CPU_ARM920T
         bool "Support ARM920T processor" if !ARCH_S3C2410
-        depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX
+        depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
         default y if ARCH_S3C2410
         select CPU_32v4
         select CPU_ABRT_EV4T
@@ -228,7 +228,6 @@ config CPU_SA1100
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_TLB_V4WB
-        select CPU_MINICACHE
 
 # XScale
 config CPU_XSCALE
@@ -239,7 +238,6 @@ config CPU_XSCALE
         select CPU_ABRT_EV5T
         select CPU_CACHE_VIVT
         select CPU_TLB_V4WBI
-        select CPU_MINICACHE
 
 # ARMv6
 config CPU_V6
@@ -345,11 +343,6 @@ config CPU_TLB_V4WBI
 config CPU_TLB_V6
         bool
 
-config CPU_MINICACHE
-        bool
-        help
-          Processor has a minicache.
-
 comment "Processor Features"
 
 config ARM_THUMB
@@ -412,21 +405,28 @@ config CPU_BPREDICT_DISABLE
 
 config TLS_REG_EMUL
         bool
-        default y if (SMP || CPU_32v6) && (CPU_32v5 || CPU_32v4 || CPU_32v3)
+        default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
         help
-          We might be running on an ARMv6+ processor which should have the TLS
-          register but for some reason we can't use it, or maybe an SMP system
-          using a pre-ARMv6 processor (there are apparently a few prototypes
-          like that in existence) and therefore access to that register must
-          be emulated.
+          An SMP system using a pre-ARMv6 processor (there are apparently
+          a few prototypes like that in existence) and therefore access to
+          that required register must be emulated.
 
 config HAS_TLS_REG
         bool
-        depends on CPU_32v6
-        default y if !TLS_REG_EMUL
+        depends on !TLS_REG_EMUL
+        default y if SMP || CPU_32v7
         help
           This selects support for the CP15 thread register.
-          It is defined to be available on ARMv6 or later.  If a particular
-          ARMv6 or later CPU doesn't support it then it must omc;ide "select
-          TLS_REG_EMUL" along with its other caracteristics.
+          It is defined to be available on some ARMv6 processors (including
+          all SMP capable ARMv6's) or later processors.  User space may
+          assume directly accessing that register and always obtain the
+          expected value only on ARMv7 and above.
+
+config NEEDS_SYSCALL_FOR_CMPXCHG
+        bool
+        default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
+        help
+          SMP on a pre-ARMv6 processor?  Well OK then.
+          Forget about fast user space cmpxchg support.
+          It is just not possible.
 
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ccf316c11e02..59f47d4c2dfe 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_CPU_COPY_V6)	+= copypage-v6.o mmu.o
 obj-$(CONFIG_CPU_SA1100)        += copypage-v4mc.o
 obj-$(CONFIG_CPU_XSCALE)        += copypage-xscale.o
 
-obj-$(CONFIG_CPU_MINICACHE)     += minicache.o
-
 obj-$(CONFIG_CPU_TLB_V3)        += tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
 obj-$(CONFIG_CPU_TLB_V4WB)      += tlb-v4wb.o
diff --git a/arch/arm/mm/copypage-v4mc.S b/arch/arm/mm/copypage-v4mc.S
deleted file mode 100644
index 305af3dab3d8..000000000000
--- a/arch/arm/mm/copypage-v4mc.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  linux/arch/arm/lib/copy_page-armv4mc.S
- *
- *  Copyright (C) 1995-2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  ASM optimised string functions
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/constants.h>
-
-        .text
-        .align  5
-/*
- * ARMv4 mini-dcache optimised copy_user_page
- *
- * We flush the destination cache lines just before we write the data into the
- * corresponding address.  Since the Dcache is read-allocate, this removes the
- * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
- * and merged as appropriate.
- *
- * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
- * instruction.  If your processor does not supply this, you have to write your
- * own copy_user_page that does the right thing.
- */
-ENTRY(v4_mc_copy_user_page)
-        stmfd   sp!, {r4, lr}                   @ 2
-        mov     r4, r0
-        mov     r0, r1
-        bl      map_page_minicache
-        mov     r1, #PAGE_SZ/64                 @ 1
-        ldmia   r0!, {r2, r3, ip, lr}           @ 4
-1:      mcr     p15, 0, r4, c7, c6, 1           @ 1   invalidate D line
-        stmia   r4!, {r2, r3, ip, lr}           @ 4
-        ldmia   r0!, {r2, r3, ip, lr}           @ 4+1
-        stmia   r4!, {r2, r3, ip, lr}           @ 4
-        ldmia   r0!, {r2, r3, ip, lr}           @ 4
-        mcr     p15, 0, r4, c7, c6, 1           @ 1   invalidate D line
-        stmia   r4!, {r2, r3, ip, lr}           @ 4
-        ldmia   r0!, {r2, r3, ip, lr}           @ 4
-        subs    r1, r1, #1                      @ 1
-        stmia   r4!, {r2, r3, ip, lr}           @ 4
-        ldmneia r0!, {r2, r3, ip, lr}           @ 4
-        bne     1b                              @ 1
-        ldmfd   sp!, {r4, pc}                   @ 3
-
-        .align  5
-/*
- * ARMv4 optimised clear_user_page
- *
- * Same story as above.
- */
-ENTRY(v4_mc_clear_user_page)
-        str     lr, [sp, #-4]!
-        mov     r1, #PAGE_SZ/64                 @ 1
-        mov     r2, #0                          @ 1
-        mov     r3, #0                          @ 1
-        mov     ip, #0                          @ 1
-        mov     lr, #0                          @ 1
-1:      mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
-        stmia   r0!, {r2, r3, ip, lr}           @ 4
-        stmia   r0!, {r2, r3, ip, lr}           @ 4
-        mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
-        stmia   r0!, {r2, r3, ip, lr}           @ 4
-        stmia   r0!, {r2, r3, ip, lr}           @ 4
-        subs    r1, r1, #1                      @ 1
-        bne     1b                              @ 1
-        ldr     pc, [sp], #4
-
-        __INITDATA
-
-        .type   v4_mc_user_fns, #object
-ENTRY(v4_mc_user_fns)
-        .long   v4_mc_clear_user_page
-        .long   v4_mc_copy_user_page
-        .size   v4_mc_user_fns, . - v4_mc_user_fns
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
new file mode 100644
index 000000000000..fc69dccdace1
--- /dev/null
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -0,0 +1,111 @@
+/*
+ *  linux/arch/arm/lib/copypage-armv4mc.S
+ *
+ *  Copyright (C) 1995-2005 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This handles the mini data cache, as found on SA11x0 and XScale
+ * processors.  When we copy a user page page, we map it in such a way
+ * that accesses to this page will not touch the main data cache, but
+ * will be cached in the mini data cache.  This prevents us thrashing
+ * the main data cache on page faults.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+
+/*
+ * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
+ * specific hacks for copying pages efficiently.
+ */
+#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
+                                  L_PTE_CACHEABLE)
+
+#define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
+
+static DEFINE_SPINLOCK(minicache_lock);
+
+/*
+ * ARMv4 mini-dcache optimised copy_user_page
+ *
+ * We flush the destination cache lines just before we write the data into the
+ * corresponding address.  Since the Dcache is read-allocate, this removes the
+ * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
+ * and merged as appropriate.
+ *
+ * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
+ * instruction.  If your processor does not supply this, you have to write your
+ * own copy_user_page that does the right thing.
+ */
+static void __attribute__((naked))
+mc_copy_user_page(void *from, void *to)
+{
+        asm volatile(
+        "stmfd  sp!, {r4, lr}                   @ 2\n\
+        mov     r4, %2                          @ 1\n\
+        ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
+1:      mcr     p15, 0, %1, c7, c6, 1           @ 1   invalidate D line\n\
+        stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
+        ldmia   %0!, {r2, r3, ip, lr}           @ 4+1\n\
+        stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
+        ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
+        mcr     p15, 0, %1, c7, c6, 1           @ 1   invalidate D line\n\
+        stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
+        ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
+        subs    r4, r4, #1                      @ 1\n\
+        stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
+        ldmneia %0!, {r2, r3, ip, lr}           @ 4\n\
+        bne     1b                              @ 1\n\
+        ldmfd   sp!, {r4, pc}                   @ 3"
+        :
+        : "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
+}
+
+void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
+{
+        spin_lock(&minicache_lock);
+
+        set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot));
+        flush_tlb_kernel_page(0xffff8000);
+
+        mc_copy_user_page((void *)0xffff8000, kto);
+
+        spin_unlock(&minicache_lock);
+}
+
+/*
+ * ARMv4 optimised clear_user_page
+ */
+void __attribute__((naked))
+v4_mc_clear_user_page(void *kaddr, unsigned long vaddr)
+{
+        asm volatile(
+        "str    lr, [sp, #-4]!\n\
+        mov     r1, %0                          @ 1\n\
+        mov     r2, #0                          @ 1\n\
+        mov     r3, #0                          @ 1\n\
+        mov     ip, #0                          @ 1\n\
+        mov     lr, #0                          @ 1\n\
+1:      mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line\n\
+        stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
+        stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
+        mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line\n\
+        stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
+        stmia   r0!, {r2, r3, ip, lr}           @ 4\n\
+        subs    r1, r1, #1                      @ 1\n\
+        bne     1b                              @ 1\n\
+        ldr     pc, [sp], #4"
+        :
+        : "I" (PAGE_SIZE / 64));
+}
+
+struct cpu_user_fns v4_mc_user_fns __initdata = {
+        .cpu_clear_user_page    = v4_mc_clear_user_page, 
+        .cpu_copy_user_page     = v4_mc_copy_user_page,
+};
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 694ac8208858..27d041574ea7 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -26,11 +26,9 @@
 #define to_address      (0xffffc000)
 #define to_pgprot       PAGE_KERNEL
 
-static pte_t *from_pte;
-static pte_t *to_pte;
-static DEFINE_SPINLOCK(v6_lock);
+#define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
 
-#define DCACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
+static DEFINE_SPINLOCK(v6_lock);
 
 /*
  * Copy the user page.  No aliasing to deal with so we can just
@@ -55,7 +53,7 @@ void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr)
  */
 void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr)
 {
-        unsigned int offset = DCACHE_COLOUR(vaddr);
+        unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long from, to;
 
         /*
@@ -74,8 +72,8 @@ void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vadd
          */
         spin_lock(&v6_lock);
 
-        set_pte(from_pte + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, from_pgprot));
-        set_pte(to_pte + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, to_pgprot));
+        set_pte(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, from_pgprot));
+        set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, to_pgprot));
 
         from = from_address + (offset << PAGE_SHIFT);
         to   = to_address + (offset << PAGE_SHIFT);
@@ -95,7 +93,7 @@ void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vadd
  */
 void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
 {
-        unsigned int offset = DCACHE_COLOUR(vaddr);
+        unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long to = to_address + (offset << PAGE_SHIFT);
 
         /*
@@ -114,7 +112,7 @@ void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
          */
         spin_lock(&v6_lock);
 
-        set_pte(to_pte + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, to_pgprot));
+        set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, to_pgprot));
         flush_tlb_kernel_page(to);
         clear_page((void *)to);
 
@@ -129,21 +127,6 @@ struct cpu_user_fns v6_user_fns __initdata = {
 static int __init v6_userpage_init(void)
 {
         if (cache_is_vipt_aliasing()) {
-                pgd_t *pgd;
-                pmd_t *pmd;
-
-                pgd = pgd_offset_k(from_address);
-                pmd = pmd_alloc(&init_mm, pgd, from_address);
-                if (!pmd)
-                        BUG();
-                from_pte = pte_alloc_kernel(&init_mm, pmd, from_address);
-                if (!from_pte)
-                        BUG();
-
-                to_pte = pte_alloc_kernel(&init_mm, pmd, to_address);
-                if (!to_pte)
-                        BUG();
-
                 cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing;
                 cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing;
         }
@@ -151,5 +134,4 @@ static int __init v6_userpage_init(void)
         return 0;
 }
 
-__initcall(v6_userpage_init);
-
+core_initcall(v6_userpage_init);
diff --git a/arch/arm/mm/copypage-xscale.S b/arch/arm/mm/copypage-xscale.S
deleted file mode 100644
index bb277316ef52..000000000000
--- a/arch/arm/mm/copypage-xscale.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *  linux/arch/arm/lib/copypage-xscale.S
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/constants.h>
-
-/*
- * General note:
- *  We don't really want write-allocate cache behaviour for these functions
- *  since that will just eat through 8K of the cache.
- */
-
-        .text
-        .align  5
-/*
- * XScale optimised copy_user_page
- *  r0 = destination
- *  r1 = source
- *  r2 = virtual user address of ultimate destination page
- *
- * The source page may have some clean entries in the cache already, but we
- * can safely ignore them - break_cow() will flush them out of the cache
- * if we eventually end up using our copied page.
- *
- * What we could do is use the mini-cache to buffer reads from the source
- * page.  We rely on the mini-cache being smaller than one page, so we'll
- * cycle through the complete cache anyway.
- */
-ENTRY(xscale_mc_copy_user_page)
-        stmfd   sp!, {r4, r5, lr}
-        mov     r5, r0
-        mov     r0, r1
-        bl      map_page_minicache
-        mov     r1, r5
-        mov     lr, #PAGE_SZ/64-1
-
-        /*
-         * Strangely enough, best performance is achieved
-         * when prefetching destination as well.  (NP)
-         */
-        pld     [r0, #0]
-        pld     [r0, #32]
-        pld     [r1, #0]
-        pld     [r1, #32]
-
-1:      pld     [r0, #64]
-        pld     [r0, #96]
-        pld     [r1, #64]
-        pld     [r1, #96]
-
-2:      ldrd    r2, [r0], #8
-        ldrd    r4, [r0], #8
-        mov     ip, r1
-        strd    r2, [r1], #8
-        ldrd    r2, [r0], #8
-        strd    r4, [r1], #8
-        ldrd    r4, [r0], #8
-        strd    r2, [r1], #8
-        strd    r4, [r1], #8
-        mcr     p15, 0, ip, c7, c10, 1          @ clean D line
-        ldrd    r2, [r0], #8
-        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line
-        ldrd    r4, [r0], #8
-        mov     ip, r1
-        strd    r2, [r1], #8
-        ldrd    r2, [r0], #8
-        strd    r4, [r1], #8
-        ldrd    r4, [r0], #8
-        strd    r2, [r1], #8
-        strd    r4, [r1], #8
-        mcr     p15, 0, ip, c7, c10, 1          @ clean D line
-        subs    lr, lr, #1
-        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line
-        bgt     1b
-        beq     2b
-
-        ldmfd   sp!, {r4, r5, pc}
-
-        .align  5
-/*
- * XScale optimised clear_user_page
- *  r0 = destination
- *  r1 = virtual user address of ultimate destination page
- */
-ENTRY(xscale_mc_clear_user_page)
-        mov     r1, #PAGE_SZ/32
-        mov     r2, #0
-        mov     r3, #0
-1:      mov     ip, r0
-        strd    r2, [r0], #8
-        strd    r2, [r0], #8
-        strd    r2, [r0], #8
-        strd    r2, [r0], #8
-        mcr     p15, 0, ip, c7, c10, 1          @ clean D line
-        subs    r1, r1, #1
-        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line
-        bne     1b
-        mov     pc, lr
-
-        __INITDATA
-
-        .type   xscale_mc_user_fns, #object
-ENTRY(xscale_mc_user_fns)
-        .long   xscale_mc_clear_user_page
-        .long   xscale_mc_copy_user_page
-        .size   xscale_mc_user_fns, . - xscale_mc_user_fns
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
new file mode 100644
index 000000000000..42a6ee255ce0
--- /dev/null
+++ b/arch/arm/mm/copypage-xscale.c
@@ -0,0 +1,131 @@
+/*
+ *  linux/arch/arm/lib/copypage-xscale.S
+ *
+ *  Copyright (C) 1995-2005 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This handles the mini data cache, as found on SA11x0 and XScale
+ * processors.  When we copy a user page page, we map it in such a way
+ * that accesses to this page will not touch the main data cache, but
+ * will be cached in the mini data cache.  This prevents us thrashing
+ * the main data cache on page faults.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+
+/*
+ * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
+ * specific hacks for copying pages efficiently.
+ */
+#define COPYPAGE_MINICACHE      0xffff8000
+
+#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
+                                  L_PTE_CACHEABLE)
+
+#define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
+
+static DEFINE_SPINLOCK(minicache_lock);
+
+/*
+ * XScale mini-dcache optimised copy_user_page
+ *
+ * We flush the destination cache lines just before we write the data into the
+ * corresponding address.  Since the Dcache is read-allocate, this removes the
+ * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
+ * and merged as appropriate.
+ */
+static void __attribute__((naked))
+mc_copy_user_page(void *from, void *to)
+{
+        /*
+         * Strangely enough, best performance is achieved
+         * when prefetching destination as well.  (NP)
+         */
+        asm volatile(
+        "stmfd  sp!, {r4, r5, lr}               \n\
+        mov     lr, %2                          \n\
+        pld     [r0, #0]                        \n\
+        pld     [r0, #32]                       \n\
+        pld     [r1, #0]                        \n\
+        pld     [r1, #32]                       \n\
+1:      pld     [r0, #64]                       \n\
+        pld     [r0, #96]                       \n\
+        pld     [r1, #64]                       \n\
+        pld     [r1, #96]                       \n\
+2:      ldrd    r2, [r0], #8                    \n\
+        ldrd    r4, [r0], #8                    \n\
+        mov     ip, r1                          \n\
+        strd    r2, [r1], #8                    \n\
+        ldrd    r2, [r0], #8                    \n\
+        strd    r4, [r1], #8                    \n\
+        ldrd    r4, [r0], #8                    \n\
+        strd    r2, [r1], #8                    \n\
+        strd    r4, [r1], #8                    \n\
+        mcr     p15, 0, ip, c7, c10, 1          @ clean D line\n\
+        ldrd    r2, [r0], #8                    \n\
+        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line\n\
+        ldrd    r4, [r0], #8                    \n\
+        mov     ip, r1                          \n\
+        strd    r2, [r1], #8                    \n\
+        ldrd    r2, [r0], #8                    \n\
+        strd    r4, [r1], #8                    \n\
+        ldrd    r4, [r0], #8                    \n\
+        strd    r2, [r1], #8                    \n\
+        strd    r4, [r1], #8                    \n\
+        mcr     p15, 0, ip, c7, c10, 1          @ clean D line\n\
+        subs    lr, lr, #1                      \n\
+        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line\n\
+        bgt     1b                              \n\
+        beq     2b                              \n\
+        ldmfd   sp!, {r4, r5, pc}               "
+        :
+        : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
+}
+
+void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
+{
+        spin_lock(&minicache_lock);
+
+        set_pte(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot));
+        flush_tlb_kernel_page(COPYPAGE_MINICACHE);
+
+        mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
+
+        spin_unlock(&minicache_lock);
+}
+
+/*
+ * XScale optimised clear_user_page
+ */
+void __attribute__((naked))
+xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr)
+{
+        asm volatile(
+        "mov    r1, %0                          \n\
+        mov     r2, #0                          \n\
+        mov     r3, #0                          \n\
+1:      mov     ip, r0                          \n\
+        strd    r2, [r0], #8                    \n\
+        strd    r2, [r0], #8                    \n\
+        strd    r2, [r0], #8                    \n\
+        strd    r2, [r0], #8                    \n\
+        mcr     p15, 0, ip, c7, c10, 1          @ clean D line\n\
+        subs    r1, r1, #1                      \n\
+        mcr     p15, 0, ip, c7, c6, 1           @ invalidate D line\n\
+        bne     1b                              \n\
+        mov     pc, lr"
+        :
+        : "I" (PAGE_SIZE / 32));
+}
+
+struct cpu_user_fns xscale_mc_user_fns __initdata = {
+        .cpu_clear_user_page    = xscale_mc_clear_user_page, 
+        .cpu_copy_user_page     = xscale_mc_copy_user_page,
+};
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 01967ddeef53..be4ab3d73c91 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -77,9 +77,8 @@ no_pmd:
 }
 
 static void
-make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page, int dirty)
+make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
 {
-        struct address_space *mapping = page_mapping(page);
         struct mm_struct *mm = vma->vm_mm;
         struct vm_area_struct *mpnt;
         struct prio_tree_iter iter;
@@ -87,9 +86,6 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
         pgoff_t pgoff;
         int aliases = 0;
 
-        if (!mapping)
-                return;
-
         pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
 
         /*
@@ -115,9 +111,11 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
         if (aliases)
                 adjust_pte(vma, addr);
         else
-                flush_cache_page(vma, addr, page_to_pfn(page));
+                flush_cache_page(vma, addr, pfn);
 }
 
+void __flush_dcache_page(struct address_space *mapping, struct page *page);
+
 /*
  * Take care of architecture specific things when placing a new PTE into
  * a page table, or changing an existing PTE.  Basically, there are two
@@ -134,29 +132,22 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 {
         unsigned long pfn = pte_pfn(pte);
+        struct address_space *mapping;
         struct page *page;
 
         if (!pfn_valid(pfn))
                 return;
+
         page = pfn_to_page(pfn);
-        if (page_mapping(page)) {
+        mapping = page_mapping(page);
+        if (mapping) {
                 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
 
-                if (dirty) {
-                        /*
-                         * This is our first userspace mapping of this page.
-                         * Ensure that the physical page is coherent with
-                         * the kernel mapping.
-                         *
-                         * FIXME: only need to do this on VIVT and aliasing
-                         *        VIPT cache architectures.  We can do that
-                         *        by choosing whether to set this bit...
-                         */
-                        __cpuc_flush_dcache_page(page_address(page));
-                }
+                if (dirty)
+                        __flush_dcache_page(mapping, page);
 
                 if (cache_is_vivt())
-                        make_coherent(vma, addr, page, dirty);
+                        make_coherent(mapping, vma, addr, pfn);
         }
 }
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6de48d89503..191788fb18d1 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,14 +13,32 @@
 
 #include <asm/cacheflush.h>
 #include <asm/system.h>
+#include <asm/tlbflush.h>
 
-static void __flush_dcache_page(struct address_space *mapping, struct page *page)
+#ifdef CONFIG_CPU_CACHE_VIPT
+#define ALIAS_FLUSH_START       0xffff4000
+
+#define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
+
+static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
 {
-        struct mm_struct *mm = current->active_mm;
-        struct vm_area_struct *mpnt;
-        struct prio_tree_iter iter;
-        pgoff_t pgoff;
+        unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
+
+        set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
+        flush_tlb_kernel_page(to);
 
+        asm(    "mcrr   p15, 0, %1, %0, c14\n"
+        "       mcrr    p15, 0, %1, %0, c5\n"
+            :
+            : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
+            : "cc");
+}
+#else
+#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+#endif
+
+void __flush_dcache_page(struct address_space *mapping, struct page *page)
+{
         /*
          * Writeback any data associated with the kernel mapping of this
          * page.  This ensures that data in the physical page is mutually
@@ -29,12 +47,21 @@ static void __flush_dcache_page(struct address_space *mapping, struct page *page
         __cpuc_flush_dcache_page(page_address(page));
 
         /*
-         * If there's no mapping pointer here, then this page isn't
-         * visible to userspace yet, so there are no cache lines
-         * associated with any other aliases.
+         * If this is a page cache page, and we have an aliasing VIPT cache,
+         * we only need to do one flush - which would be at the relevant
+         * userspace colour, which is congruent with page->index.
          */
-        if (!mapping)
-                return;
+        if (mapping && cache_is_vipt_aliasing())
+                flush_pfn_alias(page_to_pfn(page),
+                                page->index << PAGE_CACHE_SHIFT);
+}
+
+static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
+{
+        struct mm_struct *mm = current->active_mm;
+        struct vm_area_struct *mpnt;
+        struct prio_tree_iter iter;
+        pgoff_t pgoff;
 
         /*
          * There are possible user space mappings of this page:
@@ -57,8 +84,6 @@ static void __flush_dcache_page(struct address_space *mapping, struct page *page
                         continue;
                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
                 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
-                if (cache_is_vipt())
-                        break;
         }
         flush_dcache_mmap_unlock(mapping);
 }
@@ -83,12 +108,12 @@ void flush_dcache_page(struct page *page)
 {
         struct address_space *mapping = page_mapping(page);
 
-        if (cache_is_vipt_nonaliasing())
-                return;
-
         if (mapping && !mapping_mapped(mapping))
                 set_bit(PG_dcache_dirty, &page->flags);
-        else
+        else {
                 __flush_dcache_page(mapping, page);
+                if (mapping && cache_is_vivt())
+                        __flush_dcache_aliases(mapping, page);
+        }
 }
 EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 00bb8fd37a59..7110e54182b1 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -170,3 +170,50 @@ void __iounmap(void __iomem *addr)
         vfree((void *) (PAGE_MASK & (unsigned long) addr));
 }
 EXPORT_SYMBOL(__iounmap);
+
+#ifdef __io
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+        return __io(port);
+}
+EXPORT_SYMBOL(ioport_map);
+
+void ioport_unmap(void __iomem *addr)
+{
+}
+EXPORT_SYMBOL(ioport_unmap);
+#endif
+
+#ifdef CONFIG_PCI
+#include <linux/pci.h>
+#include <linux/ioport.h>
+
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+        unsigned long start = pci_resource_start(dev, bar);
+        unsigned long len   = pci_resource_len(dev, bar);
+        unsigned long flags = pci_resource_flags(dev, bar);
+
+        if (!len || !start)
+                return NULL;
+        if (maxlen && len > maxlen)
+                len = maxlen;
+        if (flags & IORESOURCE_IO)
+                return ioport_map(start, len);
+        if (flags & IORESOURCE_MEM) {
+                if (flags & IORESOURCE_CACHEABLE)
+                        return ioremap(start, len);
+                return ioremap_nocache(start, len);
+        }
+        return NULL;
+}
+EXPORT_SYMBOL(pci_iomap);
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+        if ((unsigned long)addr >= VMALLOC_START &&
+            (unsigned long)addr < VMALLOC_END)
+                iounmap(addr);
+}
+EXPORT_SYMBOL(pci_iounmap);
+#endif
diff --git a/arch/arm/mm/minicache.c b/arch/arm/mm/minicache.c
deleted file mode 100644
index dedf2ab01b2a..000000000000
--- a/arch/arm/mm/minicache.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- *  linux/arch/arm/mm/minicache.c
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This handles the mini data cache, as found on SA11x0 and XScale
- * processors.  When we copy a user page page, we map it in such a way
- * that accesses to this page will not touch the main data cache, but
- * will be cached in the mini data cache.  This prevents us thrashing
- * the main data cache on page faults.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-
-/*
- * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
- * specific hacks for copying pages efficiently.
- */
-#define minicache_address (0xffff8000)
-#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
-                                  L_PTE_CACHEABLE)
-
-static pte_t *minicache_pte;
-
-/*
- * Note that this is intended to be called only from the copy_user_page
- * asm code; anything else will require special locking to prevent the
- * mini-cache space being re-used.  (Note: probably preempt unsafe).
- *
- * We rely on the fact that the minicache is 2K, and we'll be pushing
- * 4K of data through it, so we don't actually have to specifically
- * flush the minicache when we change the mapping.
- *
- * Note also: assert(PAGE_OFFSET <= virt < high_memory).
- * Unsafe: preempt, kmap.
- */
-unsigned long map_page_minicache(unsigned long virt)
-{
-        set_pte(minicache_pte, pfn_pte(__pa(virt) >> PAGE_SHIFT, minicache_pgprot));
-        flush_tlb_kernel_page(minicache_address);
-
-        return minicache_address;
-}
-
-static int __init minicache_init(void)
-{
-        pgd_t *pgd;
-        pmd_t *pmd;
-
-        spin_lock(&init_mm.page_table_lock);
-
-        pgd = pgd_offset_k(minicache_address);
-        pmd = pmd_alloc(&init_mm, pgd, minicache_address);
-        if (!pmd)
-                BUG();
-        minicache_pte = pte_alloc_kernel(&init_mm, pmd, minicache_address);
-        if (!minicache_pte)
-                BUG();
-
-        spin_unlock(&init_mm.page_table_lock);
-
-        return 0;
-}
-
-core_initcall(minicache_init);
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 585dfb8e20b9..2c2b93d77d43 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -37,6 +37,8 @@ pgprot_t pgprot_kernel;
 
 EXPORT_SYMBOL(pgprot_kernel);
 
+pmd_t *top_pmd;
+
 struct cachepolicy {
         const char      policy[16];
         unsigned int    cr_mask;
@@ -142,6 +144,16 @@ __setup("noalign", noalign_setup);
 
 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 
+static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
+{
+        return pmd_offset(pgd, virt);
+}
+
+static inline pmd_t *pmd_off_k(unsigned long virt)
+{
+        return pmd_off(pgd_offset_k(virt), virt);
+}
+
 /*
  * need to get a 16k page for level 1
  */
@@ -220,7 +232,7 @@ void free_pgd_slow(pgd_t *pgd)
                 return;
 
         /* pgd is always present and good */
-        pmd = (pmd_t *)pgd;
+        pmd = pmd_off(pgd, 0);
         if (pmd_none(*pmd))
                 goto free;
         if (pmd_bad(*pmd)) {
@@ -246,9 +258,8 @@ free:
 static inline void
 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 {
-        pmd_t *pmdp;
+        pmd_t *pmdp = pmd_off_k(virt);
 
-        pmdp = pmd_offset(pgd_offset_k(virt), virt);
         if (virt & (1 << 20))
                 pmdp++;
 
@@ -283,11 +294,9 @@ alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 static inline void
 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 {
-        pmd_t *pmdp;
+        pmd_t *pmdp = pmd_off_k(virt);
         pte_t *ptep;
 
-        pmdp = pmd_offset(pgd_offset_k(virt), virt);
-
         if (pmd_none(*pmdp)) {
                 unsigned long pmdval;
                 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
@@ -310,7 +319,7 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg
  */
 static inline void clear_mapping(unsigned long virt)
 {
-        pmd_clear(pmd_offset(pgd_offset_k(virt), virt));
+        pmd_clear(pmd_off_k(virt));
 }
 
 struct mem_types {
@@ -578,7 +587,7 @@ void setup_mm_for_reboot(char mode)
                          PMD_TYPE_SECT;
                 if (cpu_arch <= CPU_ARCH_ARMv5)
                         pmdval |= PMD_BIT4;
-                pmd = pmd_offset(pgd + i, i << PGDIR_SHIFT);
+                pmd = pmd_off(pgd, i << PGDIR_SHIFT);
                 pmd[0] = __pmd(pmdval);
                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
                 flush_pmd_entry(pmd);
@@ -675,6 +684,8 @@ void __init memtable_init(struct meminfo *mi)
 
         flush_cache_all();
         flush_tlb_all();
+
+        top_pmd = pmd_off_k(0xffff0000);
 }
 
 /*
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 32c4b0e35b37..3de7f84b53c2 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -73,7 +73,12 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                     (!vma || addr + len <= vma->vm_start))
                         return addr;
         }
-        start_addr = addr = mm->free_area_cache;
+        if (len > mm->cached_hole_size) {
+                start_addr = addr = mm->free_area_cache;
+        } else {
+                start_addr = addr = TASK_UNMAPPED_BASE;
+                mm->cached_hole_size = 0;
+        }
 
 full_search:
         if (do_align)
@@ -90,6 +95,7 @@ full_search:
                          */
                         if (start_addr != TASK_UNMAPPED_BASE) {
                                 start_addr = addr = TASK_UNMAPPED_BASE;
+                                mm->cached_hole_size = 0;
                                 goto full_search;
                         }
                         return -ENOMEM;
@@ -101,6 +107,8 @@ full_search:
                         mm->free_area_cache = addr + len;
                         return addr;
                 }
+                if (addr + mm->cached_hole_size < vma->vm_start)
+                        mm->cached_hole_size = vma->vm_start - addr;
                 addr = vma->vm_end;
                 if (do_align)
                         addr = COLOUR_ALIGN(addr, pgoff);