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authorChander Kashyap <chander.kashyap@linaro.org>2014-07-04 17:24:35 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-18 14:36:00 -0400
commitfc2cac41ebbfb16da8b036cba6ec6714ab780a6d (patch)
tree876fbae26252d39e77b7e89f4ce57a2b08194855 /arch/arm
parentb5a296cdf43e86e189c17537b85c6c0168aae750 (diff)
ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm
In order to support cpuidle through mcpm, suspend and powered-up callbacks are required in mcpm platform code. Hence populate the same callbacks. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Chander Kashyap <k.chander@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index ace0ed617476..13a210865c6f 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -257,10 +257,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
257 return -ETIMEDOUT; /* timeout */ 257 return -ETIMEDOUT; /* timeout */
258} 258}
259 259
260static void exynos_powered_up(void)
261{
262 unsigned int mpidr, cpu, cluster;
263
264 mpidr = read_cpuid_mpidr();
265 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
266 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
267
268 arch_spin_lock(&exynos_mcpm_lock);
269 if (cpu_use_count[cpu][cluster] == 0)
270 cpu_use_count[cpu][cluster] = 1;
271 arch_spin_unlock(&exynos_mcpm_lock);
272}
273
274static void exynos_suspend(u64 residency)
275{
276 unsigned int mpidr, cpunr;
277
278 exynos_power_down();
279
280 /*
281 * Execution reaches here only if cpu did not power down.
282 * Hence roll back the changes done in exynos_power_down function.
283 *
284 * CAUTION: "This function requires the stack data to be visible through
285 * power down and can only be executed on processors like A15 and A7
286 * that hit the cache with the C bit clear in the SCTLR register."
287 */
288 mpidr = read_cpuid_mpidr();
289 cpunr = exynos_pmu_cpunr(mpidr);
290
291 exynos_cpu_power_up(cpunr);
292}
293
260static const struct mcpm_platform_ops exynos_power_ops = { 294static const struct mcpm_platform_ops exynos_power_ops = {
261 .power_up = exynos_power_up, 295 .power_up = exynos_power_up,
262 .power_down = exynos_power_down, 296 .power_down = exynos_power_down,
263 .wait_for_powerdown = exynos_wait_for_powerdown, 297 .wait_for_powerdown = exynos_wait_for_powerdown,
298 .suspend = exynos_suspend,
299 .powered_up = exynos_powered_up,
264}; 300};
265 301
266static void __init exynos_mcpm_usage_count_init(void) 302static void __init exynos_mcpm_usage_count_init(void)