diff options
author | Nicolas Pitre <nico@fluxnic.net> | 2011-05-03 15:30:34 -0400 |
---|---|---|
committer | Nicolas Pitre <nico@fluxnic.net> | 2011-05-03 15:39:05 -0400 |
commit | f5178ddd2f09de8b1cfc5e19043892e8b24666cb (patch) | |
tree | 1df301d8bf3b57a2c95a7b77270188909cce3a36 /arch/arm | |
parent | 0ffd3c4805446dc00a042140443fd7342a35d0b4 (diff) |
ARM: PJ4: remove the ARMv6 compatible cache method entries
The Marvell PJ4 is ARMv7 capable, so we don't support it in
ARMv6 mode anymore.
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Acked-by: Saeed Bishara <saeed.bishara@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/compressed/head.S | 6 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 34 |
2 files changed, 0 insertions, 40 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index adf583cd0c35..a36f4526689b 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -735,12 +735,6 @@ proc_types: | |||
735 | W(b) __armv4_mmu_cache_off | 735 | W(b) __armv4_mmu_cache_off |
736 | W(b) __armv6_mmu_cache_flush | 736 | W(b) __armv6_mmu_cache_flush |
737 | 737 | ||
738 | .word 0x560f5810 @ Marvell PJ4 ARMv6 | ||
739 | .word 0xff0ffff0 | ||
740 | W(b) __armv4_mmu_cache_on | ||
741 | W(b) __armv4_mmu_cache_off | ||
742 | W(b) __armv6_mmu_cache_flush | ||
743 | |||
744 | .word 0x000f0000 @ new CPU Id | 738 | .word 0x000f0000 @ new CPU Id |
745 | .word 0x000f0000 | 739 | .word 0x000f0000 |
746 | W(b) __armv7_mmu_cache_on | 740 | W(b) __armv7_mmu_cache_on |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 7c99cb4c8e4f..ab17cc0d3fa7 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -175,11 +175,6 @@ cpu_v6_name: | |||
175 | .asciz "ARMv6-compatible processor" | 175 | .asciz "ARMv6-compatible processor" |
176 | .size cpu_v6_name, . - cpu_v6_name | 176 | .size cpu_v6_name, . - cpu_v6_name |
177 | 177 | ||
178 | .type cpu_pj4_name, #object | ||
179 | cpu_pj4_name: | ||
180 | .asciz "Marvell PJ4 processor" | ||
181 | .size cpu_pj4_name, . - cpu_pj4_name | ||
182 | |||
183 | .align | 178 | .align |
184 | 179 | ||
185 | __CPUINIT | 180 | __CPUINIT |
@@ -305,32 +300,3 @@ __v6_proc_info: | |||
305 | .long v6_user_fns | 300 | .long v6_user_fns |
306 | .long v6_cache_fns | 301 | .long v6_cache_fns |
307 | .size __v6_proc_info, . - __v6_proc_info | 302 | .size __v6_proc_info, . - __v6_proc_info |
308 | |||
309 | .type __pj4_v6_proc_info, #object | ||
310 | __pj4_v6_proc_info: | ||
311 | .long 0x560f5810 | ||
312 | .long 0xff0ffff0 | ||
313 | ALT_SMP(.long \ | ||
314 | PMD_TYPE_SECT | \ | ||
315 | PMD_SECT_AP_WRITE | \ | ||
316 | PMD_SECT_AP_READ | \ | ||
317 | PMD_FLAGS_SMP) | ||
318 | ALT_UP(.long \ | ||
319 | PMD_TYPE_SECT | \ | ||
320 | PMD_SECT_AP_WRITE | \ | ||
321 | PMD_SECT_AP_READ | \ | ||
322 | PMD_FLAGS_UP) | ||
323 | .long PMD_TYPE_SECT | \ | ||
324 | PMD_SECT_XN | \ | ||
325 | PMD_SECT_AP_WRITE | \ | ||
326 | PMD_SECT_AP_READ | ||
327 | b __v6_setup | ||
328 | .long cpu_arch_name | ||
329 | .long cpu_elf_name | ||
330 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS | ||
331 | .long cpu_pj4_name | ||
332 | .long v6_processor_functions | ||
333 | .long v6wbi_tlb_fns | ||
334 | .long v6_user_fns | ||
335 | .long v6_cache_fns | ||
336 | .size __pj4_v6_proc_info, . - __pj4_v6_proc_info | ||