Merge tag 'omap-for-v3.11/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Omap fixes and minor defconfig updates that would be good to
get in before -rc1.

* tag 'omap-for-v3.11/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: omap2plus_defconfig: Enable appended DTB support
  ARM: OMAP2+: Enable TI_EDMA in omap2plus_defconfig
  ARM: OMAP2+: omap2plus_defconfig: enable DRA752 thermal support by default
  ARM: OMAP2+: omap2plus_defconfig: enable TI bandgap driver
  ARM: OMAP2+: devices: remove duplicated include from devices.c
  ARM: OMAP3: igep0020: Set DSS pins in correct mux mode.
  ARM: OMAP2+: N900: enable N900-specific drivers even if device tree is enabled
  ARM: OMAP2+: Cocci spatch "ptr_ret.spatch"
  ARM: OMAP2+: Remove obsolete Makefile line
  ARM: OMAP5: Enable Cortex A15 errata 798181
  ARM: scu: provide inline dummy functions when SCU is not present
  ARM: OMAP4: sleep: build OMAP4 specific functions only for OMAP4
  ARM: OMAP2+: timer: initialize before using oh_name

Signed-off-by: Olof Johansson <olof@lixom.net>

Add/move/change conflicts in arch/arm/mach-omap2/Kconfig resolved.

134 files changed, 2140 insertions, 2711 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index de7049bdea85..531cdda016f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -175,6 +175,9 @@ config ARCH_HAS_CPUFREQ
           and that the relevant menu configurations are displayed for
           it.
 
+config ARCH_HAS_BANDGAP
+        bool
+
 config GENERIC_HWEIGHT
         bool
         default y
@@ -1450,7 +1453,7 @@ config SMP
         depends on CPU_V6K || CPU_V7
         depends on GENERIC_CLOCKEVENTS
         depends on HAVE_SMP
-        depends on MMU
+        depends on MMU || ARM_MPU
         select USE_GENERIC_SMP_HELPERS
         help
           This enables support for systems with more than one CPU. If you have
@@ -1471,7 +1474,7 @@ config SMP
 
 config SMP_ON_UP
         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-        depends on SMP && !XIP_KERNEL
+        depends on SMP && !XIP_KERNEL && MMU
         default y
         help
           SMP kernels contain instructions which fail on non-SMP processors.
@@ -1744,6 +1747,14 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+       def_bool y
+       depends on ARM_LPAE
+
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+       def_bool y
+       depends on ARM_LPAE
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index c859495da480..aed66d5df7f1 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -50,3 +50,15 @@ config REMAP_VECTORS_TO_RAM
           Otherwise, say 'y' here.  In this case, the kernel will require
           external support to redirect the hardware exception vectors to
           the writable versions located at DRAM_BASE.
+
+config ARM_MPU
+       bool 'Use the ARM v7 PMSA Compliant MPU'
+       depends on CPU_V7
+       default y
+       help
+         Some ARM systems without an MMU have instead a Memory Protection
+         Unit (MPU) that defines the type and permissions for regions of
+         memory.
+
+         If your CPU has an MPU then you should choose 'y' here unless you
+         know that you do not want to use the MPU.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ff4920b1f6c5..e401a766c0bd 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -560,6 +560,13 @@ choice
                   of the tiles using the RS1 memory map, including all new A-class
                   core tiles, FPGA-based SMMs and software models.
 
+        config DEBUG_VEXPRESS_UART0_CRX
+                bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
+                depends on ARCH_VEXPRESS && !MMU
+                help
+                  This option selects UART0 at 0xb0090000. This is appropriate for
+                  Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
+
         config DEBUG_VT8500_UART0
                 bool "Use UART0 on VIA/Wondermedia SoCs"
                 depends on ARCH_VT8500
@@ -789,7 +796,8 @@ config DEBUG_LL_INCLUDE
         default "debug/u300.S" if DEBUG_U300_UART
         default "debug/ux500.S" if DEBUG_UX500_UART
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
-                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \
+                DEBUG_VEXPRESS_UART0_CRX
         default "debug/vt8500.S" if DEBUG_VT8500_UART0
         default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
         default "mach/debug-macro.S"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 72caf82a8280..c0ac0f5e5e5c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,38 +59,44 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7M)        :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
-arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
-arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+arch-$(CONFIG_CPU_32v7M)        =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
+arch-$(CONFIG_CPU_32v7)         =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v6)         =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
 # always available in ARMv7
 ifeq ($(CONFIG_CPU_32v6),y)
-arch-$(CONFIG_CPU_32v6K)        :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+arch-$(CONFIG_CPU_32v6K)        =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
 endif
-arch-$(CONFIG_CPU_32v5)         :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
-arch-$(CONFIG_CPU_32v4T)        :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
-arch-$(CONFIG_CPU_32v4)         :=-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v3)         :=-D__LINUX_ARM_ARCH__=3 -march=armv3
+arch-$(CONFIG_CPU_32v5)         =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
+arch-$(CONFIG_CPU_32v4T)        =-D__LINUX_ARM_ARCH__=4 -march=armv4t
+arch-$(CONFIG_CPU_32v4)         =-D__LINUX_ARM_ARCH__=4 -march=armv4
+arch-$(CONFIG_CPU_32v3)         =-D__LINUX_ARM_ARCH__=3 -march=armv3
+
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
 
 # This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM7TDMI)     :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM720T)      :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM740T)      :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM9TDMI)     :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM940T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946E)      :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
-tune-$(CONFIG_CPU_ARM920T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM922T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM925T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM926T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_FA526)        :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_SA110)        :=-mtune=strongarm110
-tune-$(CONFIG_CPU_SA1100)       :=-mtune=strongarm1100
-tune-$(CONFIG_CPU_XSCALE)       :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_XSC3)         :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_FEROCEON)     :=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
-tune-$(CONFIG_CPU_V6)           :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
-tune-$(CONFIG_CPU_V6K)          :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_ARM7TDMI)     =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM720T)      =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM740T)      =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM9TDMI)     =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM940T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM946E)      =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
+tune-$(CONFIG_CPU_ARM920T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM922T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM926T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_FA526)        =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_SA110)        =-mtune=strongarm110
+tune-$(CONFIG_CPU_SA1100)       =-mtune=strongarm1100
+tune-$(CONFIG_CPU_XSCALE)       =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_XSC3)         =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_FEROCEON)     =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
+tune-$(CONFIG_CPU_V6)           =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_V6K)          =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
 
 ifeq ($(CONFIG_AEABI),y)
 CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork
@@ -295,9 +301,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-%.dtb: scripts
+%.dtb: | scripts
         $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 
+PHONY += dtbs
 dtbs: scripts
         $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs
 
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 120b83bfde20..48d0a44270bd 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -27,7 +27,7 @@ OBJS	+= misc.o decompress.o
 ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
 OBJS    += debug.o
 endif
-FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
+FONTC   = $(srctree)/lib/fonts/font_acorn_8x8.c
 
 # string library code (-Os is enforced to keep it much smaller)
 OBJS            += string.o
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index aabc02a68482..d1153c8a765a 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path,
         return fdt_getprop(fdt, offset, property, len);
 }
 
+static uint32_t get_cell_size(const void *fdt)
+{
+        int len;
+        uint32_t cell_size = 1;
+        const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);
+
+        if (size_len)
+                cell_size = fdt32_to_cpu(*size_len);
+        return cell_size;
+}
+
 static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 {
         char cmdline[COMMAND_LINE_SIZE];
@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 {
         struct tag *atag = atag_list;
-        uint32_t mem_reg_property[2 * NR_BANKS];
+        /* In the case of 64 bits memory size, need to reserve 2 cells for
+         * address and size for each bank */
+        uint32_t mem_reg_property[2 * 2 * NR_BANKS];
         int memcount = 0;
-        int ret;
+        int ret, memsize;
 
         /* make sure we've got an aligned pointer */
         if ((u32)atag_list & 0x3)
@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                                 continue;
                         if (!atag->u.mem.size)
                                 continue;
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
+                        memsize = get_cell_size(fdt);
+
+                        if (memsize == 2) {
+                                /* if memsize is 2, that means that
+                                 * each data needs 2 cells of 32 bits,
+                                 * so the data are 64 bits */
+                                uint64_t *mem_reg_prop64 =
+                                        (uint64_t *)mem_reg_property;
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.start);
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.size);
+                        } else {
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.start);
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.size);
+                        }
+
                 } else if (atag->hdr.tag == ATAG_INITRD2) {
                         uint32_t initrd_start, initrd_size;
                         initrd_start = atag->u.initrd.start;
@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                 }
         }
 
-        if (memcount)
-                setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
+        if (memcount) {
+                setprop(fdt, "/memory", "reg", mem_reg_property,
+                        4 * memcount * memsize);
+        }
 
         return fdt_pack(fdt);
 }
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 032a8d987148..75189f13cf54 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -142,7 +142,6 @@ start:
                 mov     r7, r1                  @ save architecture ID
                 mov     r8, r2                  @ save atags pointer
 
-#ifndef __ARM_ARCH_2__
                 /*
                  * Booting from Angel - need to enter SVC mode and disable
                  * FIQs/IRQs (numeric definitions from angel arm.h source).
@@ -158,10 +157,6 @@ not_angel:
                 safe_svcmode_maskall r0
                 msr     spsr_cxsf, r9           @ Save the CPU boot mode in
                                                 @ SPSR
-#else
-                teqp    pc, #0x0c000003         @ turn off interrupts
-#endif
-
                 /*
                  * Note that some cache flushing and other stuff may
                  * be needed here - is there an Angel SWI call for this?
@@ -183,7 +178,19 @@ not_angel:
                 ldr     r4, =zreladdr
 #endif
 
-                bl      cache_on
+                /*
+                 * Set up a page table only if it won't overwrite ourself.
+                 * That means r4 < pc && r4 - 16k page directory > &_end.
+                 * Given that r4 > &_end is most unfrequent, we add a rough
+                 * additional 1MB of room for a possible appended DTB.
+                 */
+                mov     r0, pc
+                cmp     r0, r4
+                ldrcc   r0, LC0+32
+                addcc   r0, r0, pc
+                cmpcc   r4, r0
+                orrcc   r4, r4, #1              @ remember we skipped cache_on
+                blcs    cache_on
 
 restart:        adr     r0, LC0
                 ldmia   r0, {r1, r2, r3, r6, r10, r11, r12}
@@ -229,7 +236,7 @@ restart:	adr	r0, LC0
  *   r0  = delta
  *   r2  = BSS start
  *   r3  = BSS end
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
  *   r5  = appended dtb size (still unknown)
  *   r6  = _edata
  *   r7  = architecture ID
@@ -277,6 +284,7 @@ restart:	adr	r0, LC0
                  */
                 cmp     r0, #1
                 sub     r0, r4, #TEXT_OFFSET
+                bic     r0, r0, #1
                 add     r0, r0, #0x100
                 mov     r1, r6
                 sub     r2, sp, r6
@@ -323,12 +331,13 @@ dtb_check_done:
 
 /*
  * Check to see if we will overwrite ourselves.
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
  *   r9  = size of decompressed image
  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
  * We basically want:
  *   r4 - 16k page directory >= r10 -> OK
  *   r4 + image length <= address of wont_overwrite -> OK
+ * Note: the possible LSB in r4 is harmless here.
  */
                 add     r10, r10, #16384
                 cmp     r4, r10
@@ -390,7 +399,8 @@ dtb_check_done:
                 add     sp, sp, r6
 #endif
 
-                bl      cache_clean_flush
+                tst     r4, #1
+                bleq    cache_clean_flush
 
                 adr     r0, BSYM(restart)
                 add     r0, r0, r6
@@ -402,7 +412,7 @@ wont_overwrite:
  *   r0  = delta
  *   r2  = BSS start
  *   r3  = BSS end
- *   r4  = kernel execution address
+ *   r4  = kernel execution address (possibly with LSB set)
  *   r5  = appended dtb size (0 if not present)
  *   r7  = architecture ID
  *   r8  = atags pointer
@@ -465,6 +475,15 @@ not_relocated:	mov	r0, #0
                 cmp     r2, r3
                 blo     1b
 
+                /*
+                 * Did we skip the cache setup earlier?
+                 * That is indicated by the LSB in r4.
+                 * Do it now if so.
+                 */
+                tst     r4, #1
+                bic     r4, r4, #1
+                blne    cache_on
+
 /*
  * The C runtime environment should now be setup sufficiently.
  * Set up some pointers, and start decompressing.
@@ -513,6 +532,7 @@ LC0:		.word	LC0			@ r1
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
                 .word   .L_user_stack_end       @ sp
+                .word   _end - restart + 16384 + 1024*1024
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 7d1a27949c13..9866cd736dee 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -613,7 +613,7 @@
                 };
 
                 rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 17979d5f23b4..c0cdf66f8964 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -50,10 +50,10 @@
         };
 
         L2: l2-cache {
-                    compatible = "arm,pl310-cache";
-                    reg = <0x3ff20000 0x1000>;
-                    cache-unified;
-                    cache-level = <2>;
+                compatible = "bcm,bcm11351-a2-pl310-cache";
+                reg = <0x3ff20000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
         };
 
         timer@35006000 {
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index d61b535f682a..e8559b753c9d 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -33,6 +33,8 @@
                         calxeda,port-phys = <&combophy5 0 &combophy0 0
                                              &combophy0 1 &combophy0 2
                                              &combophy0 3>;
+                        calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+                        calxeda,led-order = <4 0 1 2 3>;
                 };
 
                 sdhci@ffe0e000 {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 02edd8965f8a..05e9489cf95c 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -610,7 +610,7 @@
                 };
 
                 rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         reg = <0x80030000 0x10000>;
diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
index 8178705c4b24..80f033614a1f 100644
--- a/arch/arm/common/mcpm_head.S
+++ b/arch/arm/common/mcpm_head.S
@@ -32,11 +32,11 @@
 1901:   adr     r0, 1902b
         bl      printascii
         mov     r0, r9
-        bl      printhex8
+        bl      printhex2
         adr     r0, 1903b
         bl      printascii
         mov     r0, r10
-        bl      printhex8
+        bl      printhex2
         adr     r0, 1904b
         bl      printascii
 #endif
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
index 3caed0db6986..510e5b13aa2e 100644
--- a/arch/arm/common/mcpm_platsmp.c
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -19,10 +19,6 @@
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
 
-static void __init simple_smp_init_cpus(void)
-{
-}
-
 static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned int mpidr, pcpu, pcluster, ret;
@@ -74,7 +70,6 @@ static void mcpm_cpu_die(unsigned int cpu)
 #endif
 
 static struct smp_operations __initdata mcpm_smp_ops = {
-        .smp_init_cpus          = simple_smp_init_cpus,
         .smp_boot_secondary     = mcpm_boot_secondary,
         .smp_secondary_init     = mcpm_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f9b7fccd795d..0870b5cd5533 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -38,6 +38,8 @@ CONFIG_NR_CPUS=2
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
 CONFIG_FPE_NWFPE=y
@@ -156,6 +158,13 @@ CONFIG_W1=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_SENSORS_LM75=m
 CONFIG_WATCHDOG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
 CONFIG_MFD_TPS65217=y
@@ -242,7 +251,13 @@ CONFIG_RTC_DRV_TWL92330=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_OMAP=y
 CONFIG_DMADEVICES=y
+CONFIG_TI_EDMA=y
 CONFIG_DMA_OMAP=y
+CONFIG_TI_SOC_THERMAL=y
+CONFIG_TI_THERMAL=y
+CONFIG_OMAP4_THERMAL=y
+CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0aea0c..accefe099182 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
         return val;
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-        u64 cval;
-
-        isb();
-        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-        return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index cedd3721318b..6493802f880a 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -23,6 +23,11 @@
 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
 #define CR_DT   (1 << 16)
+#ifdef CONFIG_MMU
+#define CR_HA   (1 << 17)       /* Hardware management of Access Flag   */
+#else
+#define CR_BR   (1 << 17)       /* MPU Background region enable (PMSA)  */
+#endif
 #define CR_IT   (1 << 18)
 #define CR_ST   (1 << 19)
 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index d7deb62554c9..8c25dc4e9851 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,7 @@
 #define CPUID_CACHETYPE 1
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#define CPUID_MPUIR     4
 #define CPUID_MPIDR     5
 
 #ifdef CONFIG_CPU_V7M
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index fe92ccf1d0b0..191ada6e4d2d 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -46,7 +46,7 @@
         __rem;                                                  \
 })
 
-#if __GNUC__ < 4
+#if __GNUC__ < 4 || !defined(CONFIG_AEABI)
 
 /*
  * gcc versions earlier than 4.0 are simply too problematic for the
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index e6168c0c18e9..74a8b84f3cb1 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,21 +230,21 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_PJ4B
+#ifdef CONFIG_CPU_V7M
 # ifdef CPU_NAME
 #  undef  MULTI_CPU
 #  define MULTI_CPU
 # else
-#  define CPU_NAME cpu_pj4b
+#  define CPU_NAME cpu_v7m
 # endif
 #endif
 
-#ifdef CONFIG_CPU_V7M
+#ifdef CONFIG_CPU_PJ4B
 # ifdef CPU_NAME
 #  undef  MULTI_CPU
 #  define MULTI_CPU
 # else
-#  define CPU_NAME cpu_v7m
+#  define CPU_NAME cpu_pj4b
 # endif
 #endif
 
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
new file mode 100644
index 000000000000..d4014fbe5ea3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/include/asm/hugetlb-3level.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_3LEVEL_H
+#define _ASM_ARM_HUGETLB_3LEVEL_H
+
+
+/*
+ * If our huge pte is non-zero then mark the valid bit.
+ * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero
+ * ptes.
+ * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes).
+ */
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        pte_t retval = *ptep;
+        if (pte_val(retval))
+                pte_val(retval) |= L_PTE_VALID;
+        return retval;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+        ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+#endif /* _ASM_ARM_HUGETLB_3LEVEL_H */
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
new file mode 100644
index 000000000000..1f1b1cd112f3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb.h
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_H
+#define _ASM_ARM_HUGETLB_H
+
+#include <asm/page.h>
+#include <asm-generic/hugetlb.h>
+
+#include <asm/hugetlb-3level.h>
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr, unsigned long len)
+{
+        return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr, unsigned long len)
+{
+        struct hstate *h = hstate_file(file);
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+        clear_bit(PG_dcache_clean, &page->flags);
+}
+
+#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 652b56086de7..d070741b2b37 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
  */
 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
         size_t, unsigned int, void *);
-extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
         void *);
 
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
+extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
+extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
 extern void __arm_iounmap(volatile void __iomem *addr);
 
-extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
         unsigned int, void *);
 extern void (*arch_iounmap)(volatile void __iomem *);
 
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
deleted file mode 100644
index 68cb9e1dfb81..000000000000
--- a/arch/arm/include/asm/kvm_arch_timer.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
-#define __ASM_ARM_KVM_ARCH_TIMER_H
-
-#include <linux/clocksource.h>
-#include <linux/hrtimer.h>
-#include <linux/workqueue.h>
-
-struct arch_timer_kvm {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Is the timer enabled */
-        bool                    enabled;
-
-        /* Virtual offset */
-        cycle_t                 cntvoff;
-#endif
-};
-
-struct arch_timer_cpu {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Registers: control register, timer value */
-        u32                             cntv_ctl;       /* Saved/restored */
-        cycle_t                         cntv_cval;      /* Saved/restored */
-
-        /*
-         * Anything that is not used directly from assembly code goes
-         * here.
-         */
-
-        /* Background timer used when the guest is not running */
-        struct hrtimer                  timer;
-
-        /* Work queued with the above timer expires */
-        struct work_struct              expired;
-
-        /* Background timer active */
-        bool                            armed;
-
-        /* Timer IRQ */
-        const struct kvm_irq_level      *irq;
-#endif
-};
-
-#ifdef CONFIG_KVM_ARM_TIMER
-int kvm_timer_hyp_init(void);
-int kvm_timer_init(struct kvm *kvm);
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
-#else
-static inline int kvm_timer_hyp_init(void)
-{
-        return 0;
-};
-
-static inline int kvm_timer_init(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e5ef14..64e96960de29 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1ULL)
 #define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
 #define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
-#define S2_PGD_SIZE     (1 << S2_PGD_ORDER)
 
 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0        (3 << 12)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d50322a9e2..a2f43ddcc300 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -37,16 +37,18 @@
 #define c5_AIFSR        15      /* Auxilary Instrunction Fault Status R */
 #define c6_DFAR         16      /* Data Fault Address Register */
 #define c6_IFAR         17      /* Instruction Fault Address Register */
-#define c9_L2CTLR       18      /* Cortex A15 L2 Control Register */
-#define c10_PRRR        19      /* Primary Region Remap Register */
-#define c10_NMRR        20      /* Normal Memory Remap Register */
-#define c12_VBAR        21      /* Vector Base Address Register */
-#define c13_CID         22      /* Context ID Register */
-#define c13_TID_URW     23      /* Thread ID, User R/W */
-#define c13_TID_URO     24      /* Thread ID, User R/O */
-#define c13_TID_PRIV    25      /* Thread ID, Privileged */
-#define c14_CNTKCTL     26      /* Timer Control Register (PL1) */
-#define NR_CP15_REGS    27      /* Number of regs (incl. invalid) */
+#define c7_PAR          18      /* Physical Address Register */
+#define c7_PAR_high     19      /* PAR top 32 bits */
+#define c9_L2CTLR       20      /* Cortex A15 L2 Control Register */
+#define c10_PRRR        21      /* Primary Region Remap Register */
+#define c10_NMRR        22      /* Normal Memory Remap Register */
+#define c12_VBAR        23      /* Vector Base Address Register */
+#define c13_CID         24      /* Context ID Register */
+#define c13_TID_URW     25      /* Thread ID, User R/W */
+#define c13_TID_URO     26      /* Thread ID, User R/O */
+#define c13_TID_PRIV    27      /* Thread ID, Privileged */
+#define c14_CNTKCTL     28      /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    29      /* Number of regs (incl. invalid) */
 
 #define ARM_EXCEPTION_RESET       0
 #define ARM_EXCEPTION_UNDEFINED   1
@@ -72,8 +74,6 @@ extern char __kvm_hyp_vector[];
 extern char __kvm_hyp_code_start[];
 extern char __kvm_hyp_code_end[];
 
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
-
 extern void __kvm_flush_vm_context(void);
 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
 
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 82b4babead2c..a464e8d7b6c5 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
         return cpsr_mode > USR_MODE;;
 }
 
-static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
-{
-        return reg == 15;
-}
-
 static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
 {
         return vcpu->arch.fault.hsr;
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786a6203..7d22517d8071 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,9 +23,14 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_arch_timer.h>
 
+#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#else
+#define KVM_MAX_VCPUS 0
+#endif
+
 #define KVM_USER_MEM_SLOTS 32
 #define KVM_PRIVATE_MEM_SLOTS 4
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -38,7 +43,7 @@
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
 
-#include <asm/kvm_vgic.h>
+#include <kvm/arm_vgic.h>
 
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
@@ -190,8 +195,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
                 int exception_index);
 
-static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
-                                       unsigned long long pgd_ptr,
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+                                       phys_addr_t pgd_ptr,
                                        unsigned long hyp_stack_ptr,
                                        unsigned long vector_ptr)
 {
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
deleted file mode 100644
index 343744e4809c..000000000000
--- a/arch/arm/include/asm/kvm_vgic.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_KVM_VGIC_H
-#define __ASM_ARM_KVM_VGIC_H
-
-#include <linux/kernel.h>
-#include <linux/kvm.h>
-#include <linux/irqreturn.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <linux/irqchip/arm-gic.h>
-
-#define VGIC_NR_IRQS            128
-#define VGIC_NR_SGIS            16
-#define VGIC_NR_PPIS            16
-#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
-#define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
-#define VGIC_MAX_CPUS           KVM_MAX_VCPUS
-#define VGIC_MAX_LRS            (1 << 6)
-
-/* Sanity checks... */
-#if (VGIC_MAX_CPUS > 8)
-#error  Invalid number of CPU interfaces
-#endif
-
-#if (VGIC_NR_IRQS & 31)
-#error "VGIC_NR_IRQS must be a multiple of 32"
-#endif
-
-#if (VGIC_NR_IRQS > 1024)
-#error "VGIC_NR_IRQS must be <= 1024"
-#endif
-
-/*
- * The GIC distributor registers describing interrupts have two parts:
- * - 32 per-CPU interrupts (SGI + PPI)
- * - a bunch of shared interrupts (SPI)
- */
-struct vgic_bitmap {
-        union {
-                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
-        } percpu[VGIC_MAX_CPUS];
-        union {
-                u32 reg[VGIC_NR_SHARED_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
-        } shared;
-};
-
-struct vgic_bytemap {
-        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
-        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
-};
-
-struct vgic_dist {
-#ifdef CONFIG_KVM_ARM_VGIC
-        spinlock_t              lock;
-        bool                    ready;
-
-        /* Virtual control interface mapping */
-        void __iomem            *vctrl_base;
-
-        /* Distributor and vcpu interface mapping in the guest */
-        phys_addr_t             vgic_dist_base;
-        phys_addr_t             vgic_cpu_base;
-
-        /* Distributor enabled */
-        u32                     enabled;
-
-        /* Interrupt enabled (one bit per IRQ) */
-        struct vgic_bitmap      irq_enabled;
-
-        /* Interrupt 'pin' level */
-        struct vgic_bitmap      irq_state;
-
-        /* Level-triggered interrupt in progress */
-        struct vgic_bitmap      irq_active;
-
-        /* Interrupt priority. Not used yet. */
-        struct vgic_bytemap     irq_priority;
-
-        /* Level/edge triggered */
-        struct vgic_bitmap      irq_cfg;
-
-        /* Source CPU per SGI and target CPU */
-        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
-
-        /* Target CPU for each IRQ */
-        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
-        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
-
-        /* Bitmap indicating which CPU has something pending */
-        unsigned long           irq_pending_on_cpu;
-#endif
-};
-
-struct vgic_cpu {
-#ifdef CONFIG_KVM_ARM_VGIC
-        /* per IRQ to LR mapping */
-        u8              vgic_irq_lr_map[VGIC_NR_IRQS];
-
-        /* Pending interrupts on this VCPU */
-        DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
-        DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
-
-        /* Bitmap of used/free list registers */
-        DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
-
-        /* Number of list registers on this CPU */
-        int             nr_lr;
-
-        /* CPU vif control registers for world switch */
-        u32             vgic_hcr;
-        u32             vgic_vmcr;
-        u32             vgic_misr;      /* Saved only */
-        u32             vgic_eisr[2];   /* Saved only */
-        u32             vgic_elrsr[2];  /* Saved only */
-        u32             vgic_apr;
-        u32             vgic_lr[VGIC_MAX_LRS];
-#endif
-};
-
-#define LR_EMPTY        0xff
-
-struct kvm;
-struct kvm_vcpu;
-struct kvm_run;
-struct kvm_exit_mmio;
-
-#ifdef CONFIG_KVM_ARM_VGIC
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
-int kvm_vgic_hyp_init(void);
-int kvm_vgic_init(struct kvm *kvm);
-int kvm_vgic_create(struct kvm *kvm);
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level);
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio);
-
-#define irqchip_in_kernel(k)    (!!((k)->arch.vgic.vctrl_base))
-#define vgic_initialized(k)     ((k)->arch.vgic.ready)
-
-#else
-static inline int kvm_vgic_hyp_init(void)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_init(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_create(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-
-static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
-
-static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
-                                      unsigned int irq_num, bool level)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-
-static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                                    struct kvm_exit_mmio *mmio)
-{
-        return false;
-}
-
-static inline int irqchip_in_kernel(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline bool vgic_initialized(struct kvm *kvm)
-{
-        return true;
-}
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab313c5..e750a938fd3c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/cache.h>
+
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -141,6 +143,20 @@
 #define page_to_phys(page)      (__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)      (pfn_to_page(__phys_to_pfn(phys)))
 
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT          L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT          0
+#endif
+#define ARCH_PGD_MASK           ((1 << ARCH_PGD_SHIFT) - 1)
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -207,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
  * direct-mapped view.  We assume this is the first page
  * of RAM in the mem_map as well.
  */
-#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
@@ -260,12 +276,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 /*
  * Conversion between a struct page and a physical address.
  *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
  *  page_to_pfn(page)   convert a struct page * to a PFN number
  *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
  *
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a7b85e0d0cc1..b5792b7fd8d3 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
+#include <asm/smp_plat.h>
 #include <asm-generic/mm_hooks.h>
 
 void __check_vmalloc_seq(struct mm_struct *mm);
@@ -27,7 +28,15 @@ void __check_vmalloc_seq(struct mm_struct *mm);
 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
 #define init_new_context(tsk,mm)        ({ atomic64_set(&mm->context.id, 0); 0; })
 
-DECLARE_PER_CPU(atomic64_t, active_asids);
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask);
+#else  /* !CONFIG_ARM_ERRATA_798181 */
+static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                                           cpumask_t *mask)
+{
+}
+#endif /* CONFIG_ARM_ERRATA_798181 */
 
 #else   /* !CONFIG_CPU_HAS_ASID */
 
@@ -98,12 +107,16 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
         unsigned int cpu = smp_processor_id();
 
-#ifdef CONFIG_SMP
-        /* check for possible thread migration */
-        if (!cpumask_empty(mm_cpumask(next)) &&
+        /*
+         * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
+         * so check for possible thread migration and invalidate the I-cache
+         * if we're new to this CPU.
+         */
+        if (cache_ops_need_broadcast() &&
+            !cpumask_empty(mm_cpumask(next)) &&
             !cpumask_test_cpu(cpu, mm_cpumask(next)))
                 __flush_icache_all();
-#endif
+
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
                 check_and_switch_context(next, tsk);
                 if (cache_is_vivt())
diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
new file mode 100644
index 000000000000..c3247cc2fe08
--- /dev/null
+++ b/arch/arm/include/asm/mpu.h
@@ -0,0 +1,76 @@
+#ifndef __ARM_MPU_H
+#define __ARM_MPU_H
+
+#ifdef CONFIG_ARM_MPU
+
+/* MPUIR layout */
+#define MPUIR_nU                1
+#define MPUIR_DREGION           8
+#define MPUIR_IREGION           16
+#define MPUIR_DREGION_SZMASK    (0xFF << MPUIR_DREGION)
+#define MPUIR_IREGION_SZMASK    (0xFF << MPUIR_IREGION)
+
+/* ID_MMFR0 data relevant to MPU */
+#define MMFR0_PMSA              (0xF << 4)
+#define MMFR0_PMSAv7            (3 << 4)
+
+/* MPU D/I Size Register fields */
+#define MPU_RSR_SZ              1
+#define MPU_RSR_EN              0
+
+/* The D/I RSR value for an enabled region spanning the whole of memory */
+#define MPU_RSR_ALL_MEM         63
+
+/* Individual bits in the DR/IR ACR */
+#define MPU_ACR_XN              (1 << 12)
+#define MPU_ACR_SHARED          (1 << 2)
+
+/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
+#define MPU_RGN_CACHEABLE       0xB
+#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#define MPU_RGN_STRONGLY_ORDERED 0
+
+/* Main region should only be shared for SMP */
+#ifdef CONFIG_SMP
+#define MPU_RGN_NORMAL          (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#else
+#define MPU_RGN_NORMAL          MPU_RGN_CACHEABLE
+#endif
+
+/* Access permission bits of ACR (only define those that we use)*/
+#define MPU_AP_PL1RW_PL0RW      (0x3 << 8)
+#define MPU_AP_PL1RW_PL0R0      (0x2 << 8)
+#define MPU_AP_PL1RW_PL0NA      (0x1 << 8)
+
+/* For minimal static MPU region configurations */
+#define MPU_PROBE_REGION        0
+#define MPU_BG_REGION           1
+#define MPU_RAM_REGION          2
+#define MPU_VECTORS_REGION      3
+
+/* Maximum number of regions Linux is interested in */
+#define MPU_MAX_REGIONS         16
+
+#define MPU_DATA_SIDE           0
+#define MPU_INSTR_SIDE          1
+
+#ifndef __ASSEMBLY__
+
+struct mpu_rgn {
+        /* Assume same attributes for d/i-side  */
+        u32 drbar;
+        u32 drsr;
+        u32 dracr;
+};
+
+struct mpu_rgn_info {
+        u32 mpuir;
+        struct mpu_rgn rgns[MPU_MAX_REGIONS];
+};
+extern struct mpu_rgn_info mpu_rgn_info;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_MPU */
+
+#endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a4944e783..6363f3d1d505 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT              12
 #define PAGE_SIZE               (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK               (~(PAGE_SIZE-1))
+#define PAGE_MASK               (~((1 << PAGE_SHIFT) - 1))
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef82ad5..626989fec4d3 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -30,6 +30,7 @@
 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
 #define PMD_BIT4                (_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
 #define PMD_APTABLE_SHIFT       (61)
@@ -41,6 +42,8 @@
  */
 #define PMD_SECT_BUFFERABLE     (_AT(pmdval_t, 1) << 2)
 #define PMD_SECT_CACHEABLE      (_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
+#define PMD_SECT_RDONLY         (_AT(pmdval_t, 1) << 7)         /* AP[2] */
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
@@ -66,6 +69,7 @@
 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
 #define PTE_BUFFERABLE          (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
 #define PTE_CACHEABLE           (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
 #define PTE_EXT_SHARED          (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
@@ -79,4 +83,24 @@
 #define PHYS_MASK_SHIFT         (40)
 #define PHYS_MASK               ((1ULL << PHYS_MASK_SHIFT) - 1)
 
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET    16                      /* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET    (4096 * (1 + 3))        /* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET    0
+#endif
+
+#define TTBR1_SIZE      (((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe398b95..5689c18c85f5 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -33,7 +33,7 @@
 #define PTRS_PER_PMD            512
 #define PTRS_PER_PGD            4
 
-#define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
+#define PTE_HWTABLE_PTRS        (0)
 #define PTE_HWTABLE_OFF         (0)
 #define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u64))
 
@@ -48,20 +48,28 @@
 #define PMD_SHIFT               21
 
 #define PMD_SIZE                (1UL << PMD_SHIFT)
-#define PMD_MASK                (~(PMD_SIZE-1))
+#define PMD_MASK                (~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+#define PGDIR_MASK              (~((1 << PGDIR_SHIFT) - 1))
 
 /*
  * section address mask and size definitions.
  */
 #define SECTION_SHIFT           21
 #define SECTION_SIZE            (1UL << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
+#define SECTION_MASK            (~((1 << SECTION_SHIFT) - 1))
 
 #define USER_PTRS_PER_PGD       (PAGE_OFFSET / PGDIR_SIZE)
 
 /*
+ * Hugetlb definitions.
+ */
+#define HPAGE_SHIFT             PMD_SHIFT
+#define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+
+/*
  * "Linux" PTE definitions for LPAE.
  *
  * These bits overlap with the hardware bits but the naming is preserved for
@@ -79,6 +87,11 @@
 #define L_PTE_SPECIAL           (_AT(pteval_t, 1) << 56)        /* unused */
 #define L_PTE_NONE              (_AT(pteval_t, 1) << 57)        /* PROT_NONE */
 
+#define PMD_SECT_VALID          (_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_DIRTY          (_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING      (_AT(pmdval_t, 1) << 56)
+#define PMD_SECT_NONE           (_AT(pmdval_t, 1) << 57)
+
 /*
  * To be used in assembly code with the upper page attributes.
  */
@@ -166,8 +179,83 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
                 clean_pmd_entry(pmdp);  \
         } while (0)
 
+/*
+ * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
+ * that are written to a page table but not for ptes created with mk_pte.
+ *
+ * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
+ * hugetlb_cow, where it is compared with an entry in a page table.
+ * This comparison test fails erroneously leading ultimately to a memory leak.
+ *
+ * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
+ * present before running the comparison.
+ */
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(pte_a,pte_b)   ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG     \
+                                        : pte_val(pte_a))                               \
+                                == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG   \
+                                        : pte_val(pte_b)))
+
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
 
+#define pte_huge(pte)           (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
+#define pmd_young(pmd)          (pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)          (!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,     &= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+
+#define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
+
+/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
+#define pmd_mknotpresent(pmd)   (__pmd(0))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
+                                PMD_SECT_VALID | PMD_SECT_NONE;
+        pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+        return pmd;
+}
+
+static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                              pmd_t *pmdp, pmd_t pmd)
+{
+        BUG_ON(addr >= TASK_SIZE);
+
+        /* create a faulting entry if PROT_NONE protected */
+        if (pmd_val(pmd) & PMD_SECT_NONE)
+                pmd_val(pmd) &= ~PMD_SECT_VALID;
+
+        *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
+        flush_pmd_entry(pmdp);
+}
+
+static inline int has_transparent_hugepage(void)
+{
+        return 1;
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 229e0dde9c71..04aeb02d2e11 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,9 @@
 #include <asm/memory.h>
 #include <asm/pgtable-hwdef.h>
 
+
+#include <asm/tlbflush.h>
+
 #ifdef CONFIG_ARM_LPAE
 #include <asm/pgtable-3level.h>
 #else
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb3d2b3..5324c1112f3a 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
         /*
          * Set the page table
          */
-        void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+        void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
         /*
          * Set a possibly extended PTE.  Non-extended PTEs should
          * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)                                        \
+        ({                                                      \
+                u64 ttbr;                                       \
+                __asm__("mrrc   p15, " #nr ", %Q0, %R0, c2"     \
+                        : "=r" (ttbr));                         \
+                ttbr;                                           \
+        })
+
+#define cpu_set_ttbr(nr, val)                                   \
+        do {                                                    \
+                u64 ttbr = val;                                 \
+                __asm__("mcrr   p15, " #nr ", %Q0, %R0, c2"     \
+                        : : "r" (ttbr));                        \
+        } while (0)
+
 #define cpu_get_pgd()   \
         ({                                              \
-                unsigned long pg, pg2;                  \
-                __asm__("mrrc   p15, 0, %0, %1, c2"     \
-                        : "=r" (pg), "=r" (pg2)         \
-                        :                               \
-                        : "cc");                        \
+                u64 pg = cpu_get_ttbr(0);               \
                 pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
                 (pgd_t *)phys_to_virt(pg);              \
         })
@@ -137,6 +149,10 @@ extern void cpu_resume(void);
         })
 #endif
 
+#else   /*!CONFIG_MMU */
+
+#define cpu_switch_mm(pgd,mm)   { }
+
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index d3a22bebe6ce..a8cae71caceb 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -65,7 +65,10 @@ asmlinkage void secondary_start_kernel(void);
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
-        unsigned long pgdir;
+        union {
+                unsigned long mpu_rgn_szr;
+                unsigned long pgdir;
+        };
         unsigned long swapper_pg_dir;
         void *stack;
 };
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e78983202737..6462a721ebd4 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -26,6 +26,9 @@ static inline bool is_smp(void)
 }
 
 /* all SMP configurations have the extended CPUID registers */
+#ifndef CONFIG_MMU
+#define tlb_ops_need_broadcast()        0
+#else
 static inline int tlb_ops_need_broadcast(void)
 {
         if (!is_smp())
@@ -33,6 +36,7 @@ static inline int tlb_ops_need_broadcast(void)
 
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
+#endif
 
 #if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
 #define cache_ops_need_broadcast()      0
@@ -66,4 +70,22 @@ static inline int get_logical_index(u32 mpidr)
         return -EINVAL;
 }
 
+/*
+ * NOTE ! Assembly code relies on the following
+ * structure memory layout in order to carry out load
+ * multiple from its base address. For more
+ * information check arch/arm/kernel/sleep.S
+ */
+struct mpidr_hash {
+        u32     mask; /* used by sleep.S */
+        u32     shift_aff[3]; /* used by sleep.S */
+        u32     bits;
+};
+
+extern struct mpidr_hash mpidr_hash;
+
+static inline u32 mpidr_hash_size(void)
+{
+        return 1 << mpidr_hash.bits;
+}
 #endif
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 18d169373612..0393fbab8dd5 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -23,10 +23,21 @@ static inline unsigned long scu_a9_get_base(void)
         return pa;
 }
 
+#ifdef CONFIG_HAVE_ARM_SCU
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+#else
+static inline unsigned int scu_get_core_count(void __iomem *scu_base)
+{
+        return 0;
+}
+static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+{
+        return -EINVAL;
+}
+#endif
 
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
 void scu_enable(void __iomem *scu_base);
 #else
 static inline void scu_enable(void __iomem *scu_base) {}
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 6220e9fdf4c7..f8b8965666e9 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -97,19 +97,22 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
-        unsigned long tmp;
+        unsigned long contended, res;
         u32 slock;
 
-        __asm__ __volatile__(
-"       ldrex   %0, [%2]\n"
-"       subs    %1, %0, %0, ror #16\n"
-"       addeq   %0, %0, %3\n"
-"       strexeq %1, %0, [%2]"
-        : "=&r" (slock), "=&r" (tmp)
-        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
-        : "cc");
-
-        if (tmp == 0) {
+        do {
+                __asm__ __volatile__(
+                "       ldrex   %0, [%3]\n"
+                "       mov     %2, #0\n"
+                "       subs    %1, %0, %0, ror #16\n"
+                "       addeq   %0, %0, %4\n"
+                "       strexeq %2, %0, [%3]"
+                : "=&r" (slock), "=&r" (contended), "=r" (res)
+                : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
+                : "cc");
+        } while (res);
+
+        if (!contended) {
                 smp_mb();
                 return 1;
         } else {
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index 1c0a551ae375..cd20029bcd94 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
 
+struct sleep_save_sp {
+        u32 *save_ptr_stash;
+        u32 save_ptr_stash_phys;
+};
+
 extern void cpu_resume(void);
 extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a84060..214d4158089a 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
         struct cpu_context_save cpu_context;    /* cpu context */
         __u32                   syscall;        /* syscall number */
         __u8                    used_cp[16];    /* thread used copro */
-        unsigned long           tp_value;
+        unsigned long           tp_value[2];    /* TLS registers */
 #ifdef CONFIG_CRUNCH
         struct crunch_state     crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index bdf2b8458ec1..46e7cfb3e721 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -204,6 +204,12 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 #endif
 }
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+        tlb_add_flush(tlb, addr);
+}
+
 #define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)   __pmd_free_tlb(tlb, pmdp, addr)
 #define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d141c1d..fdbb9e369745 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -535,8 +535,33 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 }
 #endif
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
-#endif /* CONFIG_MMU */
+#elif defined(CONFIG_SMP)       /* !CONFIG_MMU */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mm_types.h>
+
+static inline void local_flush_tlb_all(void)                                                                    { }
+static inline void local_flush_tlb_mm(struct mm_struct *mm)                                                     { }
+static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)                        { }
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)                                             { }
+static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)    { }
+static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)                         { }
+static inline void local_flush_bp_all(void)                                                                     { }
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_bp_all(void);
+#endif  /* __ASSEMBLY__ */
+
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6c0251..83259b873333 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-        .macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+        .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
         .endm
 
-        .macro set_tls_v6k, tp, tmp1, tmp2
+        .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+        mrc     p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
         mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
-        mov     \tmp1, #0
-        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
+        mcr     p15, 0, \tpuser, c13, c0, 2     @ and the user r/w register
+        str     \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
         .endm
 
-        .macro set_tls_v6, tp, tmp1, tmp2
+        .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
         ldr     \tmp1, =elf_hwcap
         ldr     \tmp1, [\tmp1, #0]
         mov     \tmp2, #0xffff0fff
         tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
-        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
-        movne   \tmp1, #0
-        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+        mrcne   p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
+        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        mcrne   p15, 0, \tpuser, c13, c0, 2     @ set user r/w register
+        strne   \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
         .endm
 
-        .macro set_tls_software, tp, tmp1, tmp2
+        .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
         mov     \tmp1, #0xffff0fff
         str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
         .endm
@@ -31,19 +34,30 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu         1
 #define has_tls_reg             1
-#define set_tls         set_tls_none
+#define switch_tls      switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu         0
 #define has_tls_reg             (elf_hwcap & HWCAP_TLS)
-#define set_tls         set_tls_v6
+#define switch_tls      switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu         0
 #define has_tls_reg             1
-#define set_tls         set_tls_v6k
+#define switch_tls      switch_tls_v6k
 #else
 #define tls_emu         0
 #define has_tls_reg             0
-#define set_tls         set_tls_software
+#define switch_tls      switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tpuser(void)
+{
+        unsigned long reg = 0;
+
+        if (has_tls_reg && !tls_emu)
+                __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
+
+        return reg;
+}
+#endif
 #endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 30cdacb675af..359a7b50b158 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_ARM_XEN_PAGE_H
 #define _ASM_ARM_XEN_PAGE_H
 
-#include <asm/mach/map.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
@@ -88,6 +87,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
         return __set_phys_to_machine(pfn, mfn);
 }
 
-#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
+#define xen_remap(cookie, size) ioremap_cached((cookie), (size));
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index dc8e882a6257..acafb229e2b6 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -16,6 +16,8 @@
 #define DEBUG_LL_PHYS_BASE_RS1          0x1c000000
 #define DEBUG_LL_UART_OFFSET_RS1        0x00090000
 
+#define DEBUG_LL_UART_PHYS_CRX          0xb0090000
+
 #define DEBUG_LL_VIRT_BASE              0xf8000000
 
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
@@ -67,6 +69,14 @@
 
 #include <asm/hardware/debug-pl01x.S>
 
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
+
+                .macro  addruart,rp,tmp,tmp2
+                ldr     \rp, =DEBUG_LL_UART_PHYS_CRX
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
 #else /* CONFIG_DEBUG_LL_UART_NONE */
 
                 .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3688fd15a32d..6d34d080372a 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -25,6 +25,6 @@
 #define HWCAP_IDIVT     (1 << 18)
 #define HWCAP_VFPD32    (1 << 19)       /* set if VFP has 32 regs (not 16) */
 #define HWCAP_IDIV      (HWCAP_IDIVA | HWCAP_IDIVT)
-
+#define HWCAP_LPAE      (1 << 20)
 
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index f4285b5ffb05..fccfbdb03df1 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -38,7 +38,10 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)   += sleep.o suspend.o
-obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
+obj-$(CONFIG_SMP)               += smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP)               += smp_tlb.o
+endif
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)    += arch_timer.o
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index ee68cce6b48e..ded041711beb 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>
 
@@ -145,6 +146,11 @@ int main(void)
 #ifdef MULTI_CACHE
   DEFINE(CACHE_FLUSH_KERN_ALL,  offsetof(struct cpu_cache_fns, flush_kern_all));
 #endif
+#ifdef CONFIG_ARM_CPU_SUSPEND
+  DEFINE(SLEEP_SAVE_SP_SZ,      sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,    offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,    offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   BLANK();
   DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
   DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405befc5..a39cfc2a1f90 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,15 +685,16 @@ ENTRY(__switch_to)
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
-        ldr     r3, [r2, #TI_TP_VALUE]
  ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
  THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
  THUMB( str     sp, [ip], #4               )
  THUMB( str     lr, [ip], #4               )
+        ldr     r4, [r2, #TI_TP_VALUE]
+        ldr     r5, [r2, #TI_TP_VALUE + 4]
 #ifdef CONFIG_CPU_USE_DOMAINS
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-        set_tls r3, r4, r5
+        switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
         ldr     r7, [r2, #TI_TASK]
         ldr     r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 85a72b0809ca..94104bf69719 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -366,6 +366,16 @@ ENTRY(vector_swi)
 #endif
         zero_fp
 
+#ifdef CONFIG_ALIGNMENT_TRAP
+        ldr     ip, __cr_alignment
+        ldr     ip, [ip]
+        mcr     p15, 0, ip, c1, c0              @ update control register
+#endif
+
+        enable_irq
+        ct_user_exit
+        get_thread_info tsk
+
         /*
          * Get the system call number.
          */
@@ -379,9 +389,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
         tst     r8, #PSR_T_BIT
         movne   r10, #0                         @ no thumb OABI emulation
-        ldreq   r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldreq   r10, [lr, #-4]          )       @ get SWI instruction
 #else
-        ldr     r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldr     r10, [lr, #-4]          )       @ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
         rev     r10, r10                        @ little endian instruction
@@ -396,22 +406,13 @@ ENTRY(vector_swi)
         /* Legacy ABI only, possibly thumb mode. */
         tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
         addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
-        ldreq   scno, [lr, #-4]
+ USER(  ldreq   scno, [lr, #-4]         )
 
 #else
         /* Legacy ABI only. */
-        ldr     scno, [lr, #-4]                 @ get SWI instruction
+ USER(  ldr     scno, [lr, #-4]         )       @ get SWI instruction
 #endif
 
-#ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     ip, __cr_alignment
-        ldr     ip, [ip]
-        mcr     p15, 0, ip, c1, c0              @ update control register
-#endif
-        enable_irq
-        ct_user_exit
-
-        get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
 
 #if defined(CONFIG_OABI_COMPAT)
@@ -446,6 +447,21 @@ local_restart:
         eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
         bcs     arm_syscall     
         b       sys_ni_syscall                  @ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+        /*
+         * We failed to handle a fault trying to access the page
+         * containing the swi instruction, but we're not really in a
+         * position to return -EFAULT. Instead, return back to the
+         * instruction and re-enter the user fault handling path trying
+         * to page it in. This will likely result in sending SEGV to the
+         * current task.
+         */
+9001:
+        sub     lr, lr, #4
+        str     lr, [sp, #S_PC]
+        b       ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
 
         /*
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 8812ce88f7a1..75f14cc3e073 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,9 +17,12 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/memory.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
 #include <asm/v7m.h>
+#include <asm/mpu.h>
+#include <asm/page.h>
 
 /*
  * Kernel startup entry point.
@@ -63,12 +66,74 @@ ENTRY(stext)
         movs    r10, r5                         @ invalid processor (r5=0)?
         beq     __error_p                               @ yes, error 'p'
 
-        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+#ifdef CONFIG_ARM_MPU
+        /* Calculate the size of a region covering just the kernel */
+        ldr     r5, =PHYS_OFFSET                @ Region start: PHYS_OFFSET
+        ldr     r6, =(_end)                     @ Cover whole kernel
+        sub     r6, r6, r5                      @ Minimum size of region to map
+        clz     r6, r6                          @ Region size must be 2^N...
+        rsb     r6, r6, #31                     @ ...so round up region size
+        lsl     r6, r6, #MPU_RSR_SZ             @ Put size in right field
+        orr     r6, r6, #(1 << MPU_RSR_EN)      @ Set region enabled bit
+        bl      __setup_mpu
+#endif
+        ldr     r13, =__mmap_switched           @ address to jump to after
+                                                @ initialising sctlr
+        adr     lr, BSYM(1f)                    @ return (PIC) address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
  THUMB( mov     pc, r12                         )
+ 1:     b       __after_proc_init
 ENDPROC(stext)
 
+#ifdef CONFIG_SMP
+        __CPUINIT
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifndef CONFIG_CPU_CP15
+        ldr     r9, =CONFIG_PROCESSOR_ID
+#else
+        mrc     p15, 0, r9, c0, c0              @ get processor id
+#endif
+        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
+        movs    r10, r5                         @ invalid processor?
+        beq     __error_p                       @ yes, error 'p'
+
+        adr     r4, __secondary_data
+        ldmia   r4, {r7, r12}
+
+#ifdef CONFIG_ARM_MPU
+        /* Use MPU region info supplied by __cpu_up */
+        ldr     r6, [r7]                        @ get secondary_data.mpu_szr
+        bl      __setup_mpu                     @ Initialize the MPU
+#endif
+
+        adr     lr, BSYM(__after_proc_init)     @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
+ENDPROC(secondary_startup)
+
+ENTRY(__secondary_switched)
+        ldr     sp, [r7, #8]                    @ set up the stack pointer
+        mov     fp, #0
+        b       secondary_start_kernel
+ENDPROC(__secondary_switched)
+
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* CONFIG_SMP */
+
 /*
  * Set the Control Register and Read the process ID.
  */
@@ -99,10 +164,97 @@ __after_proc_init:
 #endif
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
-
-        b       __mmap_switched                 @ clear the BSS and jump
-                                                @ to start_kernel
+        mov     pc, r13
 ENDPROC(__after_proc_init)
         .ltorg
 
+#ifdef CONFIG_ARM_MPU
+
+
+/* Set which MPU region should be programmed */
+.macro set_region_nr tmp, rgnr
+        mov     \tmp, \rgnr                     @ Use static region numbers
+        mcr     p15, 0, \tmp, c6, c2, 0         @ Write RGNR
+.endm
+
+/* Setup a single MPU region, either D or I side (D-side for unified) */
+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
+        mcr     p15, 0, \bar, c6, c1, (0 + \side)       @ I/DRBAR
+        mcr     p15, 0, \acr, c6, c1, (4 + \side)       @ I/DRACR
+        mcr     p15, 0, \sr, c6, c1, (2 + \side)                @ I/DRSR
+.endm
+
+/*
+ * Setup the MPU and initial MPU Regions. We create the following regions:
+ * Region 0: Use this for probing the MPU details, so leave disabled.
+ * Region 1: Background region - covers the whole of RAM as strongly ordered
+ * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
+ *
+ * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
+*/
+
+ENTRY(__setup_mpu)
+
+        /* Probe for v7 PMSA compliance */
+        mrc     p15, 0, r0, c0, c1, 4           @ Read ID_MMFR0
+        and     r0, r0, #(MMFR0_PMSA)           @ PMSA field
+        teq     r0, #(MMFR0_PMSAv7)             @ PMSA v7
+        bne     __error_p                       @ Fail: ARM_MPU on NOT v7 PMSA
+
+        /* Determine whether the D/I-side memory map is unified. We set the
+         * flags here and continue to use them for the rest of this function */
+        mrc     p15, 0, r0, c0, c0, 4           @ MPUIR
+        ands    r5, r0, #MPUIR_DREGION_SZMASK   @ 0 size d region => No MPU
+        beq     __error_p                       @ Fail: ARM_MPU and no MPU
+        tst     r0, #MPUIR_nU                   @ MPUIR_nU = 0 for unified
+
+        /* Setup second region first to free up r6 */
+        set_region_nr r0, #MPU_RAM_REGION
+        isb
+        /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
+        ldr     r0, =PHYS_OFFSET                @ RAM starts at PHYS_OFFSET
+        ldr     r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ PHYS_OFFSET, shared, enabled
+        beq     1f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
+1:      isb
+
+        /* First/background region */
+        set_region_nr r0, #MPU_BG_REGION
+        isb
+        /* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
+        mov     r0, #0                          @ BG region starts at 0x0
+        ldr     r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
+        mov     r6, #MPU_RSR_ALL_MEM            @ 4GB region, enabled
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ 0x0, BG region, enabled
+        beq     2f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
+2:      isb
+
+        /* Vectors region */
+        set_region_nr r0, #MPU_VECTORS_REGION
+        isb
+        /* Shared, inaccessible to PL0, rw PL1 */
+        mov     r0, #CONFIG_VECTORS_BASE        @ Cover from VECTORS_BASE
+        ldr     r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
+        /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
+        mov     r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ VECTORS_BASE, PL0 NA, enabled
+        beq     3f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
+3:      isb
+
+        /* Enable the MPU */
+        mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
+        bic     r0, r0, #CR_BR                  @ Disable the 'default mem-map'
+        orr     r0, r0, #CR_M                   @ Set SCTRL.M (MPU on)
+        mcr     p15, 0, r0, c1, c0, 0           @ Enable MPU
+        isb
+        mov pc,lr
+ENDPROC(__setup_mpu)
+#endif
 #include "head-common.S"
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553fe213..45e8935cae4e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
         pgtbl   r4, r8                          @ page table address
@@ -331,6 +331,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
         sub     r4, r4, #0x1000         @ point to the PGD table
+        mov     r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
         mov     pc, lr
 ENDPROC(__create_page_tables)
@@ -408,7 +409,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -427,10 +428,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
         bic     r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-        mov     r5, #0
-        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4ccfa56..4910232c4833 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -153,6 +153,13 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
         mrc     p15, 4, r7, c14, c1, 0  @ CNTHCTL
         orr     r7, r7, #3              @ PL1PCEN | PL1PCTEN
         mcr     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+        mov     r7, #0
+        mcrr    p15, 4, r7, r7, c14     @ CNTVOFF
+
+        @ Disable virtual timer in case it was counting
+        mrc     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
+        bic     r7, #1                  @ Clear ENABLE
+        mcr     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
 1:
 #endif
 
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 8c3094d0f7b7..d9f5cd4e533f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -569,6 +569,7 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                 return;
         }
 
+        perf_callchain_store(entry, regs->ARM_pc);
         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 6e8931ccf13e..7f1efcd4a6e9 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -374,7 +375,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         clear_ptrace_hw_breakpoint(p);
 
         if (clone_flags & CLONE_SETTLS)
-                thread->tp_value = childregs->ARM_r3;
+                thread->tp_value[0] = childregs->ARM_r3;
+        thread->tp_value[1] = get_tpuser();
 
         thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
index 23a11424c568..219f1d73572a 100644
--- a/arch/arm/kernel/psci_smp.c
+++ b/arch/arm/kernel/psci_smp.c
@@ -68,8 +68,6 @@ void __ref psci_cpu_die(unsigned int cpu)
        /* We should never return */
        panic("psci: cpu %d failed to shutdown\n", cpu);
 }
-#else
-#define psci_cpu_die NULL
 #endif
 
 bool __init psci_smp_available(void)
@@ -80,5 +78,7 @@ bool __init psci_smp_available(void)
 
 struct smp_operations __initdata psci_smp_ops = {
         .smp_boot_secondary     = psci_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = psci_cpu_die,
+#endif
 };
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeffd9f6d..2bc1514d6dbe 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
                 case PTRACE_GET_THREAD_AREA:
-                        ret = put_user(task_thread_info(child)->tp_value,
+                        ret = put_user(task_thread_info(child)->tp_value[0],
                                        datap);
                         break;
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1c8278de6c46..9b653278c9e8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -367,7 +367,7 @@ void __init early_print(const char *str, ...)
 
 static void __init cpuid_init_hwcaps(void)
 {
-        unsigned int divide_instrs;
+        unsigned int divide_instrs, vmsa;
 
         if (cpu_architecture() < CPU_ARCH_ARMv7)
                 return;
@@ -380,6 +380,11 @@ static void __init cpuid_init_hwcaps(void)
         case 1:
                 elf_hwcap |= HWCAP_IDIVT;
         }
+
+        /* LPAE implies atomic ldrd/strd instructions */
+        vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+        if (vmsa >= 5)
+                elf_hwcap |= HWCAP_LPAE;
 }
 
 static void __init feat_v6_fixup(void)
@@ -470,9 +475,82 @@ void __init smp_setup_processor_id(void)
         for (i = 1; i < nr_cpu_ids; ++i)
                 cpu_logical_map(i) = i == cpu ? 0 : i;
 
+        /*
+         * clear __my_cpu_offset on boot CPU to avoid hang caused by
+         * using percpu variable early, for example, lockdep will
+         * access percpu variable inside lock_release
+         */
+        set_my_cpu_offset(0);
+
         printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
 }
 
+struct mpidr_hash mpidr_hash;
+#ifdef CONFIG_SMP
+/**
+ * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
+ *                        level in order to build a linear index from an
+ *                        MPIDR value. Resulting algorithm is a collision
+ *                        free hash carried out through shifting and ORing
+ */
+static void __init smp_build_mpidr_hash(void)
+{
+        u32 i, affinity;
+        u32 fs[3], bits[3], ls, mask = 0;
+        /*
+         * Pre-scan the list of MPIDRS and filter out bits that do
+         * not contribute to affinity levels, ie they never toggle.
+         */
+        for_each_possible_cpu(i)
+                mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
+        pr_debug("mask of set bits 0x%x\n", mask);
+        /*
+         * Find and stash the last and first bit set at all affinity levels to
+         * check how many bits are required to represent them.
+         */
+        for (i = 0; i < 3; i++) {
+                affinity = MPIDR_AFFINITY_LEVEL(mask, i);
+                /*
+                 * Find the MSB bit and LSB bits position
+                 * to determine how many bits are required
+                 * to express the affinity level.
+                 */
+                ls = fls(affinity);
+                fs[i] = affinity ? ffs(affinity) - 1 : 0;
+                bits[i] = ls - fs[i];
+        }
+        /*
+         * An index can be created from the MPIDR by isolating the
+         * significant bits at each affinity level and by shifting
+         * them in order to compress the 24 bits values space to a
+         * compressed set of values. This is equivalent to hashing
+         * the MPIDR through shifting and ORing. It is a collision free
+         * hash though not minimal since some levels might contain a number
+         * of CPUs that is not an exact power of 2 and their bit
+         * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
+         */
+        mpidr_hash.shift_aff[0] = fs[0];
+        mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
+        mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
+                                                (bits[1] + bits[0]);
+        mpidr_hash.mask = mask;
+        mpidr_hash.bits = bits[2] + bits[1] + bits[0];
+        pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
+                                mpidr_hash.shift_aff[0],
+                                mpidr_hash.shift_aff[1],
+                                mpidr_hash.shift_aff[2],
+                                mpidr_hash.mask,
+                                mpidr_hash.bits);
+        /*
+         * 4x is an arbitrary value used to warn on a hash table much bigger
+         * than expected on most systems.
+         */
+        if (mpidr_hash_size() > 4 * num_possible_cpus())
+                pr_warn("Large number of MPIDR hash buckets detected\n");
+        sync_cache_w(&mpidr_hash);
+}
+#endif
+
 static void __init setup_processor(void)
 {
         struct proc_info_list *list;
@@ -820,6 +898,7 @@ void __init setup_arch(char **cmdline_p)
                                 smp_set_ops(mdesc->smp);
                 }
                 smp_init_cpus();
+                smp_build_mpidr_hash();
         }
 #endif
 
@@ -892,6 +971,7 @@ static const char *hwcap_str[] = {
         "vfpv4",
         "idiva",
         "idivt",
+        "lpae",
         NULL
 };
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 296786bdbb73..1c16c35c271a 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -392,14 +392,19 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
                 if (ksig->ka.sa.sa_flags & SA_SIGINFO)
                         idx += 3;
 
+                /*
+                 * Put the sigreturn code on the stack no matter which return
+                 * mechanism we use in order to remain ABI compliant
+                 */
                 if (__put_user(sigreturn_codes[idx],   rc) ||
                     __put_user(sigreturn_codes[idx+1], rc+1))
                         return 1;
 
-                if (cpsr & MODE32_BIT) {
+                if ((cpsr & MODE32_BIT) && !IS_ENABLED(CONFIG_ARM_MPU)) {
                         /*
                          * 32-bit code can use the new high-page
-                         * signal return code support.
+                         * signal return code support except when the MPU has
+                         * protected the vectors page from PL0
                          */
                         retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
                 } else {
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf33415c..db1536b8b30b 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -7,6 +7,49 @@
         .text
 
 /*
+ * Implementation of MPIDR hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @mpidr: register containing MPIDR value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
+ *      u32 aff0, aff1, aff2;
+ *      u32 mpidr_masked = mpidr & mask;
+ *      aff0 = mpidr_masked & 0xff;
+ *      aff1 = mpidr_masked & 0xff00;
+ *      aff2 = mpidr_masked & 0xff0000;
+ *      dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
+ *}
+ * Input registers: rs0, rs1, rs2, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
+ */
+        .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
+        and     \mpidr, \mpidr, \mask                   @ mask out MPIDR bits
+        and     \dst, \mpidr, #0xff                     @ mask=aff0
+ ARM(   mov     \dst, \dst, lsr \rs0            )       @ dst=aff0>>rs0
+ THUMB( lsr     \dst, \dst, \rs0                )
+        and     \mask, \mpidr, #0xff00                  @ mask = aff1
+ ARM(   orr     \dst, \dst, \mask, lsr \rs1     )       @ dst|=(aff1>>rs1)
+ THUMB( lsr     \mask, \mask, \rs1              )
+ THUMB( orr     \dst, \dst, \mask               )
+        and     \mask, \mpidr, #0xff0000                @ mask = aff2
+ ARM(   orr     \dst, \dst, \mask, lsr \rs2     )       @ dst|=(aff2>>rs2)
+ THUMB( lsr     \mask, \mask, \rs2              )
+ THUMB( orr     \dst, \dst, \mask               )
+        .endm
+
+/*
  * Save CPU state for a suspend.  This saves the CPU general purpose
  * registers, and allocates space on the kernel stack to save the CPU
  * specific registers and some other data for resume.
@@ -29,12 +72,18 @@ ENTRY(__cpu_suspend)
         mov     r1, r4                  @ size of save block
         mov     r2, r5                  @ virtual SP
         ldr     r3, =sleep_save_sp
-#ifdef CONFIG_SMP
-        ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-        ALT_UP(mov lr, #0)
-        and     lr, lr, #15
+        ldr     r3, [r3, #SLEEP_SAVE_SP_VIRT]
+        ALT_SMP(mrc p15, 0, r9, c0, c0, 5)
+        ALT_UP_B(1f)
+        ldr     r8, =mpidr_hash
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r8, {r4-r7}     @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts
+        compute_mpidr_hash      lr, r5, r6, r7, r9, r4
         add     r3, r3, lr, lsl #2
-#endif
+1:
         bl      __cpu_suspend_save
         adr     lr, BSYM(cpu_suspend_abort)
         ldmfd   sp!, {r0, pc}           @ call suspend fn
@@ -81,15 +130,23 @@ ENDPROC(cpu_resume_after_mmu)
         .data
         .align
 ENTRY(cpu_resume)
-#ifdef CONFIG_SMP
-        adr     r0, sleep_save_sp
-        ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
-        ALT_UP(mov r1, #0)
-        and     r1, r1, #15
-        ldr     r0, [r0, r1, lsl #2]    @ stack phys addr
-#else
-        ldr     r0, sleep_save_sp       @ stack phys addr
-#endif
+        mov     r1, #0
+        ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
+        ALT_UP_B(1f)
+        adr     r2, mpidr_hash_ptr
+        ldr     r3, [r2]
+        add     r2, r2, r3              @ r2 = struct mpidr_hash phys address
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r2, { r3-r6 }   @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
+        compute_mpidr_hash      r1, r4, r5, r6, r0, r3
+1:
+        adr     r0, _sleep_save_sp
+        ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
+        ldr     r0, [r0, r1, lsl #2]
+
         setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
         @ load phys pgd, stack, resume fn
   ARM(  ldmia   r0!, {r1, sp, pc}       )
@@ -98,7 +155,11 @@ THUMB(	mov	sp, r2			)
 THUMB(  bx      r3                      )
 ENDPROC(cpu_resume)
 
-sleep_save_sp:
-        .rept   CONFIG_NR_CPUS
-        .long   0                               @ preserve stack phys ptr here
-        .endr
+        .align 2
+mpidr_hash_ptr:
+        .long   mpidr_hash - .                  @ mpidr_hash struct offset
+
+        .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+_sleep_save_sp:
+        .space  SLEEP_SAVE_SP_SZ                @ struct sleep_save_sp
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 5919eb451bb9..c5fb5469054b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -45,6 +45,7 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
+#include <asm/mpu.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -78,6 +79,13 @@ void __init smp_set_ops(struct smp_operations *ops)
                 smp_ops = *ops;
 };
 
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+        phys_addr_t pgdir = virt_to_phys(pgd);
+        BUG_ON(pgdir & ARCH_PGD_MASK);
+        return pgdir >> ARCH_PGD_SHIFT;
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         int ret;
@@ -87,8 +95,14 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
          * its stack and the page tables.
          */
         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-        secondary_data.pgdir = virt_to_phys(idmap_pgd);
-        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+#ifdef CONFIG_ARM_MPU
+        secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+#endif
+
+#ifdef CONFIG_MMU
+        secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+        secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
+#endif
         __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
         outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
@@ -112,9 +126,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
                 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
         }
 
-        secondary_data.stack = NULL;
-        secondary_data.pgdir = 0;
 
+        memset(&secondary_data, 0, sizeof(secondary_data));
         return ret;
 }
 
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 9a52a07aa40e..a98b62dca2fa 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -103,7 +103,7 @@ static void broadcast_tlb_a15_erratum(void)
 
 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 {
-        int cpu, this_cpu;
+        int this_cpu;
         cpumask_t mask = { CPU_BITS_NONE };
 
         if (!erratum_a15_798181())
@@ -111,21 +111,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 
         dummy_flush_tlb_a15_erratum();
         this_cpu = get_cpu();
-        for_each_online_cpu(cpu) {
-                if (cpu == this_cpu)
-                        continue;
-                /*
-                 * We only need to send an IPI if the other CPUs are running
-                 * the same ASID as the one being invalidated. There is no
-                 * need for locking around the active_asids check since the
-                 * switch_mm() function has at least one dmb() (as required by
-                 * this workaround) in case a context switch happens on
-                 * another CPU after the condition below.
-                 */
-                if (atomic64_read(&mm->context.id) ==
-                    atomic64_read(&per_cpu(active_asids, cpu)))
-                        cpumask_set_cpu(cpu, &mask);
-        }
+        a15_erratum_get_cpumask(this_cpu, mm, &mask);
         smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
         put_cpu();
 }
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index c59c97ea8268..41cf3cbf756d 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -1,15 +1,54 @@
 #include <linux/init.h>
+#include <linux/slab.h>
 
+#include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
 
+#ifdef CONFIG_MMU
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+
+        if (!idmap_pgd)
+                return -EINVAL;
+
+        /*
+         * Provide a temporary page table with an identity mapping for
+         * the MMU-enable code, required for resuming.  On successful
+         * resume (indicated by a zero return code), we need to switch
+         * back to the correct page tables.
+         */
+        ret = __cpu_suspend(arg, fn);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                local_flush_bp_all();
+                local_flush_tlb_all();
+        }
+
+        return ret;
+}
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        return __cpu_suspend(arg, fn);
+}
+#define idmap_pgd       NULL
+#endif
+
 /*
  * This is called by __cpu_suspend() to save the state, and do whatever
  * flushing is required to ensure that when the CPU goes to sleep we have
@@ -47,30 +86,19 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
                           virt_to_phys(save_ptr) + sizeof(*save_ptr));
 }
 
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        struct mm_struct *mm = current->active_mm;
-        int ret;
-
-        if (!idmap_pgd)
-                return -EINVAL;
+extern struct sleep_save_sp sleep_save_sp;
 
-        /*
-         * Provide a temporary page table with an identity mapping for
-         * the MMU-enable code, required for resuming.  On successful
-         * resume (indicated by a zero return code), we need to switch
-         * back to the correct page tables.
-         */
-        ret = __cpu_suspend(arg, fn);
-        if (ret == 0) {
-                cpu_switch_mm(mm->pgd, mm);
-                local_flush_bp_all();
-                local_flush_tlb_all();
-        }
+static int cpu_suspend_alloc_sp(void)
+{
+        void *ctx_ptr;
+        /* ctx_ptr is an array of physical addresses */
+        ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL);
 
-        return ret;
+        if (WARN_ON(!ctx_ptr))
+                return -ENOMEM;
+        sleep_save_sp.save_ptr_stash = ctx_ptr;
+        sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+        sync_cache_w(&sleep_save_sp);
+        return 0;
 }
+early_initcall(cpu_suspend_alloc_sp);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 486e12a0f26a..cab094c234ee 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -581,7 +581,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
                 return regs->ARM_r0;
 
         case NR(set_tls):
-                thread->tp_value = regs->ARM_r0;
+                thread->tp_value[0] = regs->ARM_r0;
                 if (tls_emu)
                         return 0;
                 if (has_tls_reg) {
@@ -699,7 +699,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
         int reg = (instr >> 12) & 15;
         if (reg == 15)
                 return 1;
-        regs->uregs[reg] = current_thread_info()->tp_value;
+        regs->uregs[reg] = current_thread_info()->tp_value[0];
         regs->ARM_pc += 4;
         return 0;
 }
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
index 370e1a8af6ac..ebf5015508b5 100644
--- a/arch/arm/kvm/Kconfig
+++ b/arch/arm/kvm/Kconfig
@@ -41,9 +41,9 @@ config KVM_ARM_HOST
           Provides host support for ARM processors.
 
 config KVM_ARM_MAX_VCPUS
-        int "Number maximum supported virtual CPUs per VM" if KVM_ARM_HOST
-        default 4 if KVM_ARM_HOST
-        default 0
+        int "Number maximum supported virtual CPUs per VM"
+        depends on KVM_ARM_HOST
+        default 4
         help
           Static number of max supported virtual CPUs per VM.
 
@@ -67,6 +67,4 @@ config KVM_ARM_TIMER
         ---help---
           Adds support for the Architected Timers in virtual machines
 
-source drivers/virtio/Kconfig
-
 endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed83d16f..d99bee4950e5 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
deleted file mode 100644
index c55b6089e923..000000000000
--- a/arch/arm/kvm/arch_timer.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/cpu.h>
-#include <linux/of_irq.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-
-#include <clocksource/arm_arch_timer.h>
-#include <asm/arch_timer.h>
-
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
-
-static struct timecounter *timecounter;
-static struct workqueue_struct *wqueue;
-static struct kvm_irq_level timer_irq = {
-        .level  = 1,
-};
-
-static cycle_t kvm_phys_timer_read(void)
-{
-        return timecounter->cc->read(timecounter->cc);
-}
-
-static bool timer_is_armed(struct arch_timer_cpu *timer)
-{
-        return timer->armed;
-}
-
-/* timer_arm: as in "arm the timer", not as in ARM the company */
-static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
-{
-        timer->armed = true;
-        hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
-                      HRTIMER_MODE_ABS);
-}
-
-static void timer_disarm(struct arch_timer_cpu *timer)
-{
-        if (timer_is_armed(timer)) {
-                hrtimer_cancel(&timer->timer);
-                cancel_work_sync(&timer->expired);
-                timer->armed = false;
-        }
-}
-
-static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        timer->cntv_ctl |= ARCH_TIMER_CTRL_IT_MASK;
-        kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
-                            vcpu->arch.timer_cpu.irq->irq,
-                            vcpu->arch.timer_cpu.irq->level);
-}
-
-static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
-{
-        struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
-
-        /*
-         * We disable the timer in the world switch and let it be
-         * handled by kvm_timer_sync_hwstate(). Getting a timer
-         * interrupt at this point is a sure sign of some major
-         * breakage.
-         */
-        pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
-        return IRQ_HANDLED;
-}
-
-static void kvm_timer_inject_irq_work(struct work_struct *work)
-{
-        struct kvm_vcpu *vcpu;
-
-        vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
-        vcpu->arch.timer_cpu.armed = false;
-        kvm_timer_inject_irq(vcpu);
-}
-
-static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
-{
-        struct arch_timer_cpu *timer;
-        timer = container_of(hrt, struct arch_timer_cpu, timer);
-        queue_work(wqueue, &timer->expired);
-        return HRTIMER_NORESTART;
-}
-
-/**
- * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
- * @vcpu: The vcpu pointer
- *
- * Disarm any pending soft timers, since the world-switch code will write the
- * virtual timer state back to the physical CPU.
- */
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        /*
-         * We're about to run this vcpu again, so there is no need to
-         * keep the background timer running, as we're about to
-         * populate the CPU timer again.
-         */
-        timer_disarm(timer);
-}
-
-/**
- * kvm_timer_sync_hwstate - sync timer state from cpu
- * @vcpu: The vcpu pointer
- *
- * Check if the virtual timer was armed and either schedule a corresponding
- * soft timer or inject directly if already expired.
- */
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        cycle_t cval, now;
-        u64 ns;
-
-        if ((timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) ||
-                !(timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE))
-                return;
-
-        cval = timer->cntv_cval;
-        now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
-
-        BUG_ON(timer_is_armed(timer));
-
-        if (cval <= now) {
-                /*
-                 * Timer has already expired while we were not
-                 * looking. Inject the interrupt and carry on.
-                 */
-                kvm_timer_inject_irq(vcpu);
-                return;
-        }
-
-        ns = cyclecounter_cyc2ns(timecounter->cc, cval - now);
-        timer_arm(timer, ns);
-}
-
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
-        hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-        timer->timer.function = kvm_timer_expire;
-        timer->irq = &timer_irq;
-}
-
-static void kvm_timer_init_interrupt(void *info)
-{
-        enable_percpu_irq(timer_irq.irq, 0);
-}
-
-
-static int kvm_timer_cpu_notify(struct notifier_block *self,
-                                unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                kvm_timer_init_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(timer_irq.irq);
-                break;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block kvm_timer_cpu_nb = {
-        .notifier_call = kvm_timer_cpu_notify,
-};
-
-static const struct of_device_id arch_timer_of_match[] = {
-        { .compatible   = "arm,armv7-timer",    },
-        {},
-};
-
-int kvm_timer_hyp_init(void)
-{
-        struct device_node *np;
-        unsigned int ppi;
-        int err;
-
-        timecounter = arch_timer_get_timecounter();
-        if (!timecounter)
-                return -ENODEV;
-
-        np = of_find_matching_node(NULL, arch_timer_of_match);
-        if (!np) {
-                kvm_err("kvm_arch_timer: can't find DT node\n");
-                return -ENODEV;
-        }
-
-        ppi = irq_of_parse_and_map(np, 2);
-        if (!ppi) {
-                kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
-                err = -EINVAL;
-                goto out;
-        }
-
-        err = request_percpu_irq(ppi, kvm_arch_timer_handler,
-                                 "kvm guest timer", kvm_get_running_vcpus());
-        if (err) {
-                kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
-                        ppi, err);
-                goto out;
-        }
-
-        timer_irq.irq = ppi;
-
-        err = register_cpu_notifier(&kvm_timer_cpu_nb);
-        if (err) {
-                kvm_err("Cannot register timer CPU notifier\n");
-                goto out_free;
-        }
-
-        wqueue = create_singlethread_workqueue("kvm_arch_timer");
-        if (!wqueue) {
-                err = -ENOMEM;
-                goto out_free;
-        }
-
-        kvm_info("%s IRQ%d\n", np->name, ppi);
-        on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
-
-        goto out;
-out_free:
-        free_percpu_irq(ppi, kvm_get_running_vcpus());
-out:
-        of_node_put(np);
-        return err;
-}
-
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        timer_disarm(timer);
-}
-
-int kvm_timer_init(struct kvm *kvm)
-{
-        if (timecounter && wqueue) {
-                kvm->arch.timer.cntvoff = kvm_phys_timer_read();
-                kvm->arch.timer.enabled = 1;
-        }
-
-        return 0;
-}
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index ef1703b9587b..741f66a2edbd 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -800,8 +800,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 static void cpu_init_hyp_mode(void *dummy)
 {
-        unsigned long long boot_pgd_ptr;
-        unsigned long long pgd_ptr;
+        phys_addr_t boot_pgd_ptr;
+        phys_addr_t pgd_ptr;
         unsigned long hyp_stack_ptr;
         unsigned long stack_page;
         unsigned long vector_ptr;
@@ -809,8 +809,8 @@ static void cpu_init_hyp_mode(void *dummy)
         /* Switch from the HYP stub to our own HYP init vector */
         __hyp_set_vectors(kvm_get_idmap_vector());
 
-        boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
-        pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+        boot_pgd_ptr = kvm_mmu_get_boot_httbr();
+        pgd_ptr = kvm_mmu_get_httbr();
         stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
         hyp_stack_ptr = stack_page + PAGE_SIZE;
         vector_ptr = (unsigned long)__kvm_hyp_vector;
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 8eea97be1ed5..4a5199070430 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -180,6 +180,10 @@ static const struct coproc_reg cp15_regs[] = {
                         NULL, reset_unknown, c6_DFAR },
         { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
                         NULL, reset_unknown, c6_IFAR },
+
+        /* PAR swapped by interrupt.S */
+        { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
+
         /*
          * DC{C,I,CI}SW operations:
          */
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 3d74a0be47db..df4c82d47ad7 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -52,9 +52,6 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        if (kvm_psci_call(vcpu))
-                return 1;
-
         kvm_inject_undefined(vcpu);
         return 1;
 }
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f7793df62f58..16cd4ba5d7fd 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -49,6 +49,7 @@ __kvm_hyp_code_start:
 ENTRY(__kvm_tlb_flush_vmid_ipa)
         push    {r2, r3}
 
+        dsb     ishst
         add     r0, r0, #KVM_VTTBR
         ldrd    r2, r3, [r0]
         mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
@@ -291,6 +292,7 @@ THUMB(	orr	r2, r2, #PSR_T_BIT	)
         ldr     r2, =BSYM(panic)
         msr     ELR_hyp, r2
         ldr     r0, =\panic_str
+        clrex                           @ Clear exclusive monitor
         eret
 .endm
 
@@ -414,6 +416,10 @@ guest_trap:
         mrcne   p15, 4, r2, c6, c0, 4   @ HPFAR
         bne     3f
 
+        /* Preserve PAR */
+        mrrc    p15, 0, r0, r1, c7      @ PAR
+        push    {r0, r1}
+
         /* Resolve IPA using the xFAR */
         mcr     p15, 0, r2, c7, c8, 0   @ ATS1CPR
         isb
@@ -424,13 +430,20 @@ guest_trap:
         lsl     r2, r2, #4
         orr     r2, r2, r1, lsl #24
 
+        /* Restore PAR */
+        pop     {r0, r1}
+        mcrr    p15, 0, r0, r1, c7      @ PAR
+
 3:      load_vcpu                       @ Load VCPU pointer to r0
         str     r2, [r0, #VCPU_HPFAR]
 
 1:      mov     r1, #ARM_EXCEPTION_HVC
         b       __kvm_vcpu_return
 
-4:      pop     {r0, r1, r2}            @ Failed translation, return to guest
+4:      pop     {r0, r1}                @ Failed translation, return to guest
+        mcrr    p15, 0, r0, r1, c7      @ PAR
+        clrex
+        pop     {r0, r1, r2}
         eret
 
 /*
@@ -456,6 +469,7 @@ switch_to_guest_vfp:
 
         pop     {r3-r7}
         pop     {r0-r2}
+        clrex
         eret
 #endif
 
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 3c8f2f0b4c5e..6f18695a09cb 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -302,11 +302,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
         .endif
 
         mrc     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mrrc    p15, 0, r4, r5, c7      @ PAR
 
         .if \store_to_vcpu == 0
-        push    {r2}
+        push    {r2,r4-r5}
         .else
         str     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        strd    r4, r5, [r12]
         .endif
 .endm
 
@@ -319,12 +322,15 @@ vcpu	.req	r0		@ vcpu pointer always in r0
  */
 .macro write_cp15_state read_from_vcpu
         .if \read_from_vcpu == 0
-        pop     {r2}
+        pop     {r2,r4-r5}
         .else
         ldr     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        ldrd    r4, r5, [r12]
         .endif
 
         mcr     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mcrr    p15, 0, r4, r5, c7      @ PAR
 
         .if \read_from_vcpu == 0
         pop     {r2-r12}
@@ -497,6 +503,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
         add     r5, vcpu, r4
         strd    r2, r3, [r5]
 
+        @ Ensure host CNTVCT == CNTPCT
+        mov     r2, #0
+        mcrr    p15, 4, r2, r2, c14     @ CNTVOFF
+
 1:
 #endif
         @ Allow physical timer/counter access for the host
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 72a12f2171b2..b8e06b7a2833 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
         sign_extend = kvm_vcpu_dabt_issext(vcpu);
         rt = kvm_vcpu_dabt_get_rd(vcpu);
 
-        if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
-                /* IO memory trying to read/write pc */
-                kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
-                return 1;
-        }
-
         mmio->is_write = is_write;
         mmio->phys_addr = fault_ipa;
         mmio->len = len;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 84ba67b982c0..ca6bea4859b4 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
         if (!pgd)
                 return -ENOMEM;
 
-        /* stage-2 pgd must be aligned to its size */
-        VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
-
         memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
         kvm_clean_pgd(pgd);
         kvm->arch.pgd = pgd;
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 7ee5bb7a3667..86a693a02ba3 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -75,7 +75,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
  * kvm_psci_call - handle PSCI call if r0 value is in range
  * @vcpu: Pointer to the VCPU struct
  *
- * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * Handle PSCI calls from guests through traps from HVC instructions.
  * The calling convention is similar to SMC calls to the secure world where
  * the function number is placed in r0 and this function returns true if the
  * function number specified in r0 is withing the PSCI range, and false
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index b80256b554cd..b7840e7aa452 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -27,6 +27,8 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_coproc.h>
 
+#include <kvm/arm_arch_timer.h>
+
 /******************************************************************************
  * Cortex-A15 Reset Values
  */
@@ -37,6 +39,11 @@ static struct kvm_regs a15_regs_reset = {
         .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
 };
 
+static const struct kvm_irq_level a15_vtimer_irq = {
+        .irq = 27,
+        .level = 1,
+};
+
 
 /*******************************************************************************
  * Exported reset function
@@ -52,6 +59,7 @@ static struct kvm_regs a15_regs_reset = {
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
         struct kvm_regs *cpu_reset;
+        const struct kvm_irq_level *cpu_vtimer_irq;
 
         switch (vcpu->arch.target) {
         case KVM_ARM_TARGET_CORTEX_A15:
@@ -59,6 +67,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
                         return -EINVAL;
                 cpu_reset = &a15_regs_reset;
                 vcpu->arch.midr = read_cpuid_id();
+                cpu_vtimer_irq = &a15_vtimer_irq;
                 break;
         default:
                 return -ENODEV;
@@ -70,5 +79,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
         /* Reset CP15 registers */
         kvm_reset_coprocs(vcpu);
 
+        /* Reset arch_timer context */
+        kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+
         return 0;
 }
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
deleted file mode 100644
index 17c5ac7d10ed..000000000000
--- a/arch/arm/kvm/vgic.c
+++ /dev/null
@@ -1,1499 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/cpu.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <linux/irqchip/arm-gic.h>
-
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_mmu.h>
-
-/*
- * How the whole thing works (courtesy of Christoffer Dall):
- *
- * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
- *   something is pending
- * - VGIC pending interrupts are stored on the vgic.irq_state vgic
- *   bitmap (this bitmap is updated by both user land ioctls and guest
- *   mmio ops, and other in-kernel peripherals such as the
- *   arch. timers) and indicate the 'wire' state.
- * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
- *   recalculated
- * - To calculate the oracle, we need info for each cpu from
- *   compute_pending_for_cpu, which considers:
- *   - PPI: dist->irq_state & dist->irq_enable
- *   - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
- *   - irq_spi_target is a 'formatted' version of the GICD_ICFGR
- *     registers, stored on each vcpu. We only keep one bit of
- *     information per interrupt, making sure that only one vcpu can
- *     accept the interrupt.
- * - The same is true when injecting an interrupt, except that we only
- *   consider a single interrupt at a time. The irq_spi_cpu array
- *   contains the target CPU for each SPI.
- *
- * The handling of level interrupts adds some extra complexity. We
- * need to track when the interrupt has been EOIed, so we can sample
- * the 'line' again. This is achieved as such:
- *
- * - When a level interrupt is moved onto a vcpu, the corresponding
- *   bit in irq_active is set. As long as this bit is set, the line
- *   will be ignored for further interrupts. The interrupt is injected
- *   into the vcpu with the GICH_LR_EOI bit set (generate a
- *   maintenance interrupt on EOI).
- * - When the interrupt is EOIed, the maintenance interrupt fires,
- *   and clears the corresponding bit in irq_active. This allow the
- *   interrupt line to be sampled again.
- */
-
-#define VGIC_ADDR_UNDEF         (-1)
-#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
-
-/* Physical address of vgic virtual cpu interface */
-static phys_addr_t vgic_vcpu_base;
-
-/* Virtual control interface base address */
-static void __iomem *vgic_vctrl_base;
-
-static struct device_node *vgic_node;
-
-#define ACCESS_READ_VALUE       (1 << 0)
-#define ACCESS_READ_RAZ         (0 << 0)
-#define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
-#define ACCESS_WRITE_IGNORED    (0 << 1)
-#define ACCESS_WRITE_SETBIT     (1 << 1)
-#define ACCESS_WRITE_CLEARBIT   (2 << 1)
-#define ACCESS_WRITE_VALUE      (3 << 1)
-#define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
-
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
-static void vgic_update_state(struct kvm *kvm);
-static void vgic_kick_vcpus(struct kvm *kvm);
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
-static u32 vgic_nr_lr;
-
-static unsigned int vgic_maint_irq;
-
-static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
-                                int cpuid, u32 offset)
-{
-        offset >>= 2;
-        if (!offset)
-                return x->percpu[cpuid].reg;
-        else
-                return x->shared.reg + offset - 1;
-}
-
-static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
-                                   int cpuid, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                return test_bit(irq, x->percpu[cpuid].reg_ul);
-
-        return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
-}
-
-static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
-                                    int irq, int val)
-{
-        unsigned long *reg;
-
-        if (irq < VGIC_NR_PRIVATE_IRQS) {
-                reg = x->percpu[cpuid].reg_ul;
-        } else {
-                reg =  x->shared.reg_ul;
-                irq -= VGIC_NR_PRIVATE_IRQS;
-        }
-
-        if (val)
-                set_bit(irq, reg);
-        else
-                clear_bit(irq, reg);
-}
-
-static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
-{
-        if (unlikely(cpuid >= VGIC_MAX_CPUS))
-                return NULL;
-        return x->percpu[cpuid].reg_ul;
-}
-
-static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
-{
-        return x->shared.reg_ul;
-}
-
-static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
-{
-        offset >>= 2;
-        BUG_ON(offset > (VGIC_NR_IRQS / 4));
-        if (offset < 4)
-                return x->percpu[cpuid] + offset;
-        else
-                return x->shared + offset - 8;
-}
-
-#define VGIC_CFG_LEVEL  0
-#define VGIC_CFG_EDGE   1
-
-static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int irq_val;
-
-        irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
-        return irq_val == VGIC_CFG_EDGE;
-}
-
-static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
-}
-
-static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
-}
-
-static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
-}
-
-static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
-}
-
-static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
-}
-
-static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
-}
-
-static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
-}
-
-static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                set_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                        vcpu->arch.vgic_cpu.pending_shared);
-}
-
-static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                          vcpu->arch.vgic_cpu.pending_shared);
-}
-
-static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
-{
-        return *((u32 *)mmio->data) & mask;
-}
-
-static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
-{
-        *((u32 *)mmio->data) = value & mask;
-}
-
-/**
- * vgic_reg_access - access vgic register
- * @mmio:   pointer to the data describing the mmio access
- * @reg:    pointer to the virtual backing of vgic distributor data
- * @offset: least significant 2 bits used for word offset
- * @mode:   ACCESS_ mode (see defines above)
- *
- * Helper to make vgic register access easier using one of the access
- * modes defined for vgic register access
- * (read,raz,write-ignored,setbit,clearbit,write)
- */
-static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
-                            phys_addr_t offset, int mode)
-{
-        int word_offset = (offset & 3) * 8;
-        u32 mask = (1UL << (mmio->len * 8)) - 1;
-        u32 regval;
-
-        /*
-         * Any alignment fault should have been delivered to the guest
-         * directly (ARM ARM B3.12.7 "Prioritization of aborts").
-         */
-
-        if (reg) {
-                regval = *reg;
-        } else {
-                BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
-                regval = 0;
-        }
-
-        if (mmio->is_write) {
-                u32 data = mmio_data_read(mmio, mask) << word_offset;
-                switch (ACCESS_WRITE_MASK(mode)) {
-                case ACCESS_WRITE_IGNORED:
-                        return;
-
-                case ACCESS_WRITE_SETBIT:
-                        regval |= data;
-                        break;
-
-                case ACCESS_WRITE_CLEARBIT:
-                        regval &= ~data;
-                        break;
-
-                case ACCESS_WRITE_VALUE:
-                        regval = (regval & ~(mask << word_offset)) | data;
-                        break;
-                }
-                *reg = regval;
-        } else {
-                switch (ACCESS_READ_MASK(mode)) {
-                case ACCESS_READ_RAZ:
-                        regval = 0;
-                        /* fall through */
-
-                case ACCESS_READ_VALUE:
-                        mmio_data_write(mmio, mask, regval >> word_offset);
-                }
-        }
-}
-
-static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
-                             struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        u32 word_offset = offset & 3;
-
-        switch (offset & ~3) {
-        case 0:                 /* CTLR */
-                reg = vcpu->kvm->arch.vgic.enabled;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-                if (mmio->is_write) {
-                        vcpu->kvm->arch.vgic.enabled = reg & 1;
-                        vgic_update_state(vcpu->kvm);
-                        return true;
-                }
-                break;
-
-        case 4:                 /* TYPER */
-                reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
-                reg |= (VGIC_NR_IRQS >> 5) - 1;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-
-        case 8:                 /* IIDR */
-                reg = 0x4B00043B;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
-                               struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        vgic_reg_access(mmio, NULL, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
-        return false;
-}
-
-static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
-                                         struct kvm_exit_mmio *mmio,
-                                         phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                if (offset < 4) /* Force SGI enabled */
-                        *reg |= 0xffff;
-                vgic_retire_disabled_irqs(vcpu);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
-                                        struct kvm_exit_mmio *mmio,
-                                        phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
-                                          struct kvm_exit_mmio *mmio,
-                                          phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
-                                     struct kvm_exit_mmio *mmio,
-                                     phys_addr_t offset)
-{
-        u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
-                                        vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        return false;
-}
-
-#define GICD_ITARGETSR_SIZE     32
-#define GICD_CPUTARGETS_BITS    8
-#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
-static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 val = 0;
-
-        irq -= VGIC_NR_PRIVATE_IRQS;
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
-                        if (test_bit(irq + i, bmap))
-                                val |= 1 << (c + i * 8);
-        }
-
-        return val;
-}
-
-static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 target;
-
-        irq -= VGIC_NR_PRIVATE_IRQS;
-
-        /*
-         * Pick the LSB in each byte. This ensures we target exactly
-         * one vcpu per IRQ. If the byte is null, assume we target
-         * CPU0.
-         */
-        for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
-                int shift = i * GICD_CPUTARGETS_BITS;
-                target = ffs((val >> shift) & 0xffU);
-                target = target ? (target - 1) : 0;
-                dist->irq_spi_cpu[irq + i] = target;
-                kvm_for_each_vcpu(c, vcpu, kvm) {
-                        bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                        if (c == target)
-                                set_bit(irq + i, bmap);
-                        else
-                                clear_bit(irq + i, bmap);
-                }
-        }
-}
-
-static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
-                                   struct kvm_exit_mmio *mmio,
-                                   phys_addr_t offset)
-{
-        u32 reg;
-
-        /* We treat the banked interrupts targets as read-only */
-        if (offset < 32) {
-                u32 roreg = 1 << vcpu->vcpu_id;
-                roreg |= roreg << 8;
-                roreg |= roreg << 16;
-
-                vgic_reg_access(mmio, &roreg, offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                return false;
-        }
-
-        reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static u32 vgic_cfg_expand(u16 val)
-{
-        u32 res = 0;
-        int i;
-
-        /*
-         * Turn a 16bit value like abcd...mnop into a 32bit word
-         * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
-
-        return res;
-}
-
-static u16 vgic_cfg_compress(u32 val)
-{
-        u16 res = 0;
-        int i;
-
-        /*
-         * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
-         * abcd...mnop which is what we really care about.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
-
-        return res;
-}
-
-/*
- * The distributor uses 2 bits per IRQ for the CFG register, but the
- * LSB is always 0. As such, we only keep the upper bit, and use the
- * two above functions to compress/expand the bits
- */
-static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 val;
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
-                                       vcpu->vcpu_id, offset >> 1);
-        if (offset & 2)
-                val = *reg >> 16;
-        else
-                val = *reg & 0xffff;
-
-        val = vgic_cfg_expand(val);
-        vgic_reg_access(mmio, &val, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                if (offset < 4) {
-                        *reg = ~0U; /* Force PPIs/SGIs to 1 */
-                        return false;
-                }
-
-                val = vgic_cfg_compress(val);
-                if (offset & 2) {
-                        *reg &= 0xffff;
-                        *reg |= val << 16;
-                } else {
-                        *reg &= 0xffff << 16;
-                        *reg |= val;
-                }
-        }
-
-        return false;
-}
-
-static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_dispatch_sgi(vcpu, reg);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-/*
- * I would have liked to use the kvm_bus_io_*() API instead, but it
- * cannot cope with banked registers (only the VM pointer is passed
- * around, and we need the vcpu). One of these days, someone please
- * fix it!
- */
-struct mmio_range {
-        phys_addr_t base;
-        unsigned long len;
-        bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
-                            phys_addr_t offset);
-};
-
-static const struct mmio_range vgic_ranges[] = {
-        {
-                .base           = GIC_DIST_CTRL,
-                .len            = 12,
-                .handle_mmio    = handle_mmio_misc,
-        },
-        {
-                .base           = GIC_DIST_IGROUP,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_PRI,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_priority_reg,
-        },
-        {
-                .base           = GIC_DIST_TARGET,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_target_reg,
-        },
-        {
-                .base           = GIC_DIST_CONFIG,
-                .len            = VGIC_NR_IRQS / 4,
-                .handle_mmio    = handle_mmio_cfg_reg,
-        },
-        {
-                .base           = GIC_DIST_SOFTINT,
-                .len            = 4,
-                .handle_mmio    = handle_mmio_sgi_reg,
-        },
-        {}
-};
-
-static const
-struct mmio_range *find_matching_range(const struct mmio_range *ranges,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t base)
-{
-        const struct mmio_range *r = ranges;
-        phys_addr_t addr = mmio->phys_addr - base;
-
-        while (r->len) {
-                if (addr >= r->base &&
-                    (addr + mmio->len) <= (r->base + r->len))
-                        return r;
-                r++;
-        }
-
-        return NULL;
-}
-
-/**
- * vgic_handle_mmio - handle an in-kernel MMIO access
- * @vcpu:       pointer to the vcpu performing the access
- * @run:        pointer to the kvm_run structure
- * @mmio:       pointer to the data describing the access
- *
- * returns true if the MMIO access has been performed in kernel space,
- * and false if it needs to be emulated in user space.
- */
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio)
-{
-        const struct mmio_range *range;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long base = dist->vgic_dist_base;
-        bool updated_state;
-        unsigned long offset;
-
-        if (!irqchip_in_kernel(vcpu->kvm) ||
-            mmio->phys_addr < base ||
-            (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
-                return false;
-
-        /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
-        if (mmio->len > 4) {
-                kvm_inject_dabt(vcpu, mmio->phys_addr);
-                return true;
-        }
-
-        range = find_matching_range(vgic_ranges, mmio, base);
-        if (unlikely(!range || !range->handle_mmio)) {
-                pr_warn("Unhandled access %d %08llx %d\n",
-                        mmio->is_write, mmio->phys_addr, mmio->len);
-                return false;
-        }
-
-        spin_lock(&vcpu->kvm->arch.vgic.lock);
-        offset = mmio->phys_addr - range->base - base;
-        updated_state = range->handle_mmio(vcpu, mmio, offset);
-        spin_unlock(&vcpu->kvm->arch.vgic.lock);
-        kvm_prepare_mmio(run, mmio);
-        kvm_handle_mmio_return(vcpu, run);
-
-        if (updated_state)
-                vgic_kick_vcpus(vcpu->kvm);
-
-        return true;
-}
-
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
-{
-        struct kvm *kvm = vcpu->kvm;
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        int nrcpus = atomic_read(&kvm->online_vcpus);
-        u8 target_cpus;
-        int sgi, mode, c, vcpu_id;
-
-        vcpu_id = vcpu->vcpu_id;
-
-        sgi = reg & 0xf;
-        target_cpus = (reg >> 16) & 0xff;
-        mode = (reg >> 24) & 3;
-
-        switch (mode) {
-        case 0:
-                if (!target_cpus)
-                        return;
-
-        case 1:
-                target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
-                break;
-
-        case 2:
-                target_cpus = 1 << vcpu_id;
-                break;
-        }
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (target_cpus & 1) {
-                        /* Flag the SGI as pending */
-                        vgic_dist_irq_set(vcpu, sgi);
-                        dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
-                        kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
-                }
-
-                target_cpus >>= 1;
-        }
-}
-
-static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
-        unsigned long pending_private, pending_shared;
-        int vcpu_id;
-
-        vcpu_id = vcpu->vcpu_id;
-        pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
-        pend_shared = vcpu->arch.vgic_cpu.pending_shared;
-
-        pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
-        enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
-        bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
-
-        pending = vgic_bitmap_get_shared_map(&dist->irq_state);
-        enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
-        bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
-        bitmap_and(pend_shared, pend_shared,
-                   vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
-                   VGIC_NR_SHARED_IRQS);
-
-        pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
-        pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
-        return (pending_private < VGIC_NR_PRIVATE_IRQS ||
-                pending_shared < VGIC_NR_SHARED_IRQS);
-}
-
-/*
- * Update the interrupt state and determine which CPUs have pending
- * interrupts. Must be called with distributor lock held.
- */
-static void vgic_update_state(struct kvm *kvm)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int c;
-
-        if (!dist->enabled) {
-                set_bit(0, &dist->irq_pending_on_cpu);
-                return;
-        }
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (compute_pending_for_cpu(vcpu)) {
-                        pr_debug("CPU%d has pending interrupts\n", c);
-                        set_bit(c, &dist->irq_pending_on_cpu);
-                }
-        }
-}
-
-#define LR_CPUID(lr)    \
-        (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
-#define MK_LR_PEND(src, irq)    \
-        (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
-
-/*
- * An interrupt may have been disabled after being made pending on the
- * CPU interface (the classic case is a timer running while we're
- * rebooting the guest - the interrupt would kick as soon as the CPU
- * interface gets enabled, with deadly consequences).
- *
- * The solution is to examine already active LRs, and check the
- * interrupt is still enabled. If not, just retire it.
- */
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-
-        for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
-                int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                if (!vgic_irq_is_enabled(vcpu, irq)) {
-                        vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-                        clear_bit(lr, vgic_cpu->lr_used);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE;
-                        if (vgic_irq_is_active(vcpu, irq))
-                                vgic_irq_clear_active(vcpu, irq);
-                }
-        }
-}
-
-/*
- * Queue an interrupt to a CPU virtual interface. Return true on success,
- * or false if it wasn't possible to queue it.
- */
-static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-
-        /* Sanitize the input... */
-        BUG_ON(sgi_source_id & ~7);
-        BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
-        BUG_ON(irq >= VGIC_NR_IRQS);
-
-        kvm_debug("Queue IRQ%d\n", irq);
-
-        lr = vgic_cpu->vgic_irq_lr_map[irq];
-
-        /* Do we have an active interrupt for the same CPUID? */
-        if (lr != LR_EMPTY &&
-            (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
-                kvm_debug("LR%d piggyback for IRQ%d %x\n",
-                          lr, irq, vgic_cpu->vgic_lr[lr]);
-                BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
-                return true;
-        }
-
-        /* Try to use another LR for this interrupt */
-        lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
-                               vgic_cpu->nr_lr);
-        if (lr >= vgic_cpu->nr_lr)
-                return false;
-
-        kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
-        vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
-        vgic_cpu->vgic_irq_lr_map[irq] = lr;
-        set_bit(lr, vgic_cpu->lr_used);
-
-        if (!vgic_irq_is_edge(vcpu, irq))
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
-
-        return true;
-}
-
-static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long sources;
-        int vcpu_id = vcpu->vcpu_id;
-        int c;
-
-        sources = dist->irq_sgi_sources[vcpu_id][irq];
-
-        for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
-                if (vgic_queue_irq(vcpu, c, irq))
-                        clear_bit(c, &sources);
-        }
-
-        dist->irq_sgi_sources[vcpu_id][irq] = sources;
-
-        /*
-         * If the sources bitmap has been cleared it means that we
-         * could queue all the SGIs onto link registers (see the
-         * clear_bit above), and therefore we are done with them in
-         * our emulated gic and can get rid of them.
-         */
-        if (!sources) {
-                vgic_dist_irq_clear(vcpu, irq);
-                vgic_cpu_irq_clear(vcpu, irq);
-                return true;
-        }
-
-        return false;
-}
-
-static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
-{
-        if (vgic_irq_is_active(vcpu, irq))
-                return true; /* level interrupt, already queued */
-
-        if (vgic_queue_irq(vcpu, 0, irq)) {
-                if (vgic_irq_is_edge(vcpu, irq)) {
-                        vgic_dist_irq_clear(vcpu, irq);
-                        vgic_cpu_irq_clear(vcpu, irq);
-                } else {
-                        vgic_irq_set_active(vcpu, irq);
-                }
-
-                return true;
-        }
-
-        return false;
-}
-
-/*
- * Fill the list registers with pending interrupts before running the
- * guest.
- */
-static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i, vcpu_id;
-        int overflow = 0;
-
-        vcpu_id = vcpu->vcpu_id;
-
-        /*
-         * We may not have any pending interrupt, or the interrupts
-         * may have been serviced from another vcpu. In all cases,
-         * move along.
-         */
-        if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
-                pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
-                goto epilog;
-        }
-
-        /* SGIs */
-        for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
-                if (!vgic_queue_sgi(vcpu, i))
-                        overflow = 1;
-        }
-
-        /* PPIs */
-        for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i))
-                        overflow = 1;
-        }
-
-        /* SPIs */
-        for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
-                        overflow = 1;
-        }
-
-epilog:
-        if (overflow) {
-                vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
-        } else {
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-                /*
-                 * We're about to run this VCPU, and we've consumed
-                 * everything the distributor had in store for
-                 * us. Claim we don't have anything pending. We'll
-                 * adjust that if needed while exiting.
-                 */
-                clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
-        }
-}
-
-static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        bool level_pending = false;
-
-        kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
-
-        if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
-                /*
-                 * Some level interrupts have been EOIed. Clear their
-                 * active bit.
-                 */
-                int lr, irq;
-
-                for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
-                                 vgic_cpu->nr_lr) {
-                        irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                        vgic_irq_clear_active(vcpu, irq);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
-
-                        /* Any additional pending interrupt? */
-                        if (vgic_dist_irq_is_pending(vcpu, irq)) {
-                                vgic_cpu_irq_set(vcpu, irq);
-                                level_pending = true;
-                        } else {
-                                vgic_cpu_irq_clear(vcpu, irq);
-                        }
-
-                        /*
-                         * Despite being EOIed, the LR may not have
-                         * been marked as empty.
-                         */
-                        set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
-                }
-        }
-
-        if (vgic_cpu->vgic_misr & GICH_MISR_U)
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-
-        return level_pending;
-}
-
-/*
- * Sync back the VGIC state after a guest run. The distributor lock is
- * needed so we don't get preempted in the middle of the state processing.
- */
-static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int lr, pending;
-        bool level_pending;
-
-        level_pending = vgic_process_maintenance(vcpu);
-
-        /* Clear mappings for empty LRs */
-        for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
-                         vgic_cpu->nr_lr) {
-                int irq;
-
-                if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
-                        continue;
-
-                irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                BUG_ON(irq >= VGIC_NR_IRQS);
-                vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-        }
-
-        /* Check if we still have something up our sleeve... */
-        pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
-                                      vgic_cpu->nr_lr);
-        if (level_pending || pending < vgic_cpu->nr_lr)
-                set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-
-        spin_lock(&dist->lock);
-        __kvm_vgic_flush_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-
-        spin_lock(&dist->lock);
-        __kvm_vgic_sync_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-
-        return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-
-static void vgic_kick_vcpus(struct kvm *kvm)
-{
-        struct kvm_vcpu *vcpu;
-        int c;
-
-        /*
-         * We've injected an interrupt, time to find out who deserves
-         * a good kick...
-         */
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (kvm_vgic_vcpu_pending_irq(vcpu))
-                        kvm_vcpu_kick(vcpu);
-        }
-}
-
-static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
-{
-        int is_edge = vgic_irq_is_edge(vcpu, irq);
-        int state = vgic_dist_irq_is_pending(vcpu, irq);
-
-        /*
-         * Only inject an interrupt if:
-         * - edge triggered and we have a rising edge
-         * - level triggered and we change level
-         */
-        if (is_edge)
-                return level > state;
-        else
-                return level != state;
-}
-
-static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
-                                  unsigned int irq_num, bool level)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int is_edge, is_level;
-        int enabled;
-        bool ret = true;
-
-        spin_lock(&dist->lock);
-
-        vcpu = kvm_get_vcpu(kvm, cpuid);
-        is_edge = vgic_irq_is_edge(vcpu, irq_num);
-        is_level = !is_edge;
-
-        if (!vgic_validate_injection(vcpu, irq_num, level)) {
-                ret = false;
-                goto out;
-        }
-
-        if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
-                cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
-                vcpu = kvm_get_vcpu(kvm, cpuid);
-        }
-
-        kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
-
-        if (level)
-                vgic_dist_irq_set(vcpu, irq_num);
-        else
-                vgic_dist_irq_clear(vcpu, irq_num);
-
-        enabled = vgic_irq_is_enabled(vcpu, irq_num);
-
-        if (!enabled) {
-                ret = false;
-                goto out;
-        }
-
-        if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
-                /*
-                 * Level interrupt in progress, will be picked up
-                 * when EOId.
-                 */
-                ret = false;
-                goto out;
-        }
-
-        if (level) {
-                vgic_cpu_irq_set(vcpu, irq_num);
-                set_bit(cpuid, &dist->irq_pending_on_cpu);
-        }
-
-out:
-        spin_unlock(&dist->lock);
-
-        return ret;
-}
-
-/**
- * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
- * @kvm:     The VM structure pointer
- * @cpuid:   The CPU for PPIs
- * @irq_num: The IRQ number that is assigned to the device
- * @level:   Edge-triggered:  true:  to trigger the interrupt
- *                            false: to ignore the call
- *           Level-sensitive  true:  activates an interrupt
- *                            false: deactivates an interrupt
- *
- * The GIC is not concerned with devices being active-LOW or active-HIGH for
- * level-sensitive interrupts.  You can think of the level parameter as 1
- * being HIGH and 0 being LOW and all devices being active-HIGH.
- */
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level)
-{
-        if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
-                vgic_kick_vcpus(kvm);
-
-        return 0;
-}
-
-static irqreturn_t vgic_maintenance_handler(int irq, void *data)
-{
-        /*
-         * We cannot rely on the vgic maintenance interrupt to be
-         * delivered synchronously. This means we can only use it to
-         * exit the VM, and we perform the handling of EOIed
-         * interrupts on the exit path (see vgic_process_maintenance).
-         */
-        return IRQ_HANDLED;
-}
-
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-
-        if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
-                return -EBUSY;
-
-        for (i = 0; i < VGIC_NR_IRQS; i++) {
-                if (i < VGIC_NR_PPIS)
-                        vgic_bitmap_set_irq_val(&dist->irq_enabled,
-                                                vcpu->vcpu_id, i, 1);
-                if (i < VGIC_NR_PRIVATE_IRQS)
-                        vgic_bitmap_set_irq_val(&dist->irq_cfg,
-                                                vcpu->vcpu_id, i, VGIC_CFG_EDGE);
-
-                vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
-        }
-
-        /*
-         * By forcing VMCR to zero, the GIC will restore the binary
-         * points to their reset values. Anything else resets to zero
-         * anyway.
-         */
-        vgic_cpu->vgic_vmcr = 0;
-
-        vgic_cpu->nr_lr = vgic_nr_lr;
-        vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
-
-        return 0;
-}
-
-static void vgic_init_maintenance_interrupt(void *info)
-{
-        enable_percpu_irq(vgic_maint_irq, 0);
-}
-
-static int vgic_cpu_notify(struct notifier_block *self,
-                           unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                vgic_init_maintenance_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(vgic_maint_irq);
-                break;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block vgic_cpu_nb = {
-        .notifier_call = vgic_cpu_notify,
-};
-
-int kvm_vgic_hyp_init(void)
-{
-        int ret;
-        struct resource vctrl_res;
-        struct resource vcpu_res;
-
-        vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
-        if (!vgic_node) {
-                kvm_err("error: no compatible vgic node in DT\n");
-                return -ENODEV;
-        }
-
-        vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
-        if (!vgic_maint_irq) {
-                kvm_err("error getting vgic maintenance irq from DT\n");
-                ret = -ENXIO;
-                goto out;
-        }
-
-        ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
-                                 "vgic", kvm_get_running_vcpus());
-        if (ret) {
-                kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
-                goto out;
-        }
-
-        ret = register_cpu_notifier(&vgic_cpu_nb);
-        if (ret) {
-                kvm_err("Cannot register vgic CPU notifier\n");
-                goto out_free_irq;
-        }
-
-        ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
-        if (ret) {
-                kvm_err("Cannot obtain VCTRL resource\n");
-                goto out_free_irq;
-        }
-
-        vgic_vctrl_base = of_iomap(vgic_node, 2);
-        if (!vgic_vctrl_base) {
-                kvm_err("Cannot ioremap VCTRL\n");
-                ret = -ENOMEM;
-                goto out_free_irq;
-        }
-
-        vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
-        vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
-
-        ret = create_hyp_io_mappings(vgic_vctrl_base,
-                                     vgic_vctrl_base + resource_size(&vctrl_res),
-                                     vctrl_res.start);
-        if (ret) {
-                kvm_err("Cannot map VCTRL into hyp\n");
-                goto out_unmap;
-        }
-
-        kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
-                 vctrl_res.start, vgic_maint_irq);
-        on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
-
-        if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
-                kvm_err("Cannot obtain VCPU resource\n");
-                ret = -ENXIO;
-                goto out_unmap;
-        }
-        vgic_vcpu_base = vcpu_res.start;
-
-        goto out;
-
-out_unmap:
-        iounmap(vgic_vctrl_base);
-out_free_irq:
-        free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
-out:
-        of_node_put(vgic_node);
-        return ret;
-}
-
-int kvm_vgic_init(struct kvm *kvm)
-{
-        int ret = 0, i;
-
-        mutex_lock(&kvm->lock);
-
-        if (vgic_initialized(kvm))
-                goto out;
-
-        if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
-            IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
-                kvm_err("Need to set vgic cpu and dist addresses first\n");
-                ret = -ENXIO;
-                goto out;
-        }
-
-        ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
-                                    vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
-        if (ret) {
-                kvm_err("Unable to remap VGIC CPU to VCPU\n");
-                goto out;
-        }
-
-        for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
-                vgic_set_target_reg(kvm, 0, i);
-
-        kvm_timer_init(kvm);
-        kvm->arch.vgic.ready = true;
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-
-int kvm_vgic_create(struct kvm *kvm)
-{
-        int ret = 0;
-
-        mutex_lock(&kvm->lock);
-
-        if (atomic_read(&kvm->online_vcpus) || kvm->arch.vgic.vctrl_base) {
-                ret = -EEXIST;
-                goto out;
-        }
-
-        spin_lock_init(&kvm->arch.vgic.lock);
-        kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
-        kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
-        kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
-
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-
-static bool vgic_ioaddr_overlap(struct kvm *kvm)
-{
-        phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
-        phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
-
-        if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
-                return 0;
-        if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
-            (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
-                return -EBUSY;
-        return 0;
-}
-
-static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
-                              phys_addr_t addr, phys_addr_t size)
-{
-        int ret;
-
-        if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
-                return -EEXIST;
-        if (addr + size < addr)
-                return -EINVAL;
-
-        ret = vgic_ioaddr_overlap(kvm);
-        if (ret)
-                return ret;
-        *ioaddr = addr;
-        return ret;
-}
-
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        int r = 0;
-        struct vgic_dist *vgic = &kvm->arch.vgic;
-
-        if (addr & ~KVM_PHYS_MASK)
-                return -E2BIG;
-
-        if (addr & (SZ_4K - 1))
-                return -EINVAL;
-
-        mutex_lock(&kvm->lock);
-        switch (type) {
-        case KVM_VGIC_V2_ADDR_TYPE_DIST:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
-                                       addr, KVM_VGIC_V2_DIST_SIZE);
-                break;
-        case KVM_VGIC_V2_ADDR_TYPE_CPU:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
-                                       addr, KVM_VGIC_V2_CPU_SIZE);
-                break;
-        default:
-                r = -ENODEV;
-        }
-
-        mutex_unlock(&kvm->lock);
-        return r;
-}
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..e026b19b23ea 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -40,6 +40,7 @@ config ARCH_DAVINCI_DA850
         bool "DA850/OMAP-L138/AM18x based system"
         select ARCH_DAVINCI_DA8XX
         select ARCH_HAS_CPUFREQ
+        select CPU_FREQ_TABLE
         select CP_INTC
 
 config ARCH_DAVINCI_DA8XX
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d6933848abf..a0d4f6038b60 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1004,7 +1004,7 @@ static const struct da850_opp da850_opp_96 = {
 
 #define OPP(freq)               \
         {                               \
-                .index = (unsigned int) &da850_opp_##freq,      \
+                .driver_data = (unsigned int) &da850_opp_##freq,        \
                 .frequency = freq * 1000, \
         }
 
@@ -1016,7 +1016,7 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
         OPP(200),
         OPP(96),
         {
-                .index          = 0,
+                .driver_data            = 0,
                 .frequency      = CPUFREQ_TABLE_END,
         },
 };
@@ -1044,7 +1044,7 @@ static int da850_set_voltage(unsigned int index)
         if (!cvdd)
                 return -ENODEV;
 
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
 
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -1125,7 +1125,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         struct pll_data *pll = clk->pll_data;
         int ret;
 
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
         prediv = opp->prediv;
         mult = opp->mult;
         postdiv = opp->postdiv;
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74114db..8a53f346cdb3 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
         iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
                                             unsigned int flags, void *caller)
 {
         return (void __iomem *)cookie;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ba70a846d1c6..855d4a7b462d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,7 +93,7 @@ config SOC_EXYNOS5440
         default y
         depends on ARCH_EXYNOS5
         select ARCH_HAS_OPP
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select AUTO_ZRELADDR
         select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index dae4cd7be040..6f424eced181 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -268,10 +268,11 @@ static struct mc13xxx_led_platform_data moboard_led[] = {
 static struct mc13xxx_leds_platform_data moboard_leds = {
         .num_leds = ARRAY_SIZE(moboard_led),
         .led = moboard_led,
-        .flags = MC13783_LED_SLEWLIMTC,
-        .abmode = MC13783_LED_AB_DISABLED,
-        .tc1_period = MC13783_LED_PERIOD_10MS,
-        .tc2_period = MC13783_LED_PERIOD_10MS,
+        .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0),
+        .led_control[1] = MC13783_LED_C1_SLEWLIM,
+        .led_control[2] = MC13783_LED_C2_SLEWLIM,
+        .led_control[3] = MC13783_LED_C3_PERIOD(0),
+        .led_control[4] = MC13783_LED_C3_PERIOD(0),
 };
 
 static struct mc13xxx_buttons_platform_data moboard_buttons = {
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 8f0f60697f55..0884ca90d15a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
                 : "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                          unsigned int mtype, void *caller)
 {
         if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b5511b..faaf7d4482c5 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 
 #include "pci.h"
 
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
         size_t size, unsigned int mtype, void *caller)
 {
         void __iomem * retval;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61ea63e..1c5bd7637b05 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -469,7 +469,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         break;
                 case IOP13XX_INIT_ADMA_1:
@@ -479,7 +478,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         break;
                 case IOP13XX_INIT_ADMA_2:
@@ -489,7 +487,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         dma_cap_set(DMA_PQ, plat_data->cap_mask);
                         dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff6bd92..d7223b3b81f3 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const char *cmd)
  * fallback to the default.
  */
 
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
                                            unsigned int mtype, void *caller)
 {
         if (!is_pci_memory(addr))
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index ce8215a269e5..421cf7751a80 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void);
 extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
 
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                           unsigned int mtype, void *caller);
 
 extern struct smp_operations msm_smp_ops;
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index efa113e4de86..3dc04ccaf59f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -168,7 +168,7 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                    unsigned int mtype, void *caller)
 {
         if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 58152b15ecaa..627fa7e41fba 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -62,6 +62,7 @@ config SOC_OMAP5
         select HAVE_SMP
         select COMMON_CLK
         select HAVE_ARM_ARCH_TIMER
+        select ARM_ERRATA_798181
 
 config SOC_AM33XX
         bool "AM33XX support"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea5a27ff9941..d4f671547c37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -95,10 +95,6 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
 
-ifeq ($(CONFIG_PM_VERBOSE),y)
-CFLAGS_pm_bus.o                         += -DDEBUG
-endif
-
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index b54562d1235e..87e65dde8e13 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -553,6 +553,37 @@ static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* Display Sub System */
+        OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        /* TFP410 PanelBus DVI Transmitte (GPIO_170) */
+        OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
         /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
         OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index bd74f9f6063b..bdd1e3a179e1 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -61,7 +61,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
 
 static int __init rx51_video_init(void)
 {
-        if (!machine_is_nokia_rx51())
+        if (!machine_is_nokia_rx51() && !of_machine_is_compatible("nokia,omap3-n900"))
                 return 0;
 
         if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index aef96e45cb20..3c1279f27d1f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -15,7 +15,6 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
@@ -66,7 +65,7 @@ static int __init omap3_l3_init(void)
 
         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap3_l3_init);
 
@@ -100,7 +99,7 @@ static int __init omap4_l3_init(void)
 
         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap4_l3_init);
 
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 190ae493c6ef..2ca33cc0c484 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -83,10 +83,7 @@ static int __init omap_init_vrfb(void)
         pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
                         res, num_res, NULL, 0);
 
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
-        else
-                return 0;
+        return PTR_RET(pdev);
 }
 
 omap_arch_initcall(omap_init_vrfb);
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1c7969e965d7..f3fdd6afa213 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1734,7 +1734,7 @@ static int __init omap_gpmc_init(void)
         pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
 
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap_gpmc_init);
 
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 68be532f8688..5cc92874be7e 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -588,11 +588,6 @@ static int _od_runtime_suspend(struct device *dev)
         return ret;
 }
 
-static int _od_runtime_idle(struct device *dev)
-{
-        return pm_generic_runtime_idle(dev);
-}
-
 static int _od_runtime_resume(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
@@ -648,7 +643,7 @@ static int _od_resume_noirq(struct device *dev)
 struct dev_pm_domain omap_device_pm_domain = {
         .ops = {
                 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
-                                   _od_runtime_idle)
+                                   NULL)
                 USE_PLATFORM_PM_SLEEP_OPS
                 .suspend_noirq = _od_suspend_noirq,
                 .resume_noirq = _od_resume_noirq,
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 9ace8eae7ee8..33c8846b4193 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -54,10 +54,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
         WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
              dev_name);
 
-        if (IS_ERR(omap_pmu_dev))
-                return PTR_ERR(omap_pmu_dev);
-
-        return 0;
+        return PTR_RET(omap_pmu_dev);
 }
 
 static int __init omap_init_pmu(void)
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 88ff83a0942e..9086ce03ae12 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -34,6 +34,8 @@ ppa_zero_params:
 ppa_por_params:
         .word           1, 0
 
+#ifdef CONFIG_ARCH_OMAP4
+
 /*
  * =============================
  * == CPU suspend finisher ==
@@ -326,7 +328,9 @@ skip_l2en:
 
         b       cpu_resume                      @ Jump to generic resume
 ENDPROC(omap4_cpu_resume)
-#endif
+#endif  /* CONFIG_ARCH_OMAP4 */
+
+#endif  /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
 
 #ifndef CONFIG_OMAP4_ERRATA_I688
 ENTRY(omap_bus_sync)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index aee3c8940a30..7a42e1960c3b 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -26,14 +26,14 @@ static int sr_class3_enable(struct omap_sr *sr)
         }
 
         omap_vp_enable(sr->voltdm);
-        return sr_enable(sr->voltdm, volt);
+        return sr_enable(sr, volt);
 }
 
 static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-        sr_disable_errgen(sr->voltdm);
+        sr_disable_errgen(sr);
         omap_vp_disable(sr->voltdm);
-        sr_disable(sr->voltdm);
+        sr_disable(sr);
         if (is_volt_reset)
                 voltdm_reset(sr->voltdm);
 
@@ -42,7 +42,7 @@ static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 
 static int sr_class3_configure(struct omap_sr *sr)
 {
-        return sr_configure_errgen(sr->voltdm);
+        return sr_configure_errgen(sr);
 }
 
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3bdb0fb02028..5f148e721790 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -220,7 +220,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                                          int posted)
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
-        const char *oh_name;
+        const char *oh_name = NULL;
         struct device_node *np;
         struct omap_hwmod *oh;
         struct resource irq, mem;
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100dbf5a2e..a8427115ee07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -615,12 +615,14 @@ endmenu
 config PXA25x
         bool
         select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA21x/25x/26x variants
 
 config PXA27x
         bool
         select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA27x variants
 
@@ -633,6 +635,7 @@ config CPU_PXA26x
 config PXA3xx
         bool
         select CPU_XSC3
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA3xx variants
 
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index ddd8280e3875..2a0aa5684e72 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -60,5 +60,5 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+        __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
 }
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index dcf3420a3271..5e37d368594b 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -33,36 +33,36 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table pll_vals_12MHz[] = {
-    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
-    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
-    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
-    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
-    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
-    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
-    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
-    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
-    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
-    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
-    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
-    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
-    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
-    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
-    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
-    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
-    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
-    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
-    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
-    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
-    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
-    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+    { .frequency = 34000000,  .driver_data = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .driver_data = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .driver_data = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .driver_data = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .driver_data = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .driver_data = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .driver_data = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .driver_data = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .driver_data = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1),  },
 
     /* 2410A extras */
 
-    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
-    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
-    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
-    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
-    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+    { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1),  },
 };
 
 static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 673781758319..a19460e6e7b0 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -21,33 +21,33 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
-        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
-        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
-        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
-        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
-        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
-        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
-        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
-        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
-        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
-        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
-        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
-        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
-        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
-        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
-        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
-        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
-        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
-        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
-        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
-        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
-        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
-        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
-        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
-        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
-        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
-        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
-        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+        { .frequency = 75000000,        .driver_data = PLLVAL(0x75, 3, 3),  },  /* FVco 600.000000 */
+        { .frequency = 80000000,        .driver_data = PLLVAL(0x98, 4, 3),  },  /* FVco 640.000000 */
+        { .frequency = 90000000,        .driver_data = PLLVAL(0x70, 2, 3),  },  /* FVco 720.000000 */
+        { .frequency = 100000000,       .driver_data = PLLVAL(0x5c, 1, 3),  },  /* FVco 800.000000 */
+        { .frequency = 110000000,       .driver_data = PLLVAL(0x66, 1, 3),  },  /* FVco 880.000000 */
+        { .frequency = 120000000,       .driver_data = PLLVAL(0x70, 1, 3),  },  /* FVco 960.000000 */
+        { .frequency = 150000000,       .driver_data = PLLVAL(0x75, 3, 2),  },  /* FVco 600.000000 */
+        { .frequency = 160000000,       .driver_data = PLLVAL(0x98, 4, 2),  },  /* FVco 640.000000 */
+        { .frequency = 170000000,       .driver_data = PLLVAL(0x4d, 1, 2),  },  /* FVco 680.000000 */
+        { .frequency = 180000000,       .driver_data = PLLVAL(0x70, 2, 2),  },  /* FVco 720.000000 */
+        { .frequency = 190000000,       .driver_data = PLLVAL(0x57, 1, 2),  },  /* FVco 760.000000 */
+        { .frequency = 200000000,       .driver_data = PLLVAL(0x5c, 1, 2),  },  /* FVco 800.000000 */
+        { .frequency = 210000000,       .driver_data = PLLVAL(0x84, 2, 2),  },  /* FVco 840.000000 */
+        { .frequency = 220000000,       .driver_data = PLLVAL(0x66, 1, 2),  },  /* FVco 880.000000 */
+        { .frequency = 230000000,       .driver_data = PLLVAL(0x6b, 1, 2),  },  /* FVco 920.000000 */
+        { .frequency = 240000000,       .driver_data = PLLVAL(0x70, 1, 2),  },  /* FVco 960.000000 */
+        { .frequency = 300000000,       .driver_data = PLLVAL(0x75, 3, 1),  },  /* FVco 600.000000 */
+        { .frequency = 310000000,       .driver_data = PLLVAL(0x93, 4, 1),  },  /* FVco 620.000000 */
+        { .frequency = 320000000,       .driver_data = PLLVAL(0x98, 4, 1),  },  /* FVco 640.000000 */
+        { .frequency = 330000000,       .driver_data = PLLVAL(0x66, 2, 1),  },  /* FVco 660.000000 */
+        { .frequency = 340000000,       .driver_data = PLLVAL(0x4d, 1, 1),  },  /* FVco 680.000000 */
+        { .frequency = 350000000,       .driver_data = PLLVAL(0xa7, 4, 1),  },  /* FVco 700.000000 */
+        { .frequency = 360000000,       .driver_data = PLLVAL(0x70, 2, 1),  },  /* FVco 720.000000 */
+        { .frequency = 370000000,       .driver_data = PLLVAL(0xb1, 4, 1),  },  /* FVco 740.000000 */
+        { .frequency = 380000000,       .driver_data = PLLVAL(0x57, 1, 1),  },  /* FVco 760.000000 */
+        { .frequency = 390000000,       .driver_data = PLLVAL(0x7a, 2, 1),  },  /* FVco 780.000000 */
+        { .frequency = 400000000,       .driver_data = PLLVAL(0x5c, 1, 1),  },  /* FVco 800.000000 */
 };
 
 static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index debfa106289b..1191b2905625 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -21,61 +21,61 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
-        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
-        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
-        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
-        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
-        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
-        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
-        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
-        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
-        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
-        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
-        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
-        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
-        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
-        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
-        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
-        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
-        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
-        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
-        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
-        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
-        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
-        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
-        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
-        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
-        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
-        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
-        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
-        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
-        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
-        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
-        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
-        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
-        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
-        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
-        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
-        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
-        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
-        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
-        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
-        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
-        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
-        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
-        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
-        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
-        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
-        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
-        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
-        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
-        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
-        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
-        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
-        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
-        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
-        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
-        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+        { .frequency = 78019200,        .driver_data = PLLVAL(121, 5, 3),       },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .driver_data = PLLVAL(131, 5, 3),       },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .driver_data = PLLVAL(141, 5, 3),       },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .driver_data = PLLVAL(151, 5, 3),       },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .driver_data = PLLVAL(185, 6, 3),       },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .driver_data = PLLVAL(171, 5, 3),       },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .driver_data = PLLVAL(127, 3, 3),       },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .driver_data = PLLVAL(134, 3, 3),       },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .driver_data = PLLVAL(141, 3, 3),       },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .driver_data = PLLVAL(148, 3, 3),       },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .driver_data = PLLVAL(155, 3, 3),       },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .driver_data = PLLVAL(163, 3, 3),       },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .driver_data = PLLVAL(187, 9, 2),       },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .driver_data = PLLVAL(121, 5, 2),       },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .driver_data = PLLVAL(126, 5, 2),       },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .driver_data = PLLVAL(131, 5, 2),       },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .driver_data = PLLVAL(177, 7, 2),       },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .driver_data = PLLVAL(141, 5, 2),       },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .driver_data = PLLVAL(124, 4, 2),       },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .driver_data = PLLVAL(151, 5, 2),       },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .driver_data = PLLVAL(109, 3, 2),       },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .driver_data = PLLVAL(185, 6, 2),       },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .driver_data = PLLVAL(141, 4, 2),       },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .driver_data = PLLVAL(171, 5, 2),       },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .driver_data = PLLVAL(97, 2, 2),        },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .driver_data = PLLVAL(127, 3, 2),       },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .driver_data = PLLVAL(158, 4, 2),       },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .driver_data = PLLVAL(134, 3, 2),       },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .driver_data = PLLVAL(167, 4, 2),       },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .driver_data = PLLVAL(141, 3, 2),       },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .driver_data = PLLVAL(114, 2, 2),       },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .driver_data = PLLVAL(148, 3, 2),       },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .driver_data = PLLVAL(120, 2, 2),       },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .driver_data = PLLVAL(155, 3, 2),       },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .driver_data = PLLVAL(92, 1, 2),        },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .driver_data = PLLVAL(163, 3, 2),       },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .driver_data = PLLVAL(131, 2, 2),       },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .driver_data = PLLVAL(187, 9, 1),       },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .driver_data = PLLVAL(191, 9, 1),       },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .driver_data = PLLVAL(121, 5, 1),       },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .driver_data = PLLVAL(86, 3, 1),        },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .driver_data = PLLVAL(126, 5, 1),       },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .driver_data = PLLVAL(109, 4, 1),       },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .driver_data = PLLVAL(131, 5, 1),       },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .driver_data = PLLVAL(93, 3, 1),        },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .driver_data = PLLVAL(177, 7, 1),       },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .driver_data = PLLVAL(118, 4, 1),       },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .driver_data = PLLVAL(141, 5, 1),       },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .driver_data = PLLVAL(165, 6, 1),       },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .driver_data = PLLVAL(124, 4, 1),       },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .driver_data = PLLVAL(126, 4, 1),       },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .driver_data = PLLVAL(151, 5, 1),       },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .driver_data = PLLVAL(177, 6, 1),       },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .driver_data = PLLVAL(109, 3, 1),       },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .driver_data = PLLVAL(87, 2, 1),        },      /* FVco 804.384000 */
 };
 
 static int s3c2440_plls169344_add(struct device *dev,
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index db27e8eef192..3912ce91fee4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,7 +23,7 @@ config ARCH_R8A73A4
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
@@ -59,7 +59,7 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7e105932c09d..5390c6bbbc02 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -142,15 +142,15 @@ static void pllc2_table_rebuild(struct clk *clk)
         /* Initialise PLLC2 frequency table */
         for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
                 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
-                pllc2_freq_table[i].index = i;
+                pllc2_freq_table[i].driver_data = i;
         }
 
         /* This is a special entry - switching PLL off makes it a repeater */
         pllc2_freq_table[i].frequency = clk->parent->rate;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
 
         pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
 }
 
 static unsigned long pllc2_recalc(struct clk *clk)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc36dfe..ef3a8da49b2d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -28,7 +28,6 @@ config ARCH_TEGRA_2x_SOC
         select ARM_ERRATA_754327 if SMP
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA20
@@ -46,7 +45,6 @@ config ARCH_TEGRA_3x_SOC
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA30
@@ -60,10 +58,9 @@ config ARCH_TEGRA_3x_SOC
 
 config ARCH_TEGRA_114_SOC
         bool "Enable support for Tegra114 family"
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select ARM_GIC
         select ARM_L1_CACHE_SHIFT_6
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA114
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index ec5836b1e713..b25153e2ebaa 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irqchip.h>
-#include <linux/clk/tegra.h>
+#include <linux/clk-provider.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -60,7 +60,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-        tegra_clocks_init();
+        of_clk_init(NULL);
         tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index b6145ea51641..e6fb0239151b 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
         } else if (cpu_is_u9540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
-                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
                                U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
                                U8500_CLKRST6_BASE);
         } else if (cpu_is_u8540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
-                u8540_clk_init();
+                u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
         }
 }
 
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
index 8958f0d896bc..081d46929436 100644
--- a/arch/arm/mach-virt/Kconfig
+++ b/arch/arm/mach-virt/Kconfig
@@ -2,7 +2,7 @@ config ARCH_VIRT
         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select ARM_PSCI
         select HAVE_SMP
         select CPU_V7
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9e8101ecd63e..6cacdc8dd654 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -392,7 +392,8 @@ config CPU_V7
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_COPY_V6 if MMU
-        select CPU_CP15_MMU
+        select CPU_CP15_MMU if MMU
+        select CPU_CP15_MPU if !MMU
         select CPU_HAS_ASID if MMU
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ee558a01f390..ecfe6e53f6e0 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
+obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)    += abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)      += abort-ev4.o
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c465faca51b0..d70e0aba0c9d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
         }
 }
 
+/*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+ * invalidation/clean/flush
+ *
+ * Section Address Range              Offset        EMI
+ *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
+ *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
+ *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
+ *
+ * When the start and end addresses have crossed two different sections, we
+ * need to break the L2 operation into two, each within its own section.
+ * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
+ * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
+ * 0xC0000000 - 0xC0001000
+ *
+ * Note 1:
+ * By breaking a single L2 operation into two, we may potentially suffer some
+ * performance hit, but keep in mind the cross section case is very rare
+ *
+ * Note 2:
+ * We do not need to handle the case when the start address is in
+ * Section 1 and the end address is in Section 3, since it is not a valid use
+ * case
+ *
+ * Note 3:
+ * Section 1 in practical terms can no longer be used on rev A2. Because of
+ * that the code does not need to handle section 1 at all.
+ *
+ */
+#define BCM_SYS_EMI_START_ADDR        0x40000000UL
+#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
+
+#define BCM_SYS_EMI_OFFSET            0x40000000UL
+#define BCM_VC_EMI_OFFSET             0x80000000UL
+
+static inline int bcm_addr_is_sys_emi(unsigned long addr)
+{
+        return (addr >= BCM_SYS_EMI_START_ADDR) &&
+                (addr < BCM_VC_EMI_SEC3_START_ADDR);
+}
+
+static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
+{
+        if (bcm_addr_is_sys_emi(addr))
+                return addr + BCM_SYS_EMI_OFFSET;
+        else
+                return addr + BCM_VC_EMI_OFFSET;
+}
+
+static void bcm_inv_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_inv_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_inv_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
+static void bcm_clean_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        if ((end - start) >= l2x0_size) {
+                l2x0_clean_all();
+                return;
+        }
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_clean_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_clean_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
+static void bcm_flush_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        if ((end - start) >= l2x0_size) {
+                l2x0_flush_all();
+                return;
+        }
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_flush_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_flush_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
 static void __init l2x0_of_setup(const struct device_node *np,
                                  u32 *aux_val, u32 *aux_mask)
 {
@@ -765,6 +906,21 @@ static const struct l2x0_of_data aurora_no_outer_data = {
         },
 };
 
+static const struct l2x0_of_data bcm_l2x0_data = {
+        .setup = pl310_of_setup,
+        .save  = pl310_save,
+        .outer_cache = {
+                .resume      = pl310_resume,
+                .inv_range   = bcm_inv_range,
+                .clean_range = bcm_clean_range,
+                .flush_range = bcm_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+        },
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
         { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
         { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
@@ -773,6 +929,8 @@ static const struct of_device_id l2x0_ids[] __initconst = {
           .data = (void *)&aurora_no_outer_data},
         { .compatible = "marvell,aurora-outer-cache",
           .data = (void *)&aurora_with_outer_data},
+        { .compatible = "bcm,bcm11351-a2-pl310-cache",
+          .data = (void *)&bcm_l2x0_data},
         {}
 };
 
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac37372ef52..b55b1015724b 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
@@ -39,33 +40,51 @@
  * non 64-bit operations.
  */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
-#define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
-
-#define ASID_TO_IDX(asid)       ((asid & ~ASID_MASK) - 1)
-#define IDX_TO_ASID(idx)        ((idx + 1) & ~ASID_MASK)
+#define NUM_USER_ASIDS          ASID_FIRST_VERSION
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
-DEFINE_PER_CPU(atomic64_t, active_asids);
+static DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask)
+{
+        int cpu;
+        unsigned long flags;
+        u64 context_id, asid;
+
+        raw_spin_lock_irqsave(&cpu_asid_lock, flags);
+        context_id = mm->context.id.counter;
+        for_each_online_cpu(cpu) {
+                if (cpu == this_cpu)
+                        continue;
+                /*
+                 * We only need to send an IPI if the other CPUs are
+                 * running the same ASID as the one being invalidated.
+                 */
+                asid = per_cpu(active_asids, cpu).counter;
+                if (asid == 0)
+                        asid = per_cpu(reserved_asids, cpu);
+                if (context_id == asid)
+                        cpumask_set_cpu(cpu, mask);
+        }
+        raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+}
+#endif
+
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-        unsigned long ttbl = __pa(swapper_pg_dir);
-        unsigned long ttbh = 0;
-
         /*
          * Set TTBR0 to swapper_pg_dir which contains only global entries. The
          * ASID is set to 0.
          */
-        asm volatile(
-        "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
-        :
-        : "r" (ttbl), "r" (ttbh));
+        cpu_set_ttbr(0, __pa(swapper_pg_dir));
         isb();
 }
 #else
@@ -128,7 +147,16 @@ static void flush_context(unsigned int cpu)
                         asid = 0;
                 } else {
                         asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
-                        __set_bit(ASID_TO_IDX(asid), asid_map);
+                        /*
+                         * If this CPU has already been through a
+                         * rollover, but hasn't run another task in
+                         * the meantime, we must preserve its reserved
+                         * ASID, as this is the only trace we have of
+                         * the process it is still running.
+                         */
+                        if (asid == 0)
+                                asid = per_cpu(reserved_asids, i);
+                        __set_bit(asid & ~ASID_MASK, asid_map);
                 }
                 per_cpu(reserved_asids, i) = asid;
         }
@@ -167,17 +195,19 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
                 /*
                  * Allocate a free ASID. If we can't find one, take a
                  * note of the currently active ASIDs and mark the TLBs
-                 * as requiring flushes.
+                 * as requiring flushes. We always count from ASID #1,
+                 * as we reserve ASID #0 to switch via TTBR0 and indicate
+                 * rollover events.
                  */
-                asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                 if (asid == NUM_USER_ASIDS) {
                         generation = atomic64_add_return(ASID_FIRST_VERSION,
                                                          &asid_generation);
                         flush_context(cpu);
-                        asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                        asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                 }
                 __set_bit(asid, asid_map);
-                asid = generation | IDX_TO_ASID(asid);
+                asid |= generation;
                 cpumask_clear(mm_cpumask(mm));
         }
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ef3e0f3aac96..7ec02961dfa0 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -250,7 +250,7 @@ static void __dma_free_buffer(struct page *page, size_t size)
 
 #ifdef CONFIG_MMU
 #ifdef CONFIG_HUGETLB_PAGE
-#error ARM Coherent DMA allocator does not (yet) support huge TLB
+#warning ARM Coherent DMA allocator does not (yet) support huge TLB
 #endif
 
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
@@ -880,10 +880,24 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
         dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
 
         /*
-         * Mark the D-cache clean for this page to avoid extra flushing.
+         * Mark the D-cache clean for these pages to avoid extra flushing.
          */
-        if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
-                set_bit(PG_dcache_clean, &page->flags);
+        if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
+                unsigned long pfn;
+                size_t left = size;
+
+                pfn = page_to_pfn(page) + off / PAGE_SIZE;
+                off %= PAGE_SIZE;
+                if (off) {
+                        pfn++;
+                        left -= PAGE_SIZE - off;
+                }
+                while (left >= PAGE_SIZE) {
+                        page = pfn_to_page(pfn++);
+                        set_bit(PG_dcache_clean, &page->flags);
+                        left -= PAGE_SIZE;
+                }
+        }
 }
 
 /**
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5dbf13f954f6..c97f7940cb95 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -491,12 +491,14 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
  * Some section permission faults need to be handled gracefully.
  * They can happen due to a __{get,put}_user during an oops.
  */
+#ifndef CONFIG_ARM_LPAE
 static int
 do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 {
         do_bad_area(addr, fsr, regs);
         return 0;
 }
+#endif /* CONFIG_ARM_LPAE */
 
 /*
  * This abort handler always returns "fault".
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 32aa5861119f..6d5ba9afb16a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <linux/hugetlb.h>
 
 #include "mm.h"
 
@@ -168,19 +169,23 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
          * coherent with the kernels mapping.
          */
         if (!PageHighMem(page)) {
-                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+                size_t page_size = PAGE_SIZE << compound_order(page);
+                __cpuc_flush_dcache_area(page_address(page), page_size);
         } else {
-                void *addr;
-
+                unsigned long i;
                 if (cache_is_vipt_nonaliasing()) {
-                        addr = kmap_atomic(page);
-                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                        kunmap_atomic(addr);
-                } else {
-                        addr = kmap_high_get(page);
-                        if (addr) {
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
+                                void *addr = kmap_atomic(page);
                                 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                                kunmap_high(page);
+                                kunmap_atomic(addr);
+                        }
+                } else {
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
+                                void *addr = kmap_high_get(page);
+                                if (addr) {
+                                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                                        kunmap_high(page);
+                                }
                         }
                 }
         }
@@ -287,7 +292,7 @@ void flush_dcache_page(struct page *page)
         mapping = page_mapping(page);
 
         if (!cache_ops_need_broadcast() &&
-            mapping && !mapping_mapped(mapping))
+            mapping && !page_mapped(page))
                 clear_bit(PG_dcache_clean, &page->flags);
         else {
                 __flush_dcache_page(mapping, page);
diff --git a/arch/arm/mm/fsr-3level.c b/arch/arm/mm/fsr-3level.c
index 05a4e9431836..ab4409a2307e 100644
--- a/arch/arm/mm/fsr-3level.c
+++ b/arch/arm/mm/fsr-3level.c
@@ -9,11 +9,11 @@ static struct fsr_info fsr_info[] = {
         { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "level 3 translation fault"     },
         { do_bad,               SIGBUS,  0,             "reserved access flag fault"    },
         { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 access flag fault"     },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 access flag fault"     },
         { do_bad,               SIGBUS,  0,             "reserved permission fault"     },
         { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 permission fault"      },
-        { do_sect_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 permission fault"      },
         { do_bad,               SIGBUS,  0,             "synchronous external abort"    },
         { do_bad,               SIGBUS,  0,             "asynchronous external abort"   },
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
new file mode 100644
index 000000000000..3d1e4a205b0b
--- /dev/null
+++ b/arch/arm/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h and Bill Carson's patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+/*
+ * On ARM, huge pages are backed by pmd's rather than pte's, so we do a lot
+ * of type casting from pmd_t * to pte_t *.
+ */
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        if (pgd_present(*pgd)) {
+                pud = pud_offset(pgd, addr);
+                if (pud_present(*pud))
+                        pmd = pmd_offset(pud, addr);
+        }
+
+        return (pte_t *)pmd;
+}
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+                              int write)
+{
+        return ERR_PTR(-EINVAL);
+}
+
+int pud_huge(pud_t pud)
+{
+        return 0;
+}
+
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+        return 0;
+}
+
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+                        unsigned long addr, unsigned long sz)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pte_t *pte = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        pud = pud_alloc(mm, pgd, addr);
+        if (pud)
+                pte = (pte_t *)pmd_alloc(mm, pud, addr);
+
+        return pte;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+                pmd_t *pmd, int write)
+{
+        struct page *page;
+
+        page = pte_page(*(pte_t *)pmd);
+        if (page)
+                page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+        return page;
+}
+
+int pmd_huge(pmd_t pmd)
+{
+        return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc01fcdf..6833cbead6cc 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 
 #include "mm.h"
 
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
 static int __init early_initrd(char *p)
 {
-        unsigned long start, size;
+        phys_addr_t start;
+        unsigned long size;
         char *endp;
 
         start = memparse(p, &endp);
@@ -350,14 +351,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
         if (phys_initrd_size &&
             !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
+                       (u64)phys_initrd_start, phys_initrd_size);
                 phys_initrd_start = phys_initrd_size = 0;
         }
         if (phys_initrd_size &&
             memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+                       (u64)phys_initrd_start, phys_initrd_size);
                 phys_initrd_start = phys_initrd_size = 0;
         }
         if (phys_initrd_size) {
@@ -442,7 +443,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
         struct page *start_pg, *end_pg;
-        unsigned long pg, pgend;
+        phys_addr_t pg, pgend;
 
         /*
          * Convert start_pfn/end_pfn to a struct page pointer.
@@ -454,8 +455,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
          * Convert to physical addresses, and
          * round start upwards and end downwards.
          */
-        pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
-        pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+        pg = PAGE_ALIGN(__pa(start_pg));
+        pgend = __pa(end_pg) & PAGE_MASK;
 
         /*
          * If there are free pages between these,
@@ -582,9 +583,6 @@ static void __init free_highpages(void)
  */
 void __init mem_init(void)
 {
-        unsigned long reserved_pages, free_pages;
-        struct memblock_region *reg;
-        int i;
 #ifdef CONFIG_HAVE_TCM
         /* These pointers are filled in on TCM detection */
         extern u32 dtcm_end;
@@ -595,57 +593,16 @@ void __init mem_init(void)
 
         /* this will put all unused low memory onto the freelists */
         free_unused_memmap(&meminfo);
-
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
 
 #ifdef CONFIG_SA1111
         /* now that our DMA memory is actually so designated, we can free it */
-        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
+        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, -1, NULL);
 #endif
 
         free_highpages();
 
-        reserved_pages = free_pages = 0;
-
-        for_each_bank(i, &meminfo) {
-                struct membank *bank = &meminfo.bank[i];
-                unsigned int pfn1, pfn2;
-                struct page *page, *end;
-
-                pfn1 = bank_pfn_start(bank);
-                pfn2 = bank_pfn_end(bank);
-
-                page = pfn_to_page(pfn1);
-                end  = pfn_to_page(pfn2 - 1) + 1;
-
-                do {
-                        if (PageReserved(page))
-                                reserved_pages++;
-                        else if (!page_count(page))
-                                free_pages++;
-                        page++;
-                } while (page < end);
-        }
-
-        /*
-         * Since our memory may not be contiguous, calculate the
-         * real number of pages we have in this system
-         */
-        printk(KERN_INFO "Memory:");
-        num_physpages = 0;
-        for_each_memblock(memory, reg) {
-                unsigned long pages = memblock_region_memory_end_pfn(reg) -
-                        memblock_region_memory_base_pfn(reg);
-                num_physpages += pages;
-                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-        }
-        printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                free_pages << (PAGE_SHIFT-10),
-                reserved_pages << (PAGE_SHIFT-10),
-                totalhigh_pages << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -711,7 +668,7 @@ void __init mem_init(void)
         BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE      > PAGE_OFFSET);
 #endif
 
-        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+        if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
                 extern int sysctl_overcommit_memory;
                 /*
                  * On a machine this small we won't get
@@ -728,12 +685,12 @@ void free_initmem(void)
         extern char __tcm_start, __tcm_end;
 
         poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
-        free_reserved_area(&__tcm_start, &__tcm_end, 0, "TCM link");
+        free_reserved_area(&__tcm_start, &__tcm_end, -1, "TCM link");
 #endif
 
         poison_init_mem(__init_begin, __init_end - __init_begin);
         if (!machine_is_integrator() && !machine_is_cintegrator())
-                free_initmem_default(0);
+                free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -744,7 +701,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd) {
                 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                free_reserved_area(start, end, 0, "initrd");
+                free_reserved_area((void *)start, (void *)end, -1, "initrd");
         }
 }
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 04d9006eab1f..f123d6eb074b 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -331,10 +331,10 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         return (void __iomem *) (offset + addr);
 }
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
         unsigned int mtype, void *caller)
 {
-        unsigned long last_addr;
+        phys_addr_t last_addr;
         unsigned long offset = phys_addr & ~PAGE_MASK;
         unsigned long pfn = __phys_to_pfn(phys_addr);
 
@@ -367,12 +367,12 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
                                       unsigned int, void *) =
         __arm_ioremap_caller;
 
 void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__arm_ioremap(phys_addr_t phys_addr, size_t size, unsigned int mtype)
 {
         return arch_ioremap_caller(phys_addr, size, mtype,
                 __builtin_return_address(0));
@@ -387,7 +387,7 @@ EXPORT_SYMBOL(__arm_ioremap);
  * CONFIG_GENERIC_ALLOCATOR for allocating external memory.
  */
 void __iomem *
-__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
+__arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
 {
         unsigned int mtype;
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index d1d1cefa1f93..d7229d28c7f8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -675,7 +675,8 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-        unsigned long end, unsigned long phys, const struct mem_type *type)
+                                  unsigned long end, phys_addr_t phys,
+                                  const struct mem_type *type)
 {
         pud_t *pud = pud_offset(pgd, addr);
         unsigned long next;
@@ -989,27 +990,28 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
+        phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
-                *bank = meminfo.bank[i];
+                phys_addr_t size_limit;
 
-                if (bank->start > ULONG_MAX)
-                        highmem = 1;
+                *bank = meminfo.bank[i];
+                size_limit = bank->size;
 
-#ifdef CONFIG_HIGHMEM
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET)
+                if (bank->start >= vmalloc_limit)
                         highmem = 1;
+                else
+                        size_limit = vmalloc_limit - bank->start;
 
                 bank->highmem = highmem;
 
+#ifdef CONFIG_HIGHMEM
                 /*
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
                  */
-                if (!highmem && __va(bank->start) < vmalloc_min &&
-                    bank->size > vmalloc_min - __va(bank->start)) {
+                if (!highmem && bank->size > size_limit) {
                         if (meminfo.nr_banks >= NR_BANKS) {
                                 printk(KERN_CRIT "NR_BANKS too low, "
                                                  "ignoring high memory\n");
@@ -1018,16 +1020,14 @@ void __init sanity_check_meminfo(void)
                                         (meminfo.nr_banks - i) * sizeof(*bank));
                                 meminfo.nr_banks++;
                                 i++;
-                                bank[1].size -= vmalloc_min - __va(bank->start);
-                                bank[1].start = __pa(vmalloc_min - 1) + 1;
+                                bank[1].size -= size_limit;
+                                bank[1].start = vmalloc_limit;
                                 bank[1].highmem = highmem = 1;
                                 j++;
                         }
-                        bank->size = vmalloc_min - __va(bank->start);
+                        bank->size = size_limit;
                 }
 #else
-                bank->highmem = highmem;
-
                 /*
                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
                  */
@@ -1040,31 +1040,16 @@ void __init sanity_check_meminfo(void)
                 }
 
                 /*
-                 * Check whether this memory bank would entirely overlap
-                 * the vmalloc area.
-                 */
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET) {
-                        printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-                               "(vmalloc region overlap).\n",
-                               (unsigned long long)bank->start,
-                               (unsigned long long)bank->start + bank->size - 1);
-                        continue;
-                }
-
-                /*
                  * Check whether this memory bank would partially overlap
                  * the vmalloc area.
                  */
-                if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
-                    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
-                        unsigned long newsize = vmalloc_min - __va(bank->start);
+                if (bank->size > size_limit) {
                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
                                "to -%.8llx (vmalloc region overlap).\n",
                                (unsigned long long)bank->start,
                                (unsigned long long)bank->start + bank->size - 1,
-                               (unsigned long long)bank->start + newsize - 1);
-                        bank->size = newsize;
+                               (unsigned long long)bank->start + size_limit - 1);
+                        bank->size = size_limit;
                 }
 #endif
                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 5a3aba614a40..1fa50100ab6a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -8,6 +8,7 @@
 #include <linux/pagemap.h>
 #include <linux/io.h>
 #include <linux/memblock.h>
+#include <linux/kernel.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -15,9 +16,260 @@
 #include <asm/setup.h>
 #include <asm/traps.h>
 #include <asm/mach/arch.h>
+#include <asm/cputype.h>
+#include <asm/mpu.h>
 
 #include "mm.h"
 
+#ifdef CONFIG_ARM_MPU
+struct mpu_rgn_info mpu_rgn_info;
+
+/* Region number */
+static void rgnr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
+}
+
+/* Data-side / unified region attributes */
+
+/* Region access control register */
+static void dracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
+}
+
+/* Region size register */
+static void drsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
+}
+
+/* Region base address register */
+static void drbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
+}
+
+static u32 drbar_read(void)
+{
+        u32 v;
+        asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
+        return v;
+}
+/* Optional instruction-side region attributes */
+
+/* I-side Region access control register */
+static void iracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
+}
+
+/* I-side Region size register */
+static void irsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
+}
+
+/* I-side Region base address register */
+static void irbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
+}
+
+static unsigned long irbar_read(void)
+{
+        unsigned long v;
+        asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
+        return v;
+}
+
+/* MPU initialisation functions */
+void __init sanity_check_meminfo_mpu(void)
+{
+        int i;
+        struct membank *bank = meminfo.bank;
+        phys_addr_t phys_offset = PHYS_OFFSET;
+        phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
+
+        /* Initially only use memory continuous from PHYS_OFFSET */
+        if (bank_phys_start(&bank[0]) != phys_offset)
+                panic("First memory bank must be contiguous from PHYS_OFFSET");
+
+        /* Banks have already been sorted by start address */
+        for (i = 1; i < meminfo.nr_banks; i++) {
+                if (bank[i].start <= bank_phys_end(&bank[0]) &&
+                    bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
+                        bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
+                } else {
+                        pr_notice("Ignoring RAM after 0x%.8lx. "
+                        "First non-contiguous (ignored) bank start: 0x%.8lx\n",
+                                (unsigned long)bank_phys_end(&bank[0]),
+                                (unsigned long)bank_phys_start(&bank[i]));
+                        break;
+                }
+        }
+        /* All contiguous banks are now merged in to the first bank */
+        meminfo.nr_banks = 1;
+        specified_mem_size = bank[0].size;
+
+        /*
+         * MPU has curious alignment requirements: Size must be power of 2, and
+         * region start must be aligned to the region size
+         */
+        if (phys_offset != 0)
+                pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
+
+        /*
+         * Maximum aligned region might overflow phys_addr_t if phys_offset is
+         * 0. Hence we keep everything below 4G until we take the smaller of
+         * the aligned_region_size and rounded_mem_size, one of which is
+         * guaranteed to be smaller than the maximum physical address.
+         */
+        aligned_region_size = (phys_offset - 1) ^ (phys_offset);
+        /* Find the max power-of-two sized region that fits inside our bank */
+        rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
+
+        /* The actual region size is the smaller of the two */
+        aligned_region_size = aligned_region_size < rounded_mem_size
+                                ? aligned_region_size + 1
+                                : rounded_mem_size + 1;
+
+        if (aligned_region_size != specified_mem_size)
+                pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
+                                (unsigned long)specified_mem_size,
+                                (unsigned long)aligned_region_size);
+
+        meminfo.bank[0].size = aligned_region_size;
+        pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
+                (unsigned long)phys_offset,
+                (unsigned long)aligned_region_size,
+                (unsigned long)bank_phys_end(&bank[0]));
+
+}
+
+static int mpu_present(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
+}
+
+static int mpu_max_regions(void)
+{
+        /*
+         * We don't support a different number of I/D side regions so if we
+         * have separate instruction and data memory maps then return
+         * whichever side has a smaller number of supported regions.
+         */
+        u32 dregions, iregions, mpuir;
+        mpuir = read_cpuid(CPUID_MPUIR);
+
+        dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
+
+        /* Check for separate d-side and i-side memory maps */
+        if (mpuir & MPUIR_nU)
+                iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
+
+        /* Use the smallest of the two maxima */
+        return min(dregions, iregions);
+}
+
+static int mpu_iside_independent(void)
+{
+        /* MPUIR.nU specifies whether there is *not* a unified memory map */
+        return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
+}
+
+static int mpu_min_region_order(void)
+{
+        u32 drbar_result, irbar_result;
+        /* We've kept a region free for this probing */
+        rgnr_write(MPU_PROBE_REGION);
+        isb();
+        /*
+         * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
+         * region order
+        */
+        drbar_write(0xFFFFFFFC);
+        drbar_result = irbar_result = drbar_read();
+        drbar_write(0x0);
+        /* If the MPU is non-unified, we use the larger of the two minima*/
+        if (mpu_iside_independent()) {
+                irbar_write(0xFFFFFFFC);
+                irbar_result = irbar_read();
+                irbar_write(0x0);
+        }
+        isb(); /* Ensure that MPU region operations have completed */
+        /* Return whichever result is larger */
+        return __ffs(max(drbar_result, irbar_result));
+}
+
+static int mpu_setup_region(unsigned int number, phys_addr_t start,
+                        unsigned int size_order, unsigned int properties)
+{
+        u32 size_data;
+
+        /* We kept a region free for probing resolution of MPU regions*/
+        if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
+                return -ENOENT;
+
+        if (size_order > 32)
+                return -ENOMEM;
+
+        if (size_order < mpu_min_region_order())
+                return -ENOMEM;
+
+        /* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
+        size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
+
+        dsb(); /* Ensure all previous data accesses occur with old mappings */
+        rgnr_write(number);
+        isb();
+        drbar_write(start);
+        dracr_write(properties);
+        isb(); /* Propagate properties before enabling region */
+        drsr_write(size_data);
+
+        /* Check for independent I-side registers */
+        if (mpu_iside_independent()) {
+                irbar_write(start);
+                iracr_write(properties);
+                isb();
+                irsr_write(size_data);
+        }
+        isb();
+
+        /* Store region info (we treat i/d side the same, so only store d) */
+        mpu_rgn_info.rgns[number].dracr = properties;
+        mpu_rgn_info.rgns[number].drbar = start;
+        mpu_rgn_info.rgns[number].drsr = size_data;
+        return 0;
+}
+
+/*
+* Set up default MPU regions, doing nothing if there is no MPU
+*/
+void __init mpu_setup(void)
+{
+        int region_err;
+        if (!mpu_present())
+                return;
+
+        region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
+                                        ilog2(meminfo.bank[0].size),
+                                        MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
+        if (region_err) {
+                panic("MPU region initialization failure! %d", region_err);
+        } else {
+                pr_info("Using ARMv7 PMSA Compliant MPU. "
+                         "Region independence: %s, Max regions: %d\n",
+                        mpu_iside_independent() ? "Yes" : "No",
+                        mpu_max_regions());
+        }
+}
+#else
+static void sanity_check_meminfo_mpu(void) {}
+static void __init mpu_setup(void) {}
+#endif /* CONFIG_ARM_MPU */
+
 void __init arm_mm_memblock_reserve(void)
 {
 #ifndef CONFIG_CPU_V7M
@@ -37,7 +289,9 @@ void __init arm_mm_memblock_reserve(void)
 
 void __init sanity_check_meminfo(void)
 {
-        phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+        phys_addr_t end;
+        sanity_check_meminfo_mpu();
+        end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
         high_memory = __va(end - 1) + 1;
 }
 
@@ -48,6 +302,7 @@ void __init sanity_check_meminfo(void)
 void __init paging_init(struct machine_desc *mdesc)
 {
         early_trap_init((void *)CONFIG_VECTORS_BASE);
+        mpu_setup();
         bootmem_init();
 }
 
@@ -94,16 +349,16 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
         return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
                             unsigned int mtype)
 {
         return (void __iomem *)phys_addr;
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                    unsigned int mtype, void *caller)
 {
         return __arm_ioremap(phys_addr, size, mtype);
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 919405e20b80..2d1ef87328a1 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -140,8 +140,10 @@ ENTRY(cpu_v6_set_pte_ext)
 ENTRY(cpu_v6_do_suspend)
         stmfd   sp!, {r4 - r9, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+#endif
         mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
         mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
         mrc     p15, 0, r9, c1, c0, 0   @ control register
@@ -158,14 +160,16 @@ ENTRY(cpu_v6_do_resume)
         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
         ldmia   r0, {r4 - r9}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
         mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
         mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+#endif
         mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
         mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
-        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mcr     p15, 0, ip, c7, c5, 4   @ ISB
         mov     r0, r9                  @ control register
         b       cpu_resume_mmu
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 363027e811d6..5ffe1956c6d9 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,14 @@
 #define TTB_FLAGS_SMP   (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP   (PMD_SECT_WBWA|PMD_SECT_S)
 
+#ifndef __ARMEB__
+#  define rpgdl r0
+#  define rpgdh r1
+#else
+#  define rpgdl r1
+#  define rpgdh r0
+#endif
+
 /*
  * cpu_v7_switch_mm(pgd_phys, tsk)
  *
@@ -47,10 +55,10 @@
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-        mmid    r1, r1                          @ get mm->context.id
-        asid    r3, r1
-        mov     r3, r3, lsl #(48 - 32)          @ ASID
-        mcrr    p15, 0, r0, r3, c2              @ set TTB 0
+        mmid    r2, r2
+        asid    r2, r2
+        orr     rpgdh, rpgdh, r2, lsl #(48 - 32)        @ upper 32-bits of pgd
+        mcrr    p15, 0, rpgdl, rpgdh, c2                @ set TTB 0
         isb
 #endif
         mov     pc, lr
@@ -106,7 +114,8 @@ ENDPROC(cpu_v7_set_pte_ext)
          */
         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
         ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
-        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+        mov     \tmp, \tmp, lsr #ARCH_PGD_SHIFT
+        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
         mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
         orr     \tmp, \tmp, #TTB_EAE
         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
@@ -114,27 +123,21 @@ ENDPROC(cpu_v7_set_pte_ext)
         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
         /*
-         * TTBR0/TTBR1 split (PAGE_OFFSET):
-         *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
-         *   0x80000000: T0SZ = 0, T1SZ = 1
-         *   0xc0000000: T0SZ = 0, T1SZ = 2
-         *
-         * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-         * booting secondary CPUs would end up using TTBR1 for the identity
-         * mapping set up in TTBR0.
+         * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
+         * otherwise booting secondary CPUs would end up using TTBR1 for the
+         * identity mapping set up in TTBR0.
          */
-        bhi     9001f                           @ PHYS_OFFSET > PAGE_OFFSET?
-        orr     \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-        /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-        add     \ttbr1, \ttbr1, #1 << 4         @ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-        /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-        add     \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
-#endif
-        /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:   mcr     p15, 0, \tmp, c2, c0, 2         @ TTB control register
-        mcrr    p15, 1, \ttbr1, \zero, c2       @ load TTBR1
+        orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
+        mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
+        mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
+        addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
         .endm
 
         __CPUINIT
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e35fec34453e..7ef3ad05df39 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -98,9 +98,11 @@ ENTRY(cpu_v7_do_suspend)
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         stmia   r0!, {r4 - r5}
+#ifdef CONFIG_MMU
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
+#endif
         mrc     p15, 0, r8, c1, c0, 0   @ Control register
         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
@@ -110,13 +112,14 @@ ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
         mov     ip, #0
-        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
         ldmia   r0!, {r4 - r5}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         ldmia   r0, {r6 - r11}
+#ifdef CONFIG_MMU
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 #ifndef CONFIG_ARM_LPAE
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +128,15 @@ ENTRY(cpu_v7_do_resume)
         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
-        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r9                  @ Is it already set?
-        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
-        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
+#endif  /* CONFIG_MMU */
+        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         isb
         dsb
         mov     r0, r8                  @ control register
@@ -178,7 +182,8 @@ ENDPROC(cpu_pj4b_do_idle)
  */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
-        mov     r10, #(1 << 0)                  @ TLB ops broadcasting
+__v7_cr7mp_setup:
+        mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
         b       1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
@@ -443,6 +448,16 @@ __v7_pj4b_proc_info:
 #endif
 
         /*
+         * ARM Ltd. Cortex R7 processor.
+         */
+        .type   __v7_cr7mp_proc_info, #object
+__v7_cr7mp_proc_info:
+        .long   0x410fc170
+        .long   0xff0ffff0
+        __v7_proc __v7_cr7mp_setup
+        .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
+
+        /*
          * ARM Ltd. Cortex A7 processor.
          */
         .type   __v7_ca7mp_proc_info, #object
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
index 1ff6a37e893c..a4d1f8de3b5b 100644
--- a/arch/arm/plat-iop/adma.c
+++ b/arch/arm/plat-iop/adma.c
@@ -192,12 +192,10 @@ static int __init iop3xx_adma_cap_init(void)
 
         #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
         #else
         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
         #endif
 
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c019b7aaf776..c66d163d7a2a 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -666,14 +666,9 @@ void __init orion_xor0_init(unsigned long mapbase_low,
         orion_xor0_shared_resources[3].start = irq_1;
         orion_xor0_shared_resources[3].end = irq_1;
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
         dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
 
-        dma_cap_set(DMA_MEMSET, orion_xor0_channels_data[1].cap_mask);
         dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
 
@@ -732,14 +727,9 @@ void __init orion_xor1_init(unsigned long mapbase_low,
         orion_xor1_shared_resources[3].start = irq_1;
         orion_xor1_shared_resources[3].end = irq_1;
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
         dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
 
-        dma_cap_set(DMA_MEMSET, orion_xor1_channels_data[1].cap_mask);
         dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
 
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 249fe6333e18..6816192a7561 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -426,7 +426,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 if (!(cause & (1 << i)))
                         continue;
 
-                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                type = irq_get_trigger_type(irq);
                 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                         /* Swap polarity (race with GPIO line) */
                         u32 polarity;
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index d7e17150028a..7231c8e4975e 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -285,7 +285,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
                 s3c_freq_dbg("%s: { %d = %u kHz }\n",
                              __func__, index, freq);
 
-                table[index].index = index;
+                table[index].driver_data = index;
                 table[index].frequency = freq;
         }
 
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index b178d44e9eaa..2677bc3762d7 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -11,8 +11,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        __INIT
-
 /*
  * Realview/Versatile Express specific entry point for secondary CPUs.
  * This provides a "holding pen" into which all secondary cores are held