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authorTrond Myklebust <trond.myklebust@primarydata.com>2015-04-23 15:16:37 -0400
committerTrond Myklebust <trond.myklebust@primarydata.com>2015-04-23 15:16:37 -0400
commitf139b6c676c7e49b66016b28bf3f8ec5c54be891 (patch)
tree742f00e431dded1daf642b44f4c199b318f255dc /arch/arm
parent21330b667070fd64b2340d8d31c1b0800df78ec8 (diff)
parentd654788e98f74f2df8dfc6079fa314938f739486 (diff)
Merge tag 'nfs-rdma-for-4.1-1' of git://git.linux-nfs.org/projects/anna/nfs-rdma
NFS: NFSoRDMA Client Changes This patch series creates an operation vector for each of the different memory registration modes. This should make it easier to one day increase credit limit, rsize, and wsize. Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi8
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts8
-rw-r--r--arch/arm/boot/dts/am335x-lxm.dts4
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi5
-rw-r--r--arch/arm/boot/dts/dm8168-evm.dts19
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi18
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts10
-rw-r--r--arch/arm/boot/dts/dra7.dtsi2
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts10
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi90
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4-cpu-thermal.dtsi52
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi45
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts19
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts57
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi38
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi64
-rw-r--r--arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts15
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi12
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi44
-rw-r--r--arch/arm/boot/dts/exynos5420-trip-points.dtsi35
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi33
-rw-r--r--arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos5440-trip-points.dtsi25
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi18
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts2
-rw-r--r--arch/arm/boot/dts/omap3.dtsi4
-rw-r--r--arch/arm/boot/dts/omap5-core-thermal.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5-gpu-thermal.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi4
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi41
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi1
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi3
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi9
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi8
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts16
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi3
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi3
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi3
-rw-r--r--arch/arm/configs/at91_dt_defconfig1
-rw-r--r--arch/arm/configs/multi_v7_defconfig2
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/configs/sama5_defconfig2
-rw-r--r--arch/arm/configs/sunxi_defconfig1
-rw-r--r--arch/arm/configs/vexpress_defconfig2
-rw-r--r--arch/arm/crypto/aesbs-core.S_shipped12
-rw-r--r--arch/arm/crypto/bsaes-armv7.pl12
-rw-r--r--arch/arm/include/asm/kvm_mmu.h13
-rw-r--r--arch/arm/include/debug/at91.S5
-rw-r--r--arch/arm/kernel/setup.c5
-rw-r--r--arch/arm/kvm/mmu.c75
-rw-r--r--arch/arm/mach-at91/pm.c22
-rw-r--r--arch/arm/mach-at91/pm.h2
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S80
-rw-r--r--arch/arm/mach-exynos/platsmp.c3
-rw-r--r--arch/arm/mach-exynos/pm_domains.c28
-rw-r--r--arch/arm/mach-exynos/suspend.c4
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c5
-rw-r--r--arch/arm/mach-omap2/id.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c103
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/prm44xx.c4
-rw-r--r--arch/arm/mach-pxa/idp.c1
-rw-r--r--arch/arm/mach-pxa/irq.c111
-rw-r--r--arch/arm/mach-pxa/lpd270.c2
-rw-r--r--arch/arm/mach-pxa/zeus.c2
-rw-r--r--arch/arm/mach-sa1100/neponset.c4
-rw-r--r--arch/arm/mach-sa1100/pleb.c2
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/socfpga.c5
-rw-r--r--arch/arm/mach-sti/board-dt.c1
-rw-r--r--arch/arm/mach-sunxi/Kconfig8
-rw-r--r--arch/arm/mm/cache-l2x0.c33
-rw-r--r--arch/arm/mm/dma-mapping.c2
-rw-r--r--arch/arm/mm/fault.c1
-rw-r--r--arch/arm/mm/pageattr.c5
-rw-r--r--arch/arm/plat-omap/dmtimer.c15
92 files changed, 1058 insertions, 371 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a2bc9b..cf4c0c99aa25 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -619,6 +619,7 @@ config ARCH_PXA
619 select GENERIC_CLOCKEVENTS 619 select GENERIC_CLOCKEVENTS
620 select GPIO_PXA 620 select GPIO_PXA
621 select HAVE_IDE 621 select HAVE_IDE
622 select IRQ_DOMAIN
622 select MULTI_IRQ_HANDLER 623 select MULTI_IRQ_HANDLER
623 select PLAT_PXA 624 select PLAT_PXA
624 select SPARSE_IRQ 625 select SPARSE_IRQ
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7f99cd652203..eb7bb511f853 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -150,6 +150,7 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin
150machine-$(CONFIG_ARCH_CLPS711X) += clps711x 150machine-$(CONFIG_ARCH_CLPS711X) += clps711x
151machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx 151machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
152machine-$(CONFIG_ARCH_DAVINCI) += davinci 152machine-$(CONFIG_ARCH_DAVINCI) += davinci
153machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
153machine-$(CONFIG_ARCH_DOVE) += dove 154machine-$(CONFIG_ARCH_DOVE) += dove
154machine-$(CONFIG_ARCH_EBSA110) += ebsa110 155machine-$(CONFIG_ARCH_EBSA110) += ebsa110
155machine-$(CONFIG_ARCH_EFM32) += efm32 156machine-$(CONFIG_ARCH_EFM32) += efm32
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2c6248d9a9ef..c3255e0c90aa 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -301,3 +301,11 @@
301 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 301 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
302 cd-inverted; 302 cd-inverted;
303}; 303};
304
305&aes {
306 status = "okay";
307};
308
309&sham {
310 status = "okay";
311};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 83d40f7655e5..6b8493720424 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -24,11 +24,3 @@
24&mmc1 { 24&mmc1 {
25 vmmc-supply = <&ldo3_reg>; 25 vmmc-supply = <&ldo3_reg>;
26}; 26};
27
28&sham {
29 status = "okay";
30};
31
32&aes {
33 status = "okay";
34};
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index 7266a00aab2e..5c5667a3624d 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -328,6 +328,10 @@
328 dual_emac_res_vlan = <3>; 328 dual_emac_res_vlan = <3>;
329}; 329};
330 330
331&phy_sel {
332 rmii-clock-ext;
333};
334
331&mac { 335&mac {
332 pinctrl-names = "default", "sleep"; 336 pinctrl-names = "default", "sleep";
333 pinctrl-0 = <&cpsw_default>; 337 pinctrl-0 = <&cpsw_default>;
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..071b56aa0c7e 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -99,7 +99,7 @@
99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
100 #clock-cells = <0>; 100 #clock-cells = <0>;
101 compatible = "ti,gate-clock"; 101 compatible = "ti,gate-clock";
102 clocks = <&dpll_per_m2_ck>; 102 clocks = <&l4ls_gclk>;
103 ti,bit-shift = <0>; 103 ti,bit-shift = <0>;
104 reg = <0x0664>; 104 reg = <0x0664>;
105 }; 105 };
@@ -107,7 +107,7 @@
107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
108 #clock-cells = <0>; 108 #clock-cells = <0>;
109 compatible = "ti,gate-clock"; 109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>; 110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <1>; 111 ti,bit-shift = <1>;
112 reg = <0x0664>; 112 reg = <0x0664>;
113 }; 113 };
@@ -115,7 +115,7 @@
115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
116 #clock-cells = <0>; 116 #clock-cells = <0>;
117 compatible = "ti,gate-clock"; 117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>; 118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <2>; 119 ti,bit-shift = <2>;
120 reg = <0x0664>; 120 reg = <0x0664>;
121 }; 121 };
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..cfb49686ab6a 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -107,7 +107,7 @@
107 ehrpwm0_tbclk: ehrpwm0_tbclk { 107 ehrpwm0_tbclk: ehrpwm0_tbclk {
108 #clock-cells = <0>; 108 #clock-cells = <0>;
109 compatible = "ti,gate-clock"; 109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>; 110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <0>; 111 ti,bit-shift = <0>;
112 reg = <0x0664>; 112 reg = <0x0664>;
113 }; 113 };
@@ -115,7 +115,7 @@
115 ehrpwm1_tbclk: ehrpwm1_tbclk { 115 ehrpwm1_tbclk: ehrpwm1_tbclk {
116 #clock-cells = <0>; 116 #clock-cells = <0>;
117 compatible = "ti,gate-clock"; 117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>; 118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <1>; 119 ti,bit-shift = <1>;
120 reg = <0x0664>; 120 reg = <0x0664>;
121 }; 121 };
@@ -123,7 +123,7 @@
123 ehrpwm2_tbclk: ehrpwm2_tbclk { 123 ehrpwm2_tbclk: ehrpwm2_tbclk {
124 #clock-cells = <0>; 124 #clock-cells = <0>;
125 compatible = "ti,gate-clock"; 125 compatible = "ti,gate-clock";
126 clocks = <&dpll_per_m2_ck>; 126 clocks = <&l4ls_gclk>;
127 ti,bit-shift = <2>; 127 ti,bit-shift = <2>;
128 reg = <0x0664>; 128 reg = <0x0664>;
129 }; 129 };
@@ -131,7 +131,7 @@
131 ehrpwm3_tbclk: ehrpwm3_tbclk { 131 ehrpwm3_tbclk: ehrpwm3_tbclk {
132 #clock-cells = <0>; 132 #clock-cells = <0>;
133 compatible = "ti,gate-clock"; 133 compatible = "ti,gate-clock";
134 clocks = <&dpll_per_m2_ck>; 134 clocks = <&l4ls_gclk>;
135 ti,bit-shift = <4>; 135 ti,bit-shift = <4>;
136 reg = <0x0664>; 136 reg = <0x0664>;
137 }; 137 };
@@ -139,7 +139,7 @@
139 ehrpwm4_tbclk: ehrpwm4_tbclk { 139 ehrpwm4_tbclk: ehrpwm4_tbclk {
140 #clock-cells = <0>; 140 #clock-cells = <0>;
141 compatible = "ti,gate-clock"; 141 compatible = "ti,gate-clock";
142 clocks = <&dpll_per_m2_ck>; 142 clocks = <&l4ls_gclk>;
143 ti,bit-shift = <5>; 143 ti,bit-shift = <5>;
144 reg = <0x0664>; 144 reg = <0x0664>;
145 }; 145 };
@@ -147,7 +147,7 @@
147 ehrpwm5_tbclk: ehrpwm5_tbclk { 147 ehrpwm5_tbclk: ehrpwm5_tbclk {
148 #clock-cells = <0>; 148 #clock-cells = <0>;
149 compatible = "ti,gate-clock"; 149 compatible = "ti,gate-clock";
150 clocks = <&dpll_per_m2_ck>; 150 clocks = <&l4ls_gclk>;
151 ti,bit-shift = <6>; 151 ti,bit-shift = <6>;
152 reg = <0x0664>; 152 reg = <0x0664>;
153 }; 153 };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index fff0ee69aab4..e7f0a4ae271c 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -494,12 +494,12 @@
494 494
495 pinctrl_usart3_rts: usart3_rts-0 { 495 pinctrl_usart3_rts: usart3_rts-0 {
496 atmel,pins = 496 atmel,pins =
497 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ 497 <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
498 }; 498 };
499 499
500 pinctrl_usart3_cts: usart3_cts-0 { 500 pinctrl_usart3_cts: usart3_cts-0 {
501 atmel,pins = 501 atmel,pins =
502 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ 502 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
503 }; 503 };
504 }; 504 };
505 505
@@ -853,7 +853,7 @@
853 }; 853 };
854 854
855 usb1: gadget@fffa4000 { 855 usb1: gadget@fffa4000 {
856 compatible = "atmel,at91rm9200-udc"; 856 compatible = "atmel,at91sam9260-udc";
857 reg = <0xfffa4000 0x4000>; 857 reg = <0xfffa4000 0x4000>;
858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
859 clocks = <&udc_clk>, <&udpck>; 859 clocks = <&udc_clk>, <&udpck>;
@@ -976,7 +976,6 @@
976 atmel,watchdog-type = "hardware"; 976 atmel,watchdog-type = "hardware";
977 atmel,reset-type = "all"; 977 atmel,reset-type = "all";
978 atmel,dbg-halt; 978 atmel,dbg-halt;
979 atmel,idle-halt;
980 status = "disabled"; 979 status = "disabled";
981 }; 980 };
982 981
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index e247b0b5fdab..d55fdf2487ef 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -124,11 +124,12 @@
124 }; 124 };
125 125
126 usb1: gadget@fffa4000 { 126 usb1: gadget@fffa4000 {
127 compatible = "atmel,at91rm9200-udc"; 127 compatible = "atmel,at91sam9261-udc";
128 reg = <0xfffa4000 0x4000>; 128 reg = <0xfffa4000 0x4000>;
129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
130 clocks = <&usb>, <&udc_clk>, <&udpck>; 130 clocks = <&udc_clk>, <&udpck>;
131 clock-names = "usb_clk", "udc_clk", "udpck"; 131 clock-names = "pclk", "hclk";
132 atmel,matrix = <&matrix>;
132 status = "disabled"; 133 status = "disabled";
133 }; 134 };
134 135
@@ -262,7 +263,7 @@
262 }; 263 };
263 264
264 matrix: matrix@ffffee00 { 265 matrix: matrix@ffffee00 {
265 compatible = "atmel,at91sam9260-bus-matrix"; 266 compatible = "atmel,at91sam9260-bus-matrix", "syscon";
266 reg = <0xffffee00 0x200>; 267 reg = <0xffffee00 0x200>;
267 }; 268 };
268 269
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1f67bb4c144e..fce301c4e9d6 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -69,7 +69,7 @@
69 69
70 sram1: sram@00500000 { 70 sram1: sram@00500000 {
71 compatible = "mmio-sram"; 71 compatible = "mmio-sram";
72 reg = <0x00300000 0x4000>; 72 reg = <0x00500000 0x4000>;
73 }; 73 };
74 74
75 ahb { 75 ahb {
@@ -856,7 +856,7 @@
856 }; 856 };
857 857
858 usb1: gadget@fff78000 { 858 usb1: gadget@fff78000 {
859 compatible = "atmel,at91rm9200-udc"; 859 compatible = "atmel,at91sam9263-udc";
860 reg = <0xfff78000 0x4000>; 860 reg = <0xfff78000 0x4000>;
861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
862 clocks = <&udc_clk>, <&udpck>; 862 clocks = <&udc_clk>, <&udpck>;
@@ -905,7 +905,6 @@
905 atmel,watchdog-type = "hardware"; 905 atmel,watchdog-type = "hardware";
906 atmel,reset-type = "all"; 906 atmel,reset-type = "all";
907 atmel,dbg-halt; 907 atmel,dbg-halt;
908 atmel,idle-halt;
909 status = "disabled"; 908 status = "disabled";
910 }; 909 };
911 910
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index ee80aa9c0759..488af63d5174 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -1116,7 +1116,6 @@
1116 atmel,watchdog-type = "hardware"; 1116 atmel,watchdog-type = "hardware";
1117 atmel,reset-type = "all"; 1117 atmel,reset-type = "all";
1118 atmel,dbg-halt; 1118 atmel,dbg-halt;
1119 atmel,idle-halt;
1120 status = "disabled"; 1119 status = "disabled";
1121 }; 1120 };
1122 1121
@@ -1301,7 +1300,7 @@
1301 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1300 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1302 reg = <0x00800000 0x100000>; 1301 reg = <0x00800000 0x100000>;
1303 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1302 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1304 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1303 clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1305 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; 1304 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
1306 status = "disabled"; 1305 status = "disabled";
1307 }; 1306 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index c2666a7cb5b1..0c53a375ba99 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -894,7 +894,6 @@
894 atmel,watchdog-type = "hardware"; 894 atmel,watchdog-type = "hardware";
895 atmel,reset-type = "all"; 895 atmel,reset-type = "all";
896 atmel,dbg-halt; 896 atmel,dbg-halt;
897 atmel,idle-halt;
898 status = "disabled"; 897 status = "disabled";
899 }; 898 };
900 899
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 818dabdd8c0e..d221179d0f1a 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1066,7 +1066,7 @@
1066 reg = <0x00500000 0x80000 1066 reg = <0x00500000 0x80000
1067 0xf803c000 0x400>; 1067 0xf803c000 0x400>;
1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1069 clocks = <&usb>, <&udphs_clk>; 1069 clocks = <&utmi>, <&udphs_clk>;
1070 clock-names = "hclk", "pclk"; 1070 clock-names = "hclk", "pclk";
1071 status = "disabled"; 1071 status = "disabled";
1072 1072
@@ -1130,7 +1130,6 @@
1130 atmel,watchdog-type = "hardware"; 1130 atmel,watchdog-type = "hardware";
1131 atmel,reset-type = "all"; 1131 atmel,reset-type = "all";
1132 atmel,dbg-halt; 1132 atmel,dbg-halt;
1133 atmel,idle-halt;
1134 status = "disabled"; 1133 status = "disabled";
1135 }; 1134 };
1136 1135
@@ -1186,7 +1185,7 @@
1186 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1185 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1187 reg = <0x00700000 0x100000>; 1186 reg = <0x00700000 0x100000>;
1188 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1187 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1189 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1188 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1190 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1189 clock-names = "usb_clk", "ehci_clk", "uhpck";
1191 status = "disabled"; 1190 status = "disabled";
1192 }; 1191 };
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index d3a29c1b8417..afe678f6d2e9 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -36,6 +36,20 @@
36 >; 36 >;
37 }; 37 };
38 38
39 mmc_pins: pinmux_mmc_pins {
40 pinctrl-single,pins = <
41 DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
42 DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
43 DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
44 DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
45 DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
46 DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
47 DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
48 DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
49 DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
50 >;
51 };
52
39 usb0_pins: pinmux_usb0_pins { 53 usb0_pins: pinmux_usb0_pins {
40 pinctrl-single,pins = < 54 pinctrl-single,pins = <
41 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ 55 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
@@ -137,7 +151,12 @@
137}; 151};
138 152
139&mmc1 { 153&mmc1 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&mmc_pins>;
140 vmmc-supply = <&vmmcsd_fixed>; 156 vmmc-supply = <&vmmcsd_fixed>;
157 bus-width = <4>;
158 cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
159 wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
141}; 160};
142 161
143/* At least dm8168-evm rev c won't support multipoint, later may */ 162/* At least dm8168-evm rev c won't support multipoint, later may */
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 3c97b5f2addc..f35715bc6992 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -150,17 +150,27 @@
150 }; 150 };
151 151
152 gpio1: gpio@48032000 { 152 gpio1: gpio@48032000 {
153 compatible = "ti,omap3-gpio"; 153 compatible = "ti,omap4-gpio";
154 ti,hwmods = "gpio1"; 154 ti,hwmods = "gpio1";
155 ti,gpio-always-on;
155 reg = <0x48032000 0x1000>; 156 reg = <0x48032000 0x1000>;
156 interrupts = <97>; 157 interrupts = <96>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
157 }; 162 };
158 163
159 gpio2: gpio@4804c000 { 164 gpio2: gpio@4804c000 {
160 compatible = "ti,omap3-gpio"; 165 compatible = "ti,omap4-gpio";
161 ti,hwmods = "gpio2"; 166 ti,hwmods = "gpio2";
167 ti,gpio-always-on;
162 reg = <0x4804c000 0x1000>; 168 reg = <0x4804c000 0x1000>;
163 interrupts = <99>; 169 interrupts = <98>;
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
164 }; 174 };
165 175
166 gpmc: gpmc@50000000 { 176 gpmc: gpmc@50000000 {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 3290a96ba586..7563d7ce01bb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -263,17 +263,15 @@
263 263
264 dcan1_pins_default: dcan1_pins_default { 264 dcan1_pins_default: dcan1_pins_default {
265 pinctrl-single,pins = < 265 pinctrl-single,pins = <
266 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 266 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
267 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 267 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
268 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
269 >; 268 >;
270 }; 269 };
271 270
272 dcan1_pins_sleep: dcan1_pins_sleep { 271 dcan1_pins_sleep: dcan1_pins_sleep {
273 pinctrl-single,pins = < 272 pinctrl-single,pins = <
274 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 273 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
275 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 274 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
276 0x418 (MUX_MODE15) /* wakeup0.off */
277 >; 275 >;
278 }; 276 };
279}; 277};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 127608d79033..c4659a979c41 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1111,7 +1111,6 @@
1111 "wkupclk", "refclk", 1111 "wkupclk", "refclk",
1112 "div-clk", "phy-div"; 1112 "div-clk", "phy-div";
1113 #phy-cells = <0>; 1113 #phy-cells = <0>;
1114 ti,hwmods = "pcie1-phy";
1115 }; 1114 };
1116 1115
1117 pcie2_phy: pciephy@4a095000 { 1116 pcie2_phy: pciephy@4a095000 {
@@ -1130,7 +1129,6 @@
1130 "wkupclk", "refclk", 1129 "wkupclk", "refclk",
1131 "div-clk", "phy-div"; 1130 "div-clk", "phy-div";
1132 #phy-cells = <0>; 1131 #phy-cells = <0>;
1133 ti,hwmods = "pcie2-phy";
1134 status = "disabled"; 1132 status = "disabled";
1135 }; 1133 };
1136 }; 1134 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index e0264d0bf7b9..40ed539ce474 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -119,17 +119,15 @@
119 119
120 dcan1_pins_default: dcan1_pins_default { 120 dcan1_pins_default: dcan1_pins_default {
121 pinctrl-single,pins = < 121 pinctrl-single,pins = <
122 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 122 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
123 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 123 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
124 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
125 >; 124 >;
126 }; 125 };
127 126
128 dcan1_pins_sleep: dcan1_pins_sleep { 127 dcan1_pins_sleep: dcan1_pins_sleep {
129 pinctrl-single,pins = < 128 pinctrl-single,pins = <
130 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 129 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
131 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 130 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
132 0x418 (MUX_MODE15) /* wakeup0.off */
133 >; 131 >;
134 }; 132 };
135 133
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd61ce47..99b09a44e269 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -243,10 +243,18 @@
243 ti,invert-autoidle-bit; 243 ti,invert-autoidle-bit;
244 }; 244 };
245 245
246 dpll_core_byp_mux: dpll_core_byp_mux {
247 #clock-cells = <0>;
248 compatible = "ti,mux-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 ti,bit-shift = <23>;
251 reg = <0x012c>;
252 };
253
246 dpll_core_ck: dpll_core_ck { 254 dpll_core_ck: dpll_core_ck {
247 #clock-cells = <0>; 255 #clock-cells = <0>;
248 compatible = "ti,omap4-dpll-core-clock"; 256 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 257 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 258 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
251 }; 259 };
252 260
@@ -309,10 +317,18 @@
309 clock-div = <1>; 317 clock-div = <1>;
310 }; 318 };
311 319
320 dpll_dsp_byp_mux: dpll_dsp_byp_mux {
321 #clock-cells = <0>;
322 compatible = "ti,mux-clock";
323 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
324 ti,bit-shift = <23>;
325 reg = <0x0240>;
326 };
327
312 dpll_dsp_ck: dpll_dsp_ck { 328 dpll_dsp_ck: dpll_dsp_ck {
313 #clock-cells = <0>; 329 #clock-cells = <0>;
314 compatible = "ti,omap4-dpll-clock"; 330 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 331 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 332 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
317 }; 333 };
318 334
@@ -335,10 +351,18 @@
335 clock-div = <1>; 351 clock-div = <1>;
336 }; 352 };
337 353
354 dpll_iva_byp_mux: dpll_iva_byp_mux {
355 #clock-cells = <0>;
356 compatible = "ti,mux-clock";
357 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
358 ti,bit-shift = <23>;
359 reg = <0x01ac>;
360 };
361
338 dpll_iva_ck: dpll_iva_ck { 362 dpll_iva_ck: dpll_iva_ck {
339 #clock-cells = <0>; 363 #clock-cells = <0>;
340 compatible = "ti,omap4-dpll-clock"; 364 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 365 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 366 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
343 }; 367 };
344 368
@@ -361,10 +385,18 @@
361 clock-div = <1>; 385 clock-div = <1>;
362 }; 386 };
363 387
388 dpll_gpu_byp_mux: dpll_gpu_byp_mux {
389 #clock-cells = <0>;
390 compatible = "ti,mux-clock";
391 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
392 ti,bit-shift = <23>;
393 reg = <0x02e4>;
394 };
395
364 dpll_gpu_ck: dpll_gpu_ck { 396 dpll_gpu_ck: dpll_gpu_ck {
365 #clock-cells = <0>; 397 #clock-cells = <0>;
366 compatible = "ti,omap4-dpll-clock"; 398 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 399 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 400 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
369 }; 401 };
370 402
@@ -398,10 +430,18 @@
398 clock-div = <1>; 430 clock-div = <1>;
399 }; 431 };
400 432
433 dpll_ddr_byp_mux: dpll_ddr_byp_mux {
434 #clock-cells = <0>;
435 compatible = "ti,mux-clock";
436 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
437 ti,bit-shift = <23>;
438 reg = <0x021c>;
439 };
440
401 dpll_ddr_ck: dpll_ddr_ck { 441 dpll_ddr_ck: dpll_ddr_ck {
402 #clock-cells = <0>; 442 #clock-cells = <0>;
403 compatible = "ti,omap4-dpll-clock"; 443 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 444 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 445 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
406 }; 446 };
407 447
@@ -416,10 +456,18 @@
416 ti,invert-autoidle-bit; 456 ti,invert-autoidle-bit;
417 }; 457 };
418 458
459 dpll_gmac_byp_mux: dpll_gmac_byp_mux {
460 #clock-cells = <0>;
461 compatible = "ti,mux-clock";
462 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
463 ti,bit-shift = <23>;
464 reg = <0x02b4>;
465 };
466
419 dpll_gmac_ck: dpll_gmac_ck { 467 dpll_gmac_ck: dpll_gmac_ck {
420 #clock-cells = <0>; 468 #clock-cells = <0>;
421 compatible = "ti,omap4-dpll-clock"; 469 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 470 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 471 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
424 }; 472 };
425 473
@@ -482,10 +530,18 @@
482 clock-div = <1>; 530 clock-div = <1>;
483 }; 531 };
484 532
533 dpll_eve_byp_mux: dpll_eve_byp_mux {
534 #clock-cells = <0>;
535 compatible = "ti,mux-clock";
536 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
537 ti,bit-shift = <23>;
538 reg = <0x0290>;
539 };
540
485 dpll_eve_ck: dpll_eve_ck { 541 dpll_eve_ck: dpll_eve_ck {
486 #clock-cells = <0>; 542 #clock-cells = <0>;
487 compatible = "ti,omap4-dpll-clock"; 543 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 544 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 545 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
490 }; 546 };
491 547
@@ -1249,10 +1305,18 @@
1249 clock-div = <1>; 1305 clock-div = <1>;
1250 }; 1306 };
1251 1307
1308 dpll_per_byp_mux: dpll_per_byp_mux {
1309 #clock-cells = <0>;
1310 compatible = "ti,mux-clock";
1311 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1312 ti,bit-shift = <23>;
1313 reg = <0x014c>;
1314 };
1315
1252 dpll_per_ck: dpll_per_ck { 1316 dpll_per_ck: dpll_per_ck {
1253 #clock-cells = <0>; 1317 #clock-cells = <0>;
1254 compatible = "ti,omap4-dpll-clock"; 1318 compatible = "ti,omap4-dpll-clock";
1255 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1319 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1256 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1320 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1257 }; 1321 };
1258 1322
@@ -1275,10 +1339,18 @@
1275 clock-div = <1>; 1339 clock-div = <1>;
1276 }; 1340 };
1277 1341
1342 dpll_usb_byp_mux: dpll_usb_byp_mux {
1343 #clock-cells = <0>;
1344 compatible = "ti,mux-clock";
1345 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1346 ti,bit-shift = <23>;
1347 reg = <0x018c>;
1348 };
1349
1278 dpll_usb_ck: dpll_usb_ck { 1350 dpll_usb_ck: dpll_usb_ck {
1279 #clock-cells = <0>; 1351 #clock-cells = <0>;
1280 compatible = "ti,omap4-dpll-j-type-clock"; 1352 compatible = "ti,omap4-dpll-j-type-clock";
1281 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1353 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1282 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1354 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1283 }; 1355 };
1284 1356
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 277b48b0b6f9..ac6b0ae42caf 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -18,6 +18,7 @@
18 */ 18 */
19 19
20#include "skeleton.dtsi" 20#include "skeleton.dtsi"
21#include "exynos4-cpu-thermal.dtsi"
21#include <dt-bindings/clock/exynos3250.h> 22#include <dt-bindings/clock/exynos3250.h>
22 23
23/ { 24/ {
@@ -193,6 +194,7 @@
193 interrupts = <0 216 0>; 194 interrupts = <0 216 0>;
194 clocks = <&cmu CLK_TMU_APBIF>; 195 clocks = <&cmu CLK_TMU_APBIF>;
195 clock-names = "tmu_apbif"; 196 clock-names = "tmu_apbif";
197 #include "exynos4412-tmu-sensor-conf.dtsi"
196 status = "disabled"; 198 status = "disabled";
197 }; 199 };
198 200
diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
new file mode 100644
index 000000000000..735cb2f10817
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
@@ -0,0 +1,52 @@
1/*
2 * Device tree sources for Exynos4 thermal zone
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15thermal-zones {
16 cpu_thermal: cpu-thermal {
17 thermal-sensors = <&tmu 0>;
18 polling-delay-passive = <0>;
19 polling-delay = <0>;
20 trips {
21 cpu_alert0: cpu-alert-0 {
22 temperature = <70000>; /* millicelsius */
23 hysteresis = <10000>; /* millicelsius */
24 type = "active";
25 };
26 cpu_alert1: cpu-alert-1 {
27 temperature = <95000>; /* millicelsius */
28 hysteresis = <10000>; /* millicelsius */
29 type = "active";
30 };
31 cpu_alert2: cpu-alert-2 {
32 temperature = <110000>; /* millicelsius */
33 hysteresis = <10000>; /* millicelsius */
34 type = "active";
35 };
36 cpu_crit0: cpu-crit-0 {
37 temperature = <120000>; /* millicelsius */
38 hysteresis = <0>; /* millicelsius */
39 type = "critical";
40 };
41 };
42 cooling-maps {
43 map0 {
44 trip = <&cpu_alert0>;
45 };
46 map1 {
47 trip = <&cpu_alert1>;
48 };
49 };
50 };
51};
52};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 76173cacd450..77ea547768f4 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -38,6 +38,7 @@
38 i2c5 = &i2c_5; 38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6; 39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7; 40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
41 csis0 = &csis_0; 42 csis0 = &csis_0;
42 csis1 = &csis_1; 43 csis1 = &csis_1;
43 fimc0 = &fimc_0; 44 fimc0 = &fimc_0;
@@ -104,6 +105,7 @@
104 compatible = "samsung,exynos4210-pd"; 105 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>; 106 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>; 107 #power-domain-cells = <0>;
108 power-domains = <&pd_lcd0>;
107 }; 109 };
108 110
109 pd_cam: cam-power-domain@10023C00 { 111 pd_cam: cam-power-domain@10023C00 {
@@ -554,6 +556,22 @@
554 status = "disabled"; 556 status = "disabled";
555 }; 557 };
556 558
559 i2c_8: i2c@138E0000 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "samsung,s3c2440-hdmiphy-i2c";
563 reg = <0x138E0000 0x100>;
564 interrupts = <0 93 0>;
565 clocks = <&clock CLK_I2C_HDMI>;
566 clock-names = "i2c";
567 status = "disabled";
568
569 hdmi_i2c_phy: hdmiphy@38 {
570 compatible = "exynos4210-hdmiphy";
571 reg = <0x38>;
572 };
573 };
574
557 spi_0: spi@13920000 { 575 spi_0: spi@13920000 {
558 compatible = "samsung,exynos4210-spi"; 576 compatible = "samsung,exynos4210-spi";
559 reg = <0x13920000 0x100>; 577 reg = <0x13920000 0x100>;
@@ -663,6 +681,33 @@
663 status = "disabled"; 681 status = "disabled";
664 }; 682 };
665 683
684 tmu: tmu@100C0000 {
685 #include "exynos4412-tmu-sensor-conf.dtsi"
686 };
687
688 hdmi: hdmi@12D00000 {
689 compatible = "samsung,exynos4210-hdmi";
690 reg = <0x12D00000 0x70000>;
691 interrupts = <0 92 0>;
692 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
693 "mout_hdmi";
694 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
695 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
696 <&clock CLK_MOUT_HDMI>;
697 phy = <&hdmi_i2c_phy>;
698 power-domains = <&pd_tv>;
699 samsung,syscon-phandle = <&pmu_system_controller>;
700 status = "disabled";
701 };
702
703 mixer: mixer@12C10000 {
704 compatible = "samsung,exynos4210-mixer";
705 interrupts = <0 91 0>;
706 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
707 power-domains = <&pd_tv>;
708 status = "disabled";
709 };
710
666 ppmu_dmc0: ppmu_dmc0@106a0000 { 711 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu"; 712 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>; 713 reg = <0x106a0000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 3d6652a4b6cb..32c5fd8f6269 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -426,6 +426,25 @@
426 status = "okay"; 426 status = "okay";
427 }; 427 };
428 428
429 tmu@100C0000 {
430 status = "okay";
431 };
432
433 thermal-zones {
434 cpu_thermal: cpu-thermal {
435 cooling-maps {
436 map0 {
437 /* Corresponds to 800MHz at freq_table */
438 cooling-device = <&cpu0 2 2>;
439 };
440 map1 {
441 /* Corresponds to 200MHz at freq_table */
442 cooling-device = <&cpu0 4 4>;
443 };
444 };
445 };
446 };
447
429 camera { 448 camera {
430 pinctrl-names = "default"; 449 pinctrl-names = "default";
431 pinctrl-0 = <>; 450 pinctrl-0 = <>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index b57e6b82ea20..d4f2b11319dd 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -505,6 +505,63 @@
505 assigned-clock-rates = <0>, <160000000>; 505 assigned-clock-rates = <0>, <160000000>;
506 }; 506 };
507 }; 507 };
508
509 hdmi_en: voltage-regulator-hdmi-5v {
510 compatible = "regulator-fixed";
511 regulator-name = "HDMI_5V";
512 regulator-min-microvolt = <5000000>;
513 regulator-max-microvolt = <5000000>;
514 gpio = <&gpe0 1 0>;
515 enable-active-high;
516 };
517
518 hdmi_ddc: i2c-ddc {
519 compatible = "i2c-gpio";
520 gpios = <&gpe4 2 0 &gpe4 3 0>;
521 i2c-gpio,delay-us = <100>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 pinctrl-0 = <&i2c_ddc_bus>;
526 pinctrl-names = "default";
527 status = "okay";
528 };
529
530 mixer@12C10000 {
531 status = "okay";
532 };
533
534 hdmi@12D00000 {
535 hpd-gpio = <&gpx3 7 0>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&hdmi_hpd>;
538 hdmi-en-supply = <&hdmi_en>;
539 vdd-supply = <&ldo3_reg>;
540 vdd_osc-supply = <&ldo4_reg>;
541 vdd_pll-supply = <&ldo3_reg>;
542 ddc = <&hdmi_ddc>;
543 status = "okay";
544 };
545
546 i2c@138E0000 {
547 status = "okay";
548 };
549};
550
551&pinctrl_1 {
552 hdmi_hpd: hdmi-hpd {
553 samsung,pins = "gpx3-7";
554 samsung,pin-pud = <0>;
555 };
556};
557
558&pinctrl_0 {
559 i2c_ddc_bus: i2c-ddc-bus {
560 samsung,pins = "gpe4-2", "gpe4-3";
561 samsung,pin-function = <2>;
562 samsung,pin-pud = <3>;
563 samsung,pin-drv = <0>;
564 };
508}; 565};
509 566
510&mdma1 { 567&mdma1 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 67c832c9dcf1..be89f83f70e7 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -21,6 +21,7 @@
21 21
22#include "exynos4.dtsi" 22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi" 23#include "exynos4210-pinctrl.dtsi"
24#include "exynos4-cpu-thermal.dtsi"
24 25
25/ { 26/ {
26 compatible = "samsung,exynos4210", "samsung,exynos4"; 27 compatible = "samsung,exynos4210", "samsung,exynos4";
@@ -35,10 +36,13 @@
35 #address-cells = <1>; 36 #address-cells = <1>;
36 #size-cells = <0>; 37 #size-cells = <0>;
37 38
38 cpu@900 { 39 cpu0: cpu@900 {
39 device_type = "cpu"; 40 device_type = "cpu";
40 compatible = "arm,cortex-a9"; 41 compatible = "arm,cortex-a9";
41 reg = <0x900>; 42 reg = <0x900>;
43 cooling-min-level = <4>;
44 cooling-max-level = <2>;
45 #cooling-cells = <2>; /* min followed by max */
42 }; 46 };
43 47
44 cpu@901 { 48 cpu@901 {
@@ -153,16 +157,38 @@
153 reg = <0x03860000 0x1000>; 157 reg = <0x03860000 0x1000>;
154 }; 158 };
155 159
156 tmu@100C0000 { 160 tmu: tmu@100C0000 {
157 compatible = "samsung,exynos4210-tmu"; 161 compatible = "samsung,exynos4210-tmu";
158 interrupt-parent = <&combiner>; 162 interrupt-parent = <&combiner>;
159 reg = <0x100C0000 0x100>; 163 reg = <0x100C0000 0x100>;
160 interrupts = <2 4>; 164 interrupts = <2 4>;
161 clocks = <&clock CLK_TMU_APBIF>; 165 clocks = <&clock CLK_TMU_APBIF>;
162 clock-names = "tmu_apbif"; 166 clock-names = "tmu_apbif";
167 samsung,tmu_gain = <15>;
168 samsung,tmu_reference_voltage = <7>;
163 status = "disabled"; 169 status = "disabled";
164 }; 170 };
165 171
172 thermal-zones {
173 cpu_thermal: cpu-thermal {
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&tmu 0>;
177
178 trips {
179 cpu_alert0: cpu-alert-0 {
180 temperature = <85000>; /* millicelsius */
181 };
182 cpu_alert1: cpu-alert-1 {
183 temperature = <100000>; /* millicelsius */
184 };
185 cpu_alert2: cpu-alert-2 {
186 temperature = <110000>; /* millicelsius */
187 };
188 };
189 };
190 };
191
166 g2d@12800000 { 192 g2d@12800000 {
167 compatible = "samsung,s5pv210-g2d"; 193 compatible = "samsung,s5pv210-g2d";
168 reg = <0x12800000 0x1000>; 194 reg = <0x12800000 0x1000>;
@@ -203,6 +229,14 @@
203 }; 229 };
204 }; 230 };
205 231
232 mixer: mixer@12C10000 {
233 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
234 "sclk_mixer";
235 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
236 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
237 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
238 };
239
206 ppmu_lcd1: ppmu_lcd1@12240000 { 240 ppmu_lcd1: ppmu_lcd1@12240000 {
207 compatible = "samsung,exynos-ppmu"; 241 compatible = "samsung,exynos-ppmu";
208 reg = <0x12240000 0x2000>; 242 reg = <0x12240000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index dd0a43ec56da..5be03288f1ee 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -26,10 +26,13 @@
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu@A00 { 29 cpu0: cpu@A00 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 cooling-min-level = <13>;
34 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */
33 }; 36 };
34 37
35 cpu@A01 { 38 cpu@A01 {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index de80b5bba204..adb4f6a97a1d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -249,6 +249,20 @@
249 regulator-always-on; 249 regulator-always-on;
250 }; 250 };
251 251
252 ldo8_reg: ldo@8 {
253 regulator-compatible = "LDO8";
254 regulator-name = "VDD10_HDMI_1.0V";
255 regulator-min-microvolt = <1000000>;
256 regulator-max-microvolt = <1000000>;
257 };
258
259 ldo10_reg: ldo@10 {
260 regulator-compatible = "LDO10";
261 regulator-name = "VDDQ_MIPIHSI_1.8V";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 };
265
252 ldo11_reg: LDO11 { 266 ldo11_reg: LDO11 {
253 regulator-name = "VDD18_ABB1_1.8V"; 267 regulator-name = "VDD18_ABB1_1.8V";
254 regulator-min-microvolt = <1800000>; 268 regulator-min-microvolt = <1800000>;
@@ -411,6 +425,51 @@
411 ehci: ehci@12580000 { 425 ehci: ehci@12580000 {
412 status = "okay"; 426 status = "okay";
413 }; 427 };
428
429 tmu@100C0000 {
430 vtmu-supply = <&ldo10_reg>;
431 status = "okay";
432 };
433
434 thermal-zones {
435 cpu_thermal: cpu-thermal {
436 cooling-maps {
437 map0 {
438 /* Corresponds to 800MHz at freq_table */
439 cooling-device = <&cpu0 7 7>;
440 };
441 map1 {
442 /* Corresponds to 200MHz at freq_table */
443 cooling-device = <&cpu0 13 13>;
444 };
445 };
446 };
447 };
448
449 mixer: mixer@12C10000 {
450 status = "okay";
451 };
452
453 hdmi@12D00000 {
454 hpd-gpio = <&gpx3 7 0>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&hdmi_hpd>;
457 vdd-supply = <&ldo8_reg>;
458 vdd_osc-supply = <&ldo10_reg>;
459 vdd_pll-supply = <&ldo8_reg>;
460 ddc = <&hdmi_ddc>;
461 status = "okay";
462 };
463
464 hdmi_ddc: i2c@13880000 {
465 status = "okay";
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c2_bus>;
468 };
469
470 i2c@138E0000 {
471 status = "okay";
472 };
414}; 473};
415 474
416&pinctrl_1 { 475&pinctrl_1 {
@@ -425,4 +484,9 @@
425 samsung,pin-pud = <0>; 484 samsung,pin-pud = <0>;
426 samsung,pin-drv = <0>; 485 samsung,pin-drv = <0>;
427 }; 486 };
487
488 hdmi_hpd: hdmi-hpd {
489 samsung,pins = "gpx3-7";
490 samsung,pin-pud = <1>;
491 };
428}; 492};
diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..e3f7934d19d0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
@@ -0,0 +1,24 @@
1/*
2 * Device tree sources for Exynos4412 TMU sensor configuration
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal_exynos.h>
13
14#thermal-sensor-cells = <0>;
15samsung,tmu_gain = <8>;
16samsung,tmu_reference_voltage = <16>;
17samsung,tmu_noise_cancel_mode = <4>;
18samsung,tmu_efuse_value = <55>;
19samsung,tmu_min_efuse_value = <40>;
20samsung,tmu_max_efuse_value = <100>;
21samsung,tmu_first_point_trim = <25>;
22samsung,tmu_second_point_trim = <85>;
23samsung,tmu_default_temp_offset = <50>;
24samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 21f748083586..173ffa479ad3 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -927,6 +927,21 @@
927 pulldown-ohm = <100000>; /* 100K */ 927 pulldown-ohm = <100000>; /* 100K */
928 io-channels = <&adc 2>; /* Battery temperature */ 928 io-channels = <&adc 2>; /* Battery temperature */
929 }; 929 };
930
931 thermal-zones {
932 cpu_thermal: cpu-thermal {
933 cooling-maps {
934 map0 {
935 /* Corresponds to 800MHz at freq_table */
936 cooling-device = <&cpu0 7 7>;
937 };
938 map1 {
939 /* Corresponds to 200MHz at freq_table */
940 cooling-device = <&cpu0 13 13>;
941 };
942 };
943 };
944 };
930}; 945};
931 946
932&pmu_system_controller { 947&pmu_system_controller {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 0f6ec93bb1d8..68ad43b391ae 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -26,10 +26,13 @@
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu@A00 { 29 cpu0: cpu@A00 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 cooling-min-level = <13>;
34 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */
33 }; 36 };
34 37
35 cpu@A01 { 38 cpu@A01 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index f5e0ae780d6c..6a6abe14fd9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -19,6 +19,7 @@
19 19
20#include "exynos4.dtsi" 20#include "exynos4.dtsi"
21#include "exynos4x12-pinctrl.dtsi" 21#include "exynos4x12-pinctrl.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
22 23
23/ { 24/ {
24 aliases { 25 aliases {
@@ -297,4 +298,15 @@
297 clock-names = "tmu_apbif"; 298 clock-names = "tmu_apbif";
298 status = "disabled"; 299 status = "disabled";
299 }; 300 };
301
302 hdmi: hdmi@12D00000 {
303 compatible = "samsung,exynos4212-hdmi";
304 };
305
306 mixer: mixer@12C10000 {
307 compatible = "samsung,exynos4212-mixer";
308 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
309 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
310 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
311 };
300}; 312};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9bb1b0b738f5..adbde1adad95 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,7 +20,7 @@
20#include <dt-bindings/clock/exynos5250.h> 20#include <dt-bindings/clock/exynos5250.h>
21#include "exynos5.dtsi" 21#include "exynos5.dtsi"
22#include "exynos5250-pinctrl.dtsi" 22#include "exynos5250-pinctrl.dtsi"
23 23#include "exynos4-cpu-thermal.dtsi"
24#include <dt-bindings/clock/exynos-audss-clk.h> 24#include <dt-bindings/clock/exynos-audss-clk.h>
25 25
26/ { 26/ {
@@ -58,11 +58,14 @@
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <0>; 59 #size-cells = <0>;
60 60
61 cpu@0 { 61 cpu0: cpu@0 {
62 device_type = "cpu"; 62 device_type = "cpu";
63 compatible = "arm,cortex-a15"; 63 compatible = "arm,cortex-a15";
64 reg = <0>; 64 reg = <0>;
65 clock-frequency = <1700000000>; 65 clock-frequency = <1700000000>;
66 cooling-min-level = <15>;
67 cooling-max-level = <9>;
68 #cooling-cells = <2>; /* min followed by max */
66 }; 69 };
67 cpu@1 { 70 cpu@1 {
68 device_type = "cpu"; 71 device_type = "cpu";
@@ -102,6 +105,12 @@
102 #power-domain-cells = <0>; 105 #power-domain-cells = <0>;
103 }; 106 };
104 107
108 pd_disp1: disp1-power-domain@100440A0 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x100440A0 0x20>;
111 #power-domain-cells = <0>;
112 };
113
105 clock: clock-controller@10010000 { 114 clock: clock-controller@10010000 {
106 compatible = "samsung,exynos5250-clock"; 115 compatible = "samsung,exynos5250-clock";
107 reg = <0x10010000 0x30000>; 116 reg = <0x10010000 0x30000>;
@@ -235,12 +244,32 @@
235 status = "disabled"; 244 status = "disabled";
236 }; 245 };
237 246
238 tmu@10060000 { 247 tmu: tmu@10060000 {
239 compatible = "samsung,exynos5250-tmu"; 248 compatible = "samsung,exynos5250-tmu";
240 reg = <0x10060000 0x100>; 249 reg = <0x10060000 0x100>;
241 interrupts = <0 65 0>; 250 interrupts = <0 65 0>;
242 clocks = <&clock CLK_TMU>; 251 clocks = <&clock CLK_TMU>;
243 clock-names = "tmu_apbif"; 252 clock-names = "tmu_apbif";
253 #include "exynos4412-tmu-sensor-conf.dtsi"
254 };
255
256 thermal-zones {
257 cpu_thermal: cpu-thermal {
258 polling-delay-passive = <0>;
259 polling-delay = <0>;
260 thermal-sensors = <&tmu 0>;
261
262 cooling-maps {
263 map0 {
264 /* Corresponds to 800MHz at freq_table */
265 cooling-device = <&cpu0 9 9>;
266 };
267 map1 {
268 /* Corresponds to 200MHz at freq_table */
269 cooling-device = <&cpu0 15 15>;
270 };
271 };
272 };
244 }; 273 };
245 274
246 serial@12C00000 { 275 serial@12C00000 {
@@ -719,6 +748,7 @@
719 hdmi: hdmi { 748 hdmi: hdmi {
720 compatible = "samsung,exynos4212-hdmi"; 749 compatible = "samsung,exynos4212-hdmi";
721 reg = <0x14530000 0x70000>; 750 reg = <0x14530000 0x70000>;
751 power-domains = <&pd_disp1>;
722 interrupts = <0 95 0>; 752 interrupts = <0 95 0>;
723 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 753 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
724 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 754 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
@@ -731,9 +761,11 @@
731 mixer { 761 mixer {
732 compatible = "samsung,exynos5250-mixer"; 762 compatible = "samsung,exynos5250-mixer";
733 reg = <0x14450000 0x10000>; 763 reg = <0x14450000 0x10000>;
764 power-domains = <&pd_disp1>;
734 interrupts = <0 94 0>; 765 interrupts = <0 94 0>;
735 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 766 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
736 clock-names = "mixer", "sclk_hdmi"; 767 <&clock CLK_SCLK_HDMI>;
768 clock-names = "mixer", "hdmi", "sclk_hdmi";
737 }; 769 };
738 770
739 dp_phy: video-phy@10040720 { 771 dp_phy: video-phy@10040720 {
@@ -743,6 +775,7 @@
743 }; 775 };
744 776
745 dp: dp-controller@145B0000 { 777 dp: dp-controller@145B0000 {
778 power-domains = <&pd_disp1>;
746 clocks = <&clock CLK_DP>; 779 clocks = <&clock CLK_DP>;
747 clock-names = "dp"; 780 clock-names = "dp";
748 phys = <&dp_phy>; 781 phys = <&dp_phy>;
@@ -750,6 +783,7 @@
750 }; 783 };
751 784
752 fimd: fimd@14400000 { 785 fimd: fimd@14400000 {
786 power-domains = <&pd_disp1>;
753 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 787 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
754 clock-names = "sclk_fimd", "fimd"; 788 clock-names = "sclk_fimd", "fimd";
755 }; 789 };
diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
new file mode 100644
index 000000000000..5d31fc140823
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device tree sources for default Exynos5420 thermal zone definition
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12polling-delay-passive = <0>;
13polling-delay = <0>;
14trips {
15 cpu-alert-0 {
16 temperature = <85000>; /* millicelsius */
17 hysteresis = <10000>; /* millicelsius */
18 type = "active";
19 };
20 cpu-alert-1 {
21 temperature = <103000>; /* millicelsius */
22 hysteresis = <10000>; /* millicelsius */
23 type = "active";
24 };
25 cpu-alert-2 {
26 temperature = <110000>; /* millicelsius */
27 hysteresis = <10000>; /* millicelsius */
28 type = "active";
29 };
30 cpu-crit-0 {
31 temperature = <1200000>; /* millicelsius */
32 hysteresis = <0>; /* millicelsius */
33 type = "critical";
34 };
35};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e9773b30..c0e98cf3514f 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -740,8 +740,9 @@
740 compatible = "samsung,exynos5420-mixer"; 740 compatible = "samsung,exynos5420-mixer";
741 reg = <0x14450000 0x10000>; 741 reg = <0x14450000 0x10000>;
742 interrupts = <0 94 0>; 742 interrupts = <0 94 0>;
743 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 743 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
744 clock-names = "mixer", "sclk_hdmi"; 744 <&clock CLK_SCLK_HDMI>;
745 clock-names = "mixer", "hdmi", "sclk_hdmi";
745 power-domains = <&disp_pd>; 746 power-domains = <&disp_pd>;
746 }; 747 };
747 748
@@ -782,6 +783,7 @@
782 interrupts = <0 65 0>; 783 interrupts = <0 65 0>;
783 clocks = <&clock CLK_TMU>; 784 clocks = <&clock CLK_TMU>;
784 clock-names = "tmu_apbif"; 785 clock-names = "tmu_apbif";
786 #include "exynos4412-tmu-sensor-conf.dtsi"
785 }; 787 };
786 788
787 tmu_cpu1: tmu@10064000 { 789 tmu_cpu1: tmu@10064000 {
@@ -790,6 +792,7 @@
790 interrupts = <0 183 0>; 792 interrupts = <0 183 0>;
791 clocks = <&clock CLK_TMU>; 793 clocks = <&clock CLK_TMU>;
792 clock-names = "tmu_apbif"; 794 clock-names = "tmu_apbif";
795 #include "exynos4412-tmu-sensor-conf.dtsi"
793 }; 796 };
794 797
795 tmu_cpu2: tmu@10068000 { 798 tmu_cpu2: tmu@10068000 {
@@ -798,6 +801,7 @@
798 interrupts = <0 184 0>; 801 interrupts = <0 184 0>;
799 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 802 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
800 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 803 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
804 #include "exynos4412-tmu-sensor-conf.dtsi"
801 }; 805 };
802 806
803 tmu_cpu3: tmu@1006c000 { 807 tmu_cpu3: tmu@1006c000 {
@@ -806,6 +810,7 @@
806 interrupts = <0 185 0>; 810 interrupts = <0 185 0>;
807 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 811 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
808 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 812 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
813 #include "exynos4412-tmu-sensor-conf.dtsi"
809 }; 814 };
810 815
811 tmu_gpu: tmu@100a0000 { 816 tmu_gpu: tmu@100a0000 {
@@ -814,6 +819,30 @@
814 interrupts = <0 215 0>; 819 interrupts = <0 215 0>;
815 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 820 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
816 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 821 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
822 #include "exynos4412-tmu-sensor-conf.dtsi"
823 };
824
825 thermal-zones {
826 cpu0_thermal: cpu0-thermal {
827 thermal-sensors = <&tmu_cpu0>;
828 #include "exynos5420-trip-points.dtsi"
829 };
830 cpu1_thermal: cpu1-thermal {
831 thermal-sensors = <&tmu_cpu1>;
832 #include "exynos5420-trip-points.dtsi"
833 };
834 cpu2_thermal: cpu2-thermal {
835 thermal-sensors = <&tmu_cpu2>;
836 #include "exynos5420-trip-points.dtsi"
837 };
838 cpu3_thermal: cpu3-thermal {
839 thermal-sensors = <&tmu_cpu3>;
840 #include "exynos5420-trip-points.dtsi"
841 };
842 gpu_thermal: gpu-thermal {
843 thermal-sensors = <&tmu_gpu>;
844 #include "exynos5420-trip-points.dtsi"
845 };
817 }; 846 };
818 847
819 watchdog: watchdog@101D0000 { 848 watchdog: watchdog@101D0000 {
diff --git a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..7b2fba0ae92b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi
@@ -0,0 +1,24 @@
1/*
2 * Device tree sources for Exynos5440 TMU sensor configuration
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/thermal/thermal_exynos.h>
13
14#thermal-sensor-cells = <0>;
15samsung,tmu_gain = <5>;
16samsung,tmu_reference_voltage = <16>;
17samsung,tmu_noise_cancel_mode = <4>;
18samsung,tmu_efuse_value = <0x5d2d>;
19samsung,tmu_min_efuse_value = <16>;
20samsung,tmu_max_efuse_value = <76>;
21samsung,tmu_first_point_trim = <25>;
22samsung,tmu_second_point_trim = <70>;
23samsung,tmu_default_temp_offset = <25>;
24samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
new file mode 100644
index 000000000000..48adfa8f4300
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
@@ -0,0 +1,25 @@
1/*
2 * Device tree sources for default Exynos5440 thermal zone definition
3 *
4 * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12polling-delay-passive = <0>;
13polling-delay = <0>;
14trips {
15 cpu-alert-0 {
16 temperature = <100000>; /* millicelsius */
17 hysteresis = <0>; /* millicelsius */
18 type = "active";
19 };
20 cpu-crit-0 {
21 temperature = <1050000>; /* millicelsius */
22 hysteresis = <0>; /* millicelsius */
23 type = "critical";
24 };
25};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 8f3373cd7b87..59d9416b3b03 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -219,6 +219,7 @@
219 interrupts = <0 58 0>; 219 interrupts = <0 58 0>;
220 clocks = <&clock CLK_B_125>; 220 clocks = <&clock CLK_B_125>;
221 clock-names = "tmu_apbif"; 221 clock-names = "tmu_apbif";
222 #include "exynos5440-tmu-sensor-conf.dtsi"
222 }; 223 };
223 224
224 tmuctrl_1: tmuctrl@16011C { 225 tmuctrl_1: tmuctrl@16011C {
@@ -227,6 +228,7 @@
227 interrupts = <0 58 0>; 228 interrupts = <0 58 0>;
228 clocks = <&clock CLK_B_125>; 229 clocks = <&clock CLK_B_125>;
229 clock-names = "tmu_apbif"; 230 clock-names = "tmu_apbif";
231 #include "exynos5440-tmu-sensor-conf.dtsi"
230 }; 232 };
231 233
232 tmuctrl_2: tmuctrl@160120 { 234 tmuctrl_2: tmuctrl@160120 {
@@ -235,6 +237,22 @@
235 interrupts = <0 58 0>; 237 interrupts = <0 58 0>;
236 clocks = <&clock CLK_B_125>; 238 clocks = <&clock CLK_B_125>;
237 clock-names = "tmu_apbif"; 239 clock-names = "tmu_apbif";
240 #include "exynos5440-tmu-sensor-conf.dtsi"
241 };
242
243 thermal-zones {
244 cpu0_thermal: cpu0-thermal {
245 thermal-sensors = <&tmuctrl_0>;
246 #include "exynos5440-trip-points.dtsi"
247 };
248 cpu1_thermal: cpu1-thermal {
249 thermal-sensors = <&tmuctrl_1>;
250 #include "exynos5440-trip-points.dtsi"
251 };
252 cpu2_thermal: cpu2-thermal {
253 thermal-sensors = <&tmuctrl_2>;
254 #include "exynos5440-trip-points.dtsi"
255 };
238 }; 256 };
239 257
240 sata@210000 { 258 sata@210000 {
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f1cd2147421d..a626e6dd8022 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -35,6 +35,7 @@
35 regulator-max-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>; 36 gpio = <&gpio3 22 0>;
37 enable-active-high; 37 enable-active-high;
38 vin-supply = <&swbst_reg>;
38 }; 39 };
39 40
40 reg_usb_h1_vbus: regulator@1 { 41 reg_usb_h1_vbus: regulator@1 {
@@ -45,6 +46,7 @@
45 regulator-max-microvolt = <5000000>; 46 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio1 29 0>; 47 gpio = <&gpio1 29 0>;
47 enable-active-high; 48 enable-active-high;
49 vin-supply = <&swbst_reg>;
48 }; 50 };
49 51
50 reg_audio: regulator@2 { 52 reg_audio: regulator@2 {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index fda4932faefd..945887d3fdb3 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -52,6 +52,7 @@
52 regulator-max-microvolt = <5000000>; 52 regulator-max-microvolt = <5000000>;
53 gpio = <&gpio4 0 0>; 53 gpio = <&gpio4 0 0>;
54 enable-active-high; 54 enable-active-high;
55 vin-supply = <&swbst_reg>;
55 }; 56 };
56 57
57 reg_usb_otg2_vbus: regulator@1 { 58 reg_usb_otg2_vbus: regulator@1 {
@@ -62,6 +63,7 @@
62 regulator-max-microvolt = <5000000>; 63 regulator-max-microvolt = <5000000>;
63 gpio = <&gpio4 2 0>; 64 gpio = <&gpio4 2 0>;
64 enable-active-high; 65 enable-active-high;
66 vin-supply = <&swbst_reg>;
65 }; 67 };
66 68
67 reg_aud3v: regulator@2 { 69 reg_aud3v: regulator@2 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f4f78c40b564..3fdc84fddb70 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -92,6 +92,8 @@
92 ti,hwmods = "aes"; 92 ti,hwmods = "aes";
93 reg = <0x480c5000 0x50>; 93 reg = <0x480c5000 0x50>;
94 interrupts = <0>; 94 interrupts = <0>;
95 dmas = <&sdma 65 &sdma 66>;
96 dma-names = "tx", "rx";
95 }; 97 };
96 98
97 prm: prm@48306000 { 99 prm: prm@48306000 {
@@ -550,6 +552,8 @@
550 ti,hwmods = "sham"; 552 ti,hwmods = "sham";
551 reg = <0x480c3000 0x64>; 553 reg = <0x480c3000 0x64>;
552 interrupts = <49>; 554 interrupts = <49>;
555 dmas = <&sdma 69>;
556 dma-names = "rx";
553 }; 557 };
554 558
555 smartreflex_core: smartreflex@480cb000 { 559 smartreflex_core: smartreflex@480cb000 {
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
index 19212ac6eef0..de8a3d456cf7 100644
--- a/arch/arm/boot/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -13,7 +13,7 @@
13 13
14core_thermal: core_thermal { 14core_thermal: core_thermal {
15 polling-delay-passive = <250>; /* milliseconds */ 15 polling-delay-passive = <250>; /* milliseconds */
16 polling-delay = <1000>; /* milliseconds */ 16 polling-delay = <500>; /* milliseconds */
17 17
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 2>; 19 thermal-sensors = <&bandgap 2>;
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
index 1b87aca88b77..bc3090f2e84b 100644
--- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -13,7 +13,7 @@
13 13
14gpu_thermal: gpu_thermal { 14gpu_thermal: gpu_thermal {
15 polling-delay-passive = <250>; /* milliseconds */ 15 polling-delay-passive = <250>; /* milliseconds */
16 polling-delay = <1000>; /* milliseconds */ 16 polling-delay = <500>; /* milliseconds */
17 17
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 1>; 19 thermal-sensors = <&bandgap 1>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ddff674bd05e..4a485b63a141 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1079,4 +1079,8 @@
1079 }; 1079 };
1080}; 1080};
1081 1081
1082&cpu_thermal {
1083 polling-delay = <500>; /* milliseconds */
1084};
1085
1082/include/ "omap54xx-clocks.dtsi" 1086/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 58c27466f012..83b425fb3ac2 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -167,10 +167,18 @@
167 ti,index-starts-at-one; 167 ti,index-starts-at-one;
168 }; 168 };
169 169
170 dpll_core_byp_mux: dpll_core_byp_mux {
171 #clock-cells = <0>;
172 compatible = "ti,mux-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
174 ti,bit-shift = <23>;
175 reg = <0x012c>;
176 };
177
170 dpll_core_ck: dpll_core_ck { 178 dpll_core_ck: dpll_core_ck {
171 #clock-cells = <0>; 179 #clock-cells = <0>;
172 compatible = "ti,omap4-dpll-core-clock"; 180 compatible = "ti,omap4-dpll-core-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 181 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
174 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 182 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
175 }; 183 };
176 184
@@ -294,10 +302,18 @@
294 clock-div = <1>; 302 clock-div = <1>;
295 }; 303 };
296 304
305 dpll_iva_byp_mux: dpll_iva_byp_mux {
306 #clock-cells = <0>;
307 compatible = "ti,mux-clock";
308 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
309 ti,bit-shift = <23>;
310 reg = <0x01ac>;
311 };
312
297 dpll_iva_ck: dpll_iva_ck { 313 dpll_iva_ck: dpll_iva_ck {
298 #clock-cells = <0>; 314 #clock-cells = <0>;
299 compatible = "ti,omap4-dpll-clock"; 315 compatible = "ti,omap4-dpll-clock";
300 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 316 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
301 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 317 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
302 }; 318 };
303 319
@@ -599,10 +615,19 @@
599 }; 615 };
600}; 616};
601&cm_core_clocks { 617&cm_core_clocks {
618
619 dpll_per_byp_mux: dpll_per_byp_mux {
620 #clock-cells = <0>;
621 compatible = "ti,mux-clock";
622 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
623 ti,bit-shift = <23>;
624 reg = <0x014c>;
625 };
626
602 dpll_per_ck: dpll_per_ck { 627 dpll_per_ck: dpll_per_ck {
603 #clock-cells = <0>; 628 #clock-cells = <0>;
604 compatible = "ti,omap4-dpll-clock"; 629 compatible = "ti,omap4-dpll-clock";
605 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 630 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
606 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 631 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
607 }; 632 };
608 633
@@ -714,10 +739,18 @@
714 ti,index-starts-at-one; 739 ti,index-starts-at-one;
715 }; 740 };
716 741
742 dpll_usb_byp_mux: dpll_usb_byp_mux {
743 #clock-cells = <0>;
744 compatible = "ti,mux-clock";
745 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
746 ti,bit-shift = <23>;
747 reg = <0x018c>;
748 };
749
717 dpll_usb_ck: dpll_usb_ck { 750 dpll_usb_ck: dpll_usb_ck {
718 #clock-cells = <0>; 751 #clock-cells = <0>;
719 compatible = "ti,omap4-dpll-j-type-clock"; 752 compatible = "ti,omap4-dpll-j-type-clock";
720 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 753 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
721 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 754 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
722 }; 755 };
723 756
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index d771f687a13b..eccc78d3220b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -411,6 +411,7 @@
411 "mac_clk_rx", "mac_clk_tx", 411 "mac_clk_rx", "mac_clk_tx",
412 "clk_mac_ref", "clk_mac_refout", 412 "clk_mac_ref", "clk_mac_refout",
413 "aclk_mac", "pclk_mac"; 413 "aclk_mac", "pclk_mac";
414 status = "disabled";
414 }; 415 };
415 416
416 usb_host0_ehci: usb@ff500000 { 417 usb_host0_ehci: usb@ff500000 {
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 261311bdf65b..367af53c1b84 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1248,7 +1248,6 @@
1248 atmel,watchdog-type = "hardware"; 1248 atmel,watchdog-type = "hardware";
1249 atmel,reset-type = "all"; 1249 atmel,reset-type = "all";
1250 atmel,dbg-halt; 1250 atmel,dbg-halt;
1251 atmel,idle-halt;
1252 status = "disabled"; 1251 status = "disabled";
1253 }; 1252 };
1254 1253
@@ -1416,7 +1415,7 @@
1416 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1415 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1417 reg = <0x00700000 0x100000>; 1416 reg = <0x00700000 0x100000>;
1418 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1417 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1419 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1418 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1420 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1419 clock-names = "usb_clk", "ehci_clk", "uhpck";
1421 status = "disabled"; 1420 status = "disabled";
1422 }; 1421 };
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index d986b41b9654..4303874889c6 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -66,6 +66,7 @@
66 gpio4 = &pioE; 66 gpio4 = &pioE;
67 tcb0 = &tcb0; 67 tcb0 = &tcb0;
68 tcb1 = &tcb1; 68 tcb1 = &tcb1;
69 i2c0 = &i2c0;
69 i2c2 = &i2c2; 70 i2c2 = &i2c2;
70 }; 71 };
71 cpus { 72 cpus {
@@ -259,7 +260,7 @@
259 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 260 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
260 reg = <0x00600000 0x100000>; 261 reg = <0x00600000 0x100000>;
261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 262 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
262 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 263 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
263 clock-names = "usb_clk", "ehci_clk", "uhpck"; 264 clock-names = "usb_clk", "ehci_clk", "uhpck";
264 status = "disabled"; 265 status = "disabled";
265 }; 266 };
@@ -461,8 +462,8 @@
461 462
462 lcdck: lcdck { 463 lcdck: lcdck {
463 #clock-cells = <0>; 464 #clock-cells = <0>;
464 reg = <4>; 465 reg = <3>;
465 clocks = <&smd>; 466 clocks = <&mck>;
466 }; 467 };
467 468
468 smdck: smdck { 469 smdck: smdck {
@@ -770,7 +771,7 @@
770 reg = <50>; 771 reg = <50>;
771 }; 772 };
772 773
773 lcd_clk: lcd_clk { 774 lcdc_clk: lcdc_clk {
774 #clock-cells = <0>; 775 #clock-cells = <0>;
775 reg = <51>; 776 reg = <51>;
776 }; 777 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 252c3d1bda50..d9176e606173 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -660,7 +660,7 @@
660 #address-cells = <1>; 660 #address-cells = <1>;
661 #size-cells = <0>; 661 #size-cells = <0>;
662 reg = <0xfff01000 0x1000>; 662 reg = <0xfff01000 0x1000>;
663 interrupts = <0 156 4>; 663 interrupts = <0 155 4>;
664 num-cs = <4>; 664 num-cs = <4>;
665 clocks = <&spi_m_clk>; 665 clocks = <&spi_m_clk>;
666 status = "disabled"; 666 status = "disabled";
@@ -713,6 +713,9 @@
713 reg-shift = <2>; 713 reg-shift = <2>;
714 reg-io-width = <4>; 714 reg-io-width = <4>;
715 clocks = <&l4_sp_clk>; 715 clocks = <&l4_sp_clk>;
716 dmas = <&pdma 28>,
717 <&pdma 29>;
718 dma-names = "tx", "rx";
716 }; 719 };
717 720
718 uart1: serial1@ffc03000 { 721 uart1: serial1@ffc03000 {
@@ -722,6 +725,9 @@
722 reg-shift = <2>; 725 reg-shift = <2>;
723 reg-io-width = <4>; 726 reg-io-width = <4>;
724 clocks = <&l4_sp_clk>; 727 clocks = <&l4_sp_clk>;
728 dmas = <&pdma 30>,
729 <&pdma 31>;
730 dma-names = "tx", "rx";
725 }; 731 };
726 732
727 rst: rstmgr@ffd05000 { 733 rst: rstmgr@ffd05000 {
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index ab7891c43231..75742f8f96f3 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -56,6 +56,22 @@
56 model = "Olimex A10-OLinuXino-LIME"; 56 model = "Olimex A10-OLinuXino-LIME";
57 compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; 57 compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
58 58
59 cpus {
60 cpu0: cpu@0 {
61 /*
62 * The A10-Lime is known to be unstable
63 * when running at 1008 MHz
64 */
65 operating-points = <
66 /* kHz uV */
67 912000 1350000
68 864000 1300000
69 624000 1250000
70 >;
71 cooling-max-level = <2>;
72 };
73 };
74
59 soc@01c00000 { 75 soc@01c00000 {
60 emac: ethernet@01c0b000 { 76 emac: ethernet@01c0b000 {
61 pinctrl-names = "default"; 77 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5c2925831f20..eebb7853e00b 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -75,7 +75,6 @@
75 clock-latency = <244144>; /* 8 32k periods */ 75 clock-latency = <244144>; /* 8 32k periods */
76 operating-points = < 76 operating-points = <
77 /* kHz uV */ 77 /* kHz uV */
78 1056000 1500000
79 1008000 1400000 78 1008000 1400000
80 912000 1350000 79 912000 1350000
81 864000 1300000 80 864000 1300000
@@ -83,7 +82,7 @@
83 >; 82 >;
84 #cooling-cells = <2>; 83 #cooling-cells = <2>;
85 cooling-min-level = <0>; 84 cooling-min-level = <0>;
86 cooling-max-level = <4>; 85 cooling-max-level = <3>;
87 }; 86 };
88 }; 87 };
89 88
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index f8818f1edbbe..883cb4873688 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -47,7 +47,6 @@
47 clock-latency = <244144>; /* 8 32k periods */ 47 clock-latency = <244144>; /* 8 32k periods */
48 operating-points = < 48 operating-points = <
49 /* kHz uV */ 49 /* kHz uV */
50 1104000 1500000
51 1008000 1400000 50 1008000 1400000
52 912000 1350000 51 912000 1350000
53 864000 1300000 52 864000 1300000
@@ -57,7 +56,7 @@
57 >; 56 >;
58 #cooling-cells = <2>; 57 #cooling-cells = <2>;
59 cooling-min-level = <0>; 58 cooling-min-level = <0>;
60 cooling-max-level = <6>; 59 cooling-max-level = <5>;
61 }; 60 };
62 }; 61 };
63 62
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 3a8530b79f1c..fdd181792b4b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -105,7 +105,6 @@
105 clock-latency = <244144>; /* 8 32k periods */ 105 clock-latency = <244144>; /* 8 32k periods */
106 operating-points = < 106 operating-points = <
107 /* kHz uV */ 107 /* kHz uV */
108 1008000 1450000
109 960000 1400000 108 960000 1400000
110 912000 1400000 109 912000 1400000
111 864000 1300000 110 864000 1300000
@@ -116,7 +115,7 @@
116 >; 115 >;
117 #cooling-cells = <2>; 116 #cooling-cells = <2>;
118 cooling-min-level = <0>; 117 cooling-min-level = <0>;
119 cooling-max-level = <7>; 118 cooling-max-level = <6>;
120 }; 119 };
121 120
122 cpu@1 { 121 cpu@1 {
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index f2670f638e97..811e72bbe642 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -70,6 +70,7 @@ CONFIG_SCSI=y
70CONFIG_BLK_DEV_SD=y 70CONFIG_BLK_DEV_SD=y
71# CONFIG_SCSI_LOWLEVEL is not set 71# CONFIG_SCSI_LOWLEVEL is not set
72CONFIG_NETDEVICES=y 72CONFIG_NETDEVICES=y
73CONFIG_ARM_AT91_ETHER=y
73CONFIG_MACB=y 74CONFIG_MACB=y
74# CONFIG_NET_VENDOR_BROADCOM is not set 75# CONFIG_NET_VENDOR_BROADCOM is not set
75CONFIG_DM9000=y 76CONFIG_DM9000=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index b7e6b6fba5e0..06075b6d2463 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -99,7 +99,7 @@ CONFIG_PCI_RCAR_GEN2=y
99CONFIG_PCI_RCAR_GEN2_PCIE=y 99CONFIG_PCI_RCAR_GEN2_PCIE=y
100CONFIG_PCIEPORTBUS=y 100CONFIG_PCIEPORTBUS=y
101CONFIG_SMP=y 101CONFIG_SMP=y
102CONFIG_NR_CPUS=8 102CONFIG_NR_CPUS=16
103CONFIG_HIGHPTE=y 103CONFIG_HIGHPTE=y
104CONFIG_CMA=y 104CONFIG_CMA=y
105CONFIG_ARM_APPENDED_DTB=y 105CONFIG_ARM_APPENDED_DTB=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index a097cffa1231..8e108599e1af 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -377,6 +377,7 @@ CONFIG_PWM_TWL=m
377CONFIG_PWM_TWL_LED=m 377CONFIG_PWM_TWL_LED=m
378CONFIG_OMAP_USB2=m 378CONFIG_OMAP_USB2=m
379CONFIG_TI_PIPE3=y 379CONFIG_TI_PIPE3=y
380CONFIG_TWL4030_USB=m
380CONFIG_EXT2_FS=y 381CONFIG_EXT2_FS=y
381CONFIG_EXT3_FS=y 382CONFIG_EXT3_FS=y
382# CONFIG_EXT3_FS_XATTR is not set 383# CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 41d856effe6c..510c747c65b4 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -3,8 +3,6 @@
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_IRQ_DOMAIN_DEBUG=y 4CONFIG_IRQ_DOMAIN_DEBUG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_SYSFS_DEPRECATED=y
7CONFIG_SYSFS_DEPRECATED_V2=y
8CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
9CONFIG_EMBEDDED=y 7CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 8CONFIG_SLAB=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 38840a812924..8f6a5702b696 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -4,6 +4,7 @@ CONFIG_BLK_DEV_INITRD=y
4CONFIG_PERF_EVENTS=y 4CONFIG_PERF_EVENTS=y
5CONFIG_ARCH_SUNXI=y 5CONFIG_ARCH_SUNXI=y
6CONFIG_SMP=y 6CONFIG_SMP=y
7CONFIG_NR_CPUS=8
7CONFIG_AEABI=y 8CONFIG_AEABI=y
8CONFIG_HIGHMEM=y 9CONFIG_HIGHMEM=y
9CONFIG_HIGHPTE=y 10CONFIG_HIGHPTE=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f489fdaa19b8..37fe607a4ede 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -118,8 +118,8 @@ CONFIG_HID_ZEROPLUS=y
118CONFIG_USB=y 118CONFIG_USB=y
119CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 119CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
120CONFIG_USB_MON=y 120CONFIG_USB_MON=y
121CONFIG_USB_ISP1760_HCD=y
122CONFIG_USB_STORAGE=y 121CONFIG_USB_STORAGE=y
122CONFIG_USB_ISP1760=y
123CONFIG_MMC=y 123CONFIG_MMC=y
124CONFIG_MMC_ARMMMCI=y 124CONFIG_MMC_ARMMMCI=y
125CONFIG_NEW_LEDS=y 125CONFIG_NEW_LEDS=y
diff --git a/arch/arm/crypto/aesbs-core.S_shipped b/arch/arm/crypto/aesbs-core.S_shipped
index 71e5fc7cfb18..1d1800f71c5b 100644
--- a/arch/arm/crypto/aesbs-core.S_shipped
+++ b/arch/arm/crypto/aesbs-core.S_shipped
@@ -58,14 +58,18 @@
58# define VFP_ABI_FRAME 0 58# define VFP_ABI_FRAME 0
59# define BSAES_ASM_EXTENDED_KEY 59# define BSAES_ASM_EXTENDED_KEY
60# define XTS_CHAIN_TWEAK 60# define XTS_CHAIN_TWEAK
61# define __ARM_ARCH__ 7 61# define __ARM_ARCH__ __LINUX_ARM_ARCH__
62# define __ARM_MAX_ARCH__ 7
62#endif 63#endif
63 64
64#ifdef __thumb__ 65#ifdef __thumb__
65# define adrl adr 66# define adrl adr
66#endif 67#endif
67 68
68#if __ARM_ARCH__>=7 69#if __ARM_MAX_ARCH__>=7
70.arch armv7-a
71.fpu neon
72
69.text 73.text
70.syntax unified @ ARMv7-capable assembler is expected to handle this 74.syntax unified @ ARMv7-capable assembler is expected to handle this
71#ifdef __thumb2__ 75#ifdef __thumb2__
@@ -74,8 +78,6 @@
74.code 32 78.code 32
75#endif 79#endif
76 80
77.fpu neon
78
79.type _bsaes_decrypt8,%function 81.type _bsaes_decrypt8,%function
80.align 4 82.align 4
81_bsaes_decrypt8: 83_bsaes_decrypt8:
@@ -2095,9 +2097,11 @@ bsaes_xts_decrypt:
2095 vld1.8 {q8}, [r0] @ initial tweak 2097 vld1.8 {q8}, [r0] @ initial tweak
2096 adr r2, .Lxts_magic 2098 adr r2, .Lxts_magic
2097 2099
2100#ifndef XTS_CHAIN_TWEAK
2098 tst r9, #0xf @ if not multiple of 16 2101 tst r9, #0xf @ if not multiple of 16
2099 it ne @ Thumb2 thing, sanity check in ARM 2102 it ne @ Thumb2 thing, sanity check in ARM
2100 subne r9, #0x10 @ subtract another 16 bytes 2103 subne r9, #0x10 @ subtract another 16 bytes
2104#endif
2101 subs r9, #0x80 2105 subs r9, #0x80
2102 2106
2103 blo .Lxts_dec_short 2107 blo .Lxts_dec_short
diff --git a/arch/arm/crypto/bsaes-armv7.pl b/arch/arm/crypto/bsaes-armv7.pl
index be068db960ee..a4d3856e7d24 100644
--- a/arch/arm/crypto/bsaes-armv7.pl
+++ b/arch/arm/crypto/bsaes-armv7.pl
@@ -701,14 +701,18 @@ $code.=<<___;
701# define VFP_ABI_FRAME 0 701# define VFP_ABI_FRAME 0
702# define BSAES_ASM_EXTENDED_KEY 702# define BSAES_ASM_EXTENDED_KEY
703# define XTS_CHAIN_TWEAK 703# define XTS_CHAIN_TWEAK
704# define __ARM_ARCH__ 7 704# define __ARM_ARCH__ __LINUX_ARM_ARCH__
705# define __ARM_MAX_ARCH__ 7
705#endif 706#endif
706 707
707#ifdef __thumb__ 708#ifdef __thumb__
708# define adrl adr 709# define adrl adr
709#endif 710#endif
710 711
711#if __ARM_ARCH__>=7 712#if __ARM_MAX_ARCH__>=7
713.arch armv7-a
714.fpu neon
715
712.text 716.text
713.syntax unified @ ARMv7-capable assembler is expected to handle this 717.syntax unified @ ARMv7-capable assembler is expected to handle this
714#ifdef __thumb2__ 718#ifdef __thumb2__
@@ -717,8 +721,6 @@ $code.=<<___;
717.code 32 721.code 32
718#endif 722#endif
719 723
720.fpu neon
721
722.type _bsaes_decrypt8,%function 724.type _bsaes_decrypt8,%function
723.align 4 725.align 4
724_bsaes_decrypt8: 726_bsaes_decrypt8:
@@ -2076,9 +2078,11 @@ bsaes_xts_decrypt:
2076 vld1.8 {@XMM[8]}, [r0] @ initial tweak 2078 vld1.8 {@XMM[8]}, [r0] @ initial tweak
2077 adr $magic, .Lxts_magic 2079 adr $magic, .Lxts_magic
2078 2080
2081#ifndef XTS_CHAIN_TWEAK
2079 tst $len, #0xf @ if not multiple of 16 2082 tst $len, #0xf @ if not multiple of 16
2080 it ne @ Thumb2 thing, sanity check in ARM 2083 it ne @ Thumb2 thing, sanity check in ARM
2081 subne $len, #0x10 @ subtract another 16 bytes 2084 subne $len, #0x10 @ subtract another 16 bytes
2085#endif
2082 subs $len, #0x80 2086 subs $len, #0x80
2083 2087
2084 blo .Lxts_dec_short 2088 blo .Lxts_dec_short
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index bf0fe99e8ca9..4cf48c3aca13 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -149,29 +149,28 @@ static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
149 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 149 (__boundary - 1 < (end) - 1)? __boundary: (end); \
150}) 150})
151 151
152#define kvm_pgd_index(addr) pgd_index(addr)
153
152static inline bool kvm_page_empty(void *ptr) 154static inline bool kvm_page_empty(void *ptr)
153{ 155{
154 struct page *ptr_page = virt_to_page(ptr); 156 struct page *ptr_page = virt_to_page(ptr);
155 return page_count(ptr_page) == 1; 157 return page_count(ptr_page) == 1;
156} 158}
157 159
158
159#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) 160#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
160#define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) 161#define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp)
161#define kvm_pud_table_empty(kvm, pudp) (0) 162#define kvm_pud_table_empty(kvm, pudp) (0)
162 163
163#define KVM_PREALLOC_LEVEL 0 164#define KVM_PREALLOC_LEVEL 0
164 165
165static inline int kvm_prealloc_hwpgd(struct kvm *kvm, pgd_t *pgd) 166static inline void *kvm_get_hwpgd(struct kvm *kvm)
166{ 167{
167 return 0; 168 return kvm->arch.pgd;
168} 169}
169 170
170static inline void kvm_free_hwpgd(struct kvm *kvm) { } 171static inline unsigned int kvm_get_hwpgd_size(void)
171
172static inline void *kvm_get_hwpgd(struct kvm *kvm)
173{ 172{
174 return kvm->arch.pgd; 173 return PTRS_PER_S2_PGD * sizeof(pgd_t);
175} 174}
176 175
177struct kvm; 176struct kvm;
diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index 80a6501b4d50..c3c45e628e33 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -18,8 +18,11 @@
18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ 18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
19#endif 19#endif
20 20
21/* Keep in sync with mach-at91/include/mach/hardware.h */ 21#ifdef CONFIG_MMU
22#define AT91_IO_P2V(x) ((x) - 0x01000000) 22#define AT91_IO_P2V(x) ((x) - 0x01000000)
23#else
24#define AT91_IO_P2V(x) (x)
25#endif
23 26
24#define AT91_DBGU_SR (0x14) /* Status Register */ 27#define AT91_DBGU_SR (0x14) /* Status Register */
25#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ 28#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e55408e96559..1d60bebea4b8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -246,12 +246,9 @@ static int __get_cpu_architecture(void)
246 if (cpu_arch) 246 if (cpu_arch)
247 cpu_arch += CPU_ARCH_ARMv3; 247 cpu_arch += CPU_ARCH_ARMv3;
248 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { 248 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
249 unsigned int mmfr0;
250
251 /* Revised CPUID format. Read the Memory Model Feature 249 /* Revised CPUID format. Read the Memory Model Feature
252 * Register 0 and check for VMSAv7 or PMSAv7 */ 250 * Register 0 and check for VMSAv7 or PMSAv7 */
253 asm("mrc p15, 0, %0, c0, c1, 4" 251 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
254 : "=r" (mmfr0));
255 if ((mmfr0 & 0x0000000f) >= 0x00000003 || 252 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
256 (mmfr0 & 0x000000f0) >= 0x00000030) 253 (mmfr0 & 0x000000f0) >= 0x00000030)
257 cpu_arch = CPU_ARCH_ARMv7; 254 cpu_arch = CPU_ARCH_ARMv7;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 3e6859bc3e11..5656d79c5a44 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -290,7 +290,7 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
290 phys_addr_t addr = start, end = start + size; 290 phys_addr_t addr = start, end = start + size;
291 phys_addr_t next; 291 phys_addr_t next;
292 292
293 pgd = pgdp + pgd_index(addr); 293 pgd = pgdp + kvm_pgd_index(addr);
294 do { 294 do {
295 next = kvm_pgd_addr_end(addr, end); 295 next = kvm_pgd_addr_end(addr, end);
296 if (!pgd_none(*pgd)) 296 if (!pgd_none(*pgd))
@@ -355,7 +355,7 @@ static void stage2_flush_memslot(struct kvm *kvm,
355 phys_addr_t next; 355 phys_addr_t next;
356 pgd_t *pgd; 356 pgd_t *pgd;
357 357
358 pgd = kvm->arch.pgd + pgd_index(addr); 358 pgd = kvm->arch.pgd + kvm_pgd_index(addr);
359 do { 359 do {
360 next = kvm_pgd_addr_end(addr, end); 360 next = kvm_pgd_addr_end(addr, end);
361 stage2_flush_puds(kvm, pgd, addr, next); 361 stage2_flush_puds(kvm, pgd, addr, next);
@@ -632,6 +632,20 @@ int create_hyp_io_mappings(void *from, void *to, phys_addr_t phys_addr)
632 __phys_to_pfn(phys_addr), PAGE_HYP_DEVICE); 632 __phys_to_pfn(phys_addr), PAGE_HYP_DEVICE);
633} 633}
634 634
635/* Free the HW pgd, one page at a time */
636static void kvm_free_hwpgd(void *hwpgd)
637{
638 free_pages_exact(hwpgd, kvm_get_hwpgd_size());
639}
640
641/* Allocate the HW PGD, making sure that each page gets its own refcount */
642static void *kvm_alloc_hwpgd(void)
643{
644 unsigned int size = kvm_get_hwpgd_size();
645
646 return alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
647}
648
635/** 649/**
636 * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation. 650 * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
637 * @kvm: The KVM struct pointer for the VM. 651 * @kvm: The KVM struct pointer for the VM.
@@ -645,15 +659,31 @@ int create_hyp_io_mappings(void *from, void *to, phys_addr_t phys_addr)
645 */ 659 */
646int kvm_alloc_stage2_pgd(struct kvm *kvm) 660int kvm_alloc_stage2_pgd(struct kvm *kvm)
647{ 661{
648 int ret;
649 pgd_t *pgd; 662 pgd_t *pgd;
663 void *hwpgd;
650 664
651 if (kvm->arch.pgd != NULL) { 665 if (kvm->arch.pgd != NULL) {
652 kvm_err("kvm_arch already initialized?\n"); 666 kvm_err("kvm_arch already initialized?\n");
653 return -EINVAL; 667 return -EINVAL;
654 } 668 }
655 669
670 hwpgd = kvm_alloc_hwpgd();
671 if (!hwpgd)
672 return -ENOMEM;
673
674 /* When the kernel uses more levels of page tables than the
675 * guest, we allocate a fake PGD and pre-populate it to point
676 * to the next-level page table, which will be the real
677 * initial page table pointed to by the VTTBR.
678 *
679 * When KVM_PREALLOC_LEVEL==2, we allocate a single page for
680 * the PMD and the kernel will use folded pud.
681 * When KVM_PREALLOC_LEVEL==1, we allocate 2 consecutive PUD
682 * pages.
683 */
656 if (KVM_PREALLOC_LEVEL > 0) { 684 if (KVM_PREALLOC_LEVEL > 0) {
685 int i;
686
657 /* 687 /*
658 * Allocate fake pgd for the page table manipulation macros to 688 * Allocate fake pgd for the page table manipulation macros to
659 * work. This is not used by the hardware and we have no 689 * work. This is not used by the hardware and we have no
@@ -661,30 +691,32 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
661 */ 691 */
662 pgd = (pgd_t *)kmalloc(PTRS_PER_S2_PGD * sizeof(pgd_t), 692 pgd = (pgd_t *)kmalloc(PTRS_PER_S2_PGD * sizeof(pgd_t),
663 GFP_KERNEL | __GFP_ZERO); 693 GFP_KERNEL | __GFP_ZERO);
694
695 if (!pgd) {
696 kvm_free_hwpgd(hwpgd);
697 return -ENOMEM;
698 }
699
700 /* Plug the HW PGD into the fake one. */
701 for (i = 0; i < PTRS_PER_S2_PGD; i++) {
702 if (KVM_PREALLOC_LEVEL == 1)
703 pgd_populate(NULL, pgd + i,
704 (pud_t *)hwpgd + i * PTRS_PER_PUD);
705 else if (KVM_PREALLOC_LEVEL == 2)
706 pud_populate(NULL, pud_offset(pgd, 0) + i,
707 (pmd_t *)hwpgd + i * PTRS_PER_PMD);
708 }
664 } else { 709 } else {
665 /* 710 /*
666 * Allocate actual first-level Stage-2 page table used by the 711 * Allocate actual first-level Stage-2 page table used by the
667 * hardware for Stage-2 page table walks. 712 * hardware for Stage-2 page table walks.
668 */ 713 */
669 pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, S2_PGD_ORDER); 714 pgd = (pgd_t *)hwpgd;
670 } 715 }
671 716
672 if (!pgd)
673 return -ENOMEM;
674
675 ret = kvm_prealloc_hwpgd(kvm, pgd);
676 if (ret)
677 goto out_err;
678
679 kvm_clean_pgd(pgd); 717 kvm_clean_pgd(pgd);
680 kvm->arch.pgd = pgd; 718 kvm->arch.pgd = pgd;
681 return 0; 719 return 0;
682out_err:
683 if (KVM_PREALLOC_LEVEL > 0)
684 kfree(pgd);
685 else
686 free_pages((unsigned long)pgd, S2_PGD_ORDER);
687 return ret;
688} 720}
689 721
690/** 722/**
@@ -785,11 +817,10 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
785 return; 817 return;
786 818
787 unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE); 819 unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
788 kvm_free_hwpgd(kvm); 820 kvm_free_hwpgd(kvm_get_hwpgd(kvm));
789 if (KVM_PREALLOC_LEVEL > 0) 821 if (KVM_PREALLOC_LEVEL > 0)
790 kfree(kvm->arch.pgd); 822 kfree(kvm->arch.pgd);
791 else 823
792 free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER);
793 kvm->arch.pgd = NULL; 824 kvm->arch.pgd = NULL;
794} 825}
795 826
@@ -799,7 +830,7 @@ static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache
799 pgd_t *pgd; 830 pgd_t *pgd;
800 pud_t *pud; 831 pud_t *pud;
801 832
802 pgd = kvm->arch.pgd + pgd_index(addr); 833 pgd = kvm->arch.pgd + kvm_pgd_index(addr);
803 if (WARN_ON(pgd_none(*pgd))) { 834 if (WARN_ON(pgd_none(*pgd))) {
804 if (!cache) 835 if (!cache)
805 return NULL; 836 return NULL;
@@ -1089,7 +1120,7 @@ static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
1089 pgd_t *pgd; 1120 pgd_t *pgd;
1090 phys_addr_t next; 1121 phys_addr_t next;
1091 1122
1092 pgd = kvm->arch.pgd + pgd_index(addr); 1123 pgd = kvm->arch.pgd + kvm_pgd_index(addr);
1093 do { 1124 do {
1094 /* 1125 /*
1095 * Release kvm_mmu_lock periodically if the memory region is 1126 * Release kvm_mmu_lock periodically if the memory region is
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5e34fb143309..aa4116e9452f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -270,37 +270,35 @@ static void __init at91_pm_sram_init(void)
270 phys_addr_t sram_pbase; 270 phys_addr_t sram_pbase;
271 unsigned long sram_base; 271 unsigned long sram_base;
272 struct device_node *node; 272 struct device_node *node;
273 struct platform_device *pdev; 273 struct platform_device *pdev = NULL;
274 274
275 node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 275 for_each_compatible_node(node, NULL, "mmio-sram") {
276 if (!node) { 276 pdev = of_find_device_by_node(node);
277 pr_warn("%s: failed to find sram node!\n", __func__); 277 if (pdev) {
278 return; 278 of_node_put(node);
279 break;
280 }
279 } 281 }
280 282
281 pdev = of_find_device_by_node(node);
282 if (!pdev) { 283 if (!pdev) {
283 pr_warn("%s: failed to find sram device!\n", __func__); 284 pr_warn("%s: failed to find sram device!\n", __func__);
284 goto put_node; 285 return;
285 } 286 }
286 287
287 sram_pool = dev_get_gen_pool(&pdev->dev); 288 sram_pool = dev_get_gen_pool(&pdev->dev);
288 if (!sram_pool) { 289 if (!sram_pool) {
289 pr_warn("%s: sram pool unavailable!\n", __func__); 290 pr_warn("%s: sram pool unavailable!\n", __func__);
290 goto put_node; 291 return;
291 } 292 }
292 293
293 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); 294 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
294 if (!sram_base) { 295 if (!sram_base) {
295 pr_warn("%s: unable to alloc ocram!\n", __func__); 296 pr_warn("%s: unable to alloc ocram!\n", __func__);
296 goto put_node; 297 return;
297 } 298 }
298 299
299 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 300 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
300 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); 301 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
301
302put_node:
303 of_node_put(node);
304} 302}
305#endif 303#endif
306 304
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index d2c89963af2d..86c0aa819d25 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -44,7 +44,7 @@ static inline void at91rm9200_standby(void)
44 " mcr p15, 0, %0, c7, c0, 4\n\t" 44 " mcr p15, 0, %0, c7, c0, 4\n\t"
45 " str %5, [%1, %2]" 45 " str %5, [%1, %2]"
46 : 46 :
47 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR), 47 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
49 "r" (lpr)); 49 "r" (lpr));
50} 50}
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 556151e85ec4..931f0e302c03 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -25,11 +25,6 @@
25 */ 25 */
26#undef SLOWDOWN_MASTER_CLOCK 26#undef SLOWDOWN_MASTER_CLOCK
27 27
28#define MCKRDY_TIMEOUT 1000
29#define MOSCRDY_TIMEOUT 1000
30#define PLLALOCK_TIMEOUT 1000
31#define PLLBLOCK_TIMEOUT 1000
32
33pmc .req r0 28pmc .req r0
34sdramc .req r1 29sdramc .req r1
35ramc1 .req r2 30ramc1 .req r2
@@ -41,60 +36,42 @@ tmp2 .req r5
41 * Wait until master clock is ready (after switching master clock source) 36 * Wait until master clock is ready (after switching master clock source)
42 */ 37 */
43 .macro wait_mckrdy 38 .macro wait_mckrdy
44 mov tmp2, #MCKRDY_TIMEOUT 391: ldr tmp1, [pmc, #AT91_PMC_SR]
451: sub tmp2, tmp2, #1
46 cmp tmp2, #0
47 beq 2f
48 ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_MCKRDY 40 tst tmp1, #AT91_PMC_MCKRDY
50 beq 1b 41 beq 1b
512:
52 .endm 42 .endm
53 43
54/* 44/*
55 * Wait until master oscillator has stabilized. 45 * Wait until master oscillator has stabilized.
56 */ 46 */
57 .macro wait_moscrdy 47 .macro wait_moscrdy
58 mov tmp2, #MOSCRDY_TIMEOUT 481: ldr tmp1, [pmc, #AT91_PMC_SR]
591: sub tmp2, tmp2, #1
60 cmp tmp2, #0
61 beq 2f
62 ldr tmp1, [pmc, #AT91_PMC_SR]
63 tst tmp1, #AT91_PMC_MOSCS 49 tst tmp1, #AT91_PMC_MOSCS
64 beq 1b 50 beq 1b
652:
66 .endm 51 .endm
67 52
68/* 53/*
69 * Wait until PLLA has locked. 54 * Wait until PLLA has locked.
70 */ 55 */
71 .macro wait_pllalock 56 .macro wait_pllalock
72 mov tmp2, #PLLALOCK_TIMEOUT 571: ldr tmp1, [pmc, #AT91_PMC_SR]
731: sub tmp2, tmp2, #1
74 cmp tmp2, #0
75 beq 2f
76 ldr tmp1, [pmc, #AT91_PMC_SR]
77 tst tmp1, #AT91_PMC_LOCKA 58 tst tmp1, #AT91_PMC_LOCKA
78 beq 1b 59 beq 1b
792:
80 .endm 60 .endm
81 61
82/* 62/*
83 * Wait until PLLB has locked. 63 * Wait until PLLB has locked.
84 */ 64 */
85 .macro wait_pllblock 65 .macro wait_pllblock
86 mov tmp2, #PLLBLOCK_TIMEOUT 661: ldr tmp1, [pmc, #AT91_PMC_SR]
871: sub tmp2, tmp2, #1
88 cmp tmp2, #0
89 beq 2f
90 ldr tmp1, [pmc, #AT91_PMC_SR]
91 tst tmp1, #AT91_PMC_LOCKB 67 tst tmp1, #AT91_PMC_LOCKB
92 beq 1b 68 beq 1b
932:
94 .endm 69 .endm
95 70
96 .text 71 .text
97 72
73 .arm
74
98/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, 75/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
99 * void __iomem *ramc1, int memctrl) 76 * void __iomem *ramc1, int memctrl)
100 */ 77 */
@@ -134,6 +111,16 @@ ddr_sr_enable:
134 cmp memctrl, #AT91_MEMCTRL_DDRSDR 111 cmp memctrl, #AT91_MEMCTRL_DDRSDR
135 bne sdr_sr_enable 112 bne sdr_sr_enable
136 113
114 /* LPDDR1 --> force DDR2 mode during self-refresh */
115 ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
116 str tmp1, .saved_sam9_mdr
117 bic tmp1, tmp1, #~AT91_DDRSDRC_MD
118 cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
119 ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
120 biceq tmp1, tmp1, #AT91_DDRSDRC_MD
121 orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
122 streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
123
137 /* prepare for DDRAM self-refresh mode */ 124 /* prepare for DDRAM self-refresh mode */
138 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR] 125 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
139 str tmp1, .saved_sam9_lpr 126 str tmp1, .saved_sam9_lpr
@@ -142,14 +129,26 @@ ddr_sr_enable:
142 129
143 /* figure out if we use the second ram controller */ 130 /* figure out if we use the second ram controller */
144 cmp ramc1, #0 131 cmp ramc1, #0
145 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 132 beq ddr_no_2nd_ctrl
146 strne tmp2, .saved_sam9_lpr1 133
147 bicne tmp2, #AT91_DDRSDRC_LPCB 134 ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
148 orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH 135 str tmp2, .saved_sam9_mdr1
136 bic tmp2, tmp2, #~AT91_DDRSDRC_MD
137 cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
138 ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
139 biceq tmp2, tmp2, #AT91_DDRSDRC_MD
140 orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
141 streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
142
143 ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
144 str tmp2, .saved_sam9_lpr1
145 bic tmp2, #AT91_DDRSDRC_LPCB
146 orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
149 147
150 /* Enable DDRAM self-refresh mode */ 148 /* Enable DDRAM self-refresh mode */
149 str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
150ddr_no_2nd_ctrl:
151 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 151 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
152 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
153 152
154 b sdr_sr_done 153 b sdr_sr_done
155 154
@@ -208,6 +207,7 @@ sdr_sr_done:
208 /* Turn off the main oscillator */ 207 /* Turn off the main oscillator */
209 ldr tmp1, [pmc, #AT91_CKGR_MOR] 208 ldr tmp1, [pmc, #AT91_CKGR_MOR]
210 bic tmp1, tmp1, #AT91_PMC_MOSCEN 209 bic tmp1, tmp1, #AT91_PMC_MOSCEN
210 orr tmp1, tmp1, #AT91_PMC_KEY
211 str tmp1, [pmc, #AT91_CKGR_MOR] 211 str tmp1, [pmc, #AT91_CKGR_MOR]
212 212
213 /* Wait for interrupt */ 213 /* Wait for interrupt */
@@ -216,6 +216,7 @@ sdr_sr_done:
216 /* Turn on the main oscillator */ 216 /* Turn on the main oscillator */
217 ldr tmp1, [pmc, #AT91_CKGR_MOR] 217 ldr tmp1, [pmc, #AT91_CKGR_MOR]
218 orr tmp1, tmp1, #AT91_PMC_MOSCEN 218 orr tmp1, tmp1, #AT91_PMC_MOSCEN
219 orr tmp1, tmp1, #AT91_PMC_KEY
219 str tmp1, [pmc, #AT91_CKGR_MOR] 220 str tmp1, [pmc, #AT91_CKGR_MOR]
220 221
221 wait_moscrdy 222 wait_moscrdy
@@ -280,12 +281,17 @@ sdr_sr_done:
280 */ 281 */
281 cmp memctrl, #AT91_MEMCTRL_DDRSDR 282 cmp memctrl, #AT91_MEMCTRL_DDRSDR
282 bne sdr_en_restore 283 bne sdr_en_restore
284 /* Restore MDR in case of LPDDR1 */
285 ldr tmp1, .saved_sam9_mdr
286 str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
283 /* Restore LPR on AT91 with DDRAM */ 287 /* Restore LPR on AT91 with DDRAM */
284 ldr tmp1, .saved_sam9_lpr 288 ldr tmp1, .saved_sam9_lpr
285 str tmp1, [sdramc, #AT91_DDRSDRC_LPR] 289 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
286 290
287 /* if we use the second ram controller */ 291 /* if we use the second ram controller */
288 cmp ramc1, #0 292 cmp ramc1, #0
293 ldrne tmp2, .saved_sam9_mdr1
294 strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
289 ldrne tmp2, .saved_sam9_lpr1 295 ldrne tmp2, .saved_sam9_lpr1
290 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR] 296 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
291 297
@@ -319,5 +325,11 @@ ram_restored:
319.saved_sam9_lpr1: 325.saved_sam9_lpr1:
320 .word 0 326 .word 0
321 327
328.saved_sam9_mdr:
329 .word 0
330
331.saved_sam9_mdr1:
332 .word 0
333
322ENTRY(at91_slow_clock_sz) 334ENTRY(at91_slow_clock_sz)
323 .word .-at91_slow_clock 335 .word .-at91_slow_clock
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 3f32c47a6d74..d2e9f12d12f1 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,8 +126,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
126 */ 126 */
127void exynos_cpu_power_down(int cpu) 127void exynos_cpu_power_down(int cpu)
128{ 128{
129 if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") || 129 if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
130 of_machine_is_compatible("samsung,exynos5800"))) {
131 /* 130 /*
132 * Bypass power down for CPU0 during suspend. Check for 131 * Bypass power down for CPU0 during suspend. Check for
133 * the SYS_PWR_REG value to decide if we are suspending 132 * the SYS_PWR_REG value to decide if we are suspending
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 20f267121b3e..37266a826437 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -161,6 +161,34 @@ no_clk:
161 of_genpd_add_provider_simple(np, &pd->pd); 161 of_genpd_add_provider_simple(np, &pd->pd);
162 } 162 }
163 163
164 /* Assign the child power domains to their parents */
165 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
166 struct generic_pm_domain *child_domain, *parent_domain;
167 struct of_phandle_args args;
168
169 args.np = np;
170 args.args_count = 0;
171 child_domain = of_genpd_get_from_provider(&args);
172 if (!child_domain)
173 continue;
174
175 if (of_parse_phandle_with_args(np, "power-domains",
176 "#power-domain-cells", 0, &args) != 0)
177 continue;
178
179 parent_domain = of_genpd_get_from_provider(&args);
180 if (!parent_domain)
181 continue;
182
183 if (pm_genpd_add_subdomain(parent_domain, child_domain))
184 pr_warn("%s failed to add subdomain: %s\n",
185 parent_domain->name, child_domain->name);
186 else
187 pr_info("%s has as child subdomain: %s.\n",
188 parent_domain->name, child_domain->name);
189 of_node_put(np);
190 }
191
164 return 0; 192 return 0;
165} 193}
166arch_initcall(exynos4_pm_init_power_domain); 194arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 52e2b1a2fddb..318d127df147 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
87static u32 exynos_irqwake_intmask = 0xffffffff; 87static u32 exynos_irqwake_intmask = 0xffffffff;
88 88
89static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 89static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
90 { 73, BIT(1) }, /* RTC alarm */ 90 { 105, BIT(1) }, /* RTC alarm */
91 { 74, BIT(2) }, /* RTC tick */ 91 { 106, BIT(2) }, /* RTC tick */
92 { /* sentinel */ }, 92 { /* sentinel */ },
93}; 93};
94 94
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4ad6e473cf83..9de3412af406 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -211,8 +211,9 @@ static void __init imx6q_1588_init(void)
211 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad 211 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
212 * (external OSC), and we need to clear the bit. 212 * (external OSC), and we need to clear the bit.
213 */ 213 */
214 clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : 214 clksel = clk_is_match(ptp_clk, enet_ref) ?
215 IMX6Q_GPR1_ENET_CLK_SEL_PAD; 215 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
216 IMX6Q_GPR1_ENET_CLK_SEL_PAD;
216 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 217 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
217 if (!IS_ERR(gpr)) 218 if (!IS_ERR(gpr))
218 regmap_update_bits(gpr, IOMUXC_GPR1, 219 regmap_update_bits(gpr, IOMUXC_GPR1,
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2a2f4d56e4c8..25f1beea453e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -720,6 +720,8 @@ static const char * __init omap_get_family(void)
720 return kasprintf(GFP_KERNEL, "OMAP4"); 720 return kasprintf(GFP_KERNEL, "OMAP4");
721 else if (soc_is_omap54xx()) 721 else if (soc_is_omap54xx())
722 return kasprintf(GFP_KERNEL, "OMAP5"); 722 return kasprintf(GFP_KERNEL, "OMAP5");
723 else if (soc_is_am33xx() || soc_is_am335x())
724 return kasprintf(GFP_KERNEL, "AM33xx");
723 else if (soc_is_am43xx()) 725 else if (soc_is_am43xx())
724 return kasprintf(GFP_KERNEL, "AM43xx"); 726 return kasprintf(GFP_KERNEL, "AM43xx");
725 else if (soc_is_dra7xx()) 727 else if (soc_is_dra7xx())
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 92afb723dcfc..355b08936871 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1692,16 +1692,15 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1692 if (ret == -EBUSY) 1692 if (ret == -EBUSY)
1693 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); 1693 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1694 1694
1695 if (!ret) { 1695 if (oh->clkdm) {
1696 /* 1696 /*
1697 * Set the clockdomain to HW_AUTO, assuming that the 1697 * Set the clockdomain to HW_AUTO, assuming that the
1698 * previous state was HW_AUTO. 1698 * previous state was HW_AUTO.
1699 */ 1699 */
1700 if (oh->clkdm && hwsup) 1700 if (hwsup)
1701 clkdm_allow_idle(oh->clkdm); 1701 clkdm_allow_idle(oh->clkdm);
1702 } else { 1702
1703 if (oh->clkdm) 1703 clkdm_hwmod_disable(oh->clkdm, oh);
1704 clkdm_hwmod_disable(oh->clkdm, oh);
1705 } 1704 }
1706 1705
1707 return ret; 1706 return ret;
@@ -2698,6 +2697,7 @@ static int __init _register(struct omap_hwmod *oh)
2698 INIT_LIST_HEAD(&oh->master_ports); 2697 INIT_LIST_HEAD(&oh->master_ports);
2699 INIT_LIST_HEAD(&oh->slave_ports); 2698 INIT_LIST_HEAD(&oh->slave_ports);
2700 spin_lock_init(&oh->_lock); 2699 spin_lock_init(&oh->_lock);
2700 lockdep_set_class(&oh->_lock, &oh->hwmod_key);
2701 2701
2702 oh->_state = _HWMOD_STATE_REGISTERED; 2702 oh->_state = _HWMOD_STATE_REGISTERED;
2703 2703
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 9d4bec6ee742..9611c91d9b82 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -674,6 +674,7 @@ struct omap_hwmod {
674 u32 _sysc_cache; 674 u32 _sysc_cache;
675 void __iomem *_mpu_rt_va; 675 void __iomem *_mpu_rt_va;
676 spinlock_t _lock; 676 spinlock_t _lock;
677 struct lock_class_key hwmod_key; /* unique lock class */
677 struct list_head node; 678 struct list_head node;
678 struct omap_hwmod_ocp_if *_mpu_port; 679 struct omap_hwmod_ocp_if *_mpu_port;
679 unsigned int (*xlate_irq)(unsigned int); 680 unsigned int (*xlate_irq)(unsigned int);
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e8692e7675b8..16fe7a1b7a35 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1466,55 +1466,18 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1466 * 1466 *
1467 */ 1467 */
1468 1468
1469static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { 1469static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1470 .name = "pcie", 1470 .name = "pcie",
1471}; 1471};
1472 1472
1473/* pcie1 */ 1473/* pcie1 */
1474static struct omap_hwmod dra7xx_pcie1_hwmod = { 1474static struct omap_hwmod dra7xx_pciess1_hwmod = {
1475 .name = "pcie1", 1475 .name = "pcie1",
1476 .class = &dra7xx_pcie_hwmod_class, 1476 .class = &dra7xx_pciess_hwmod_class,
1477 .clkdm_name = "pcie_clkdm", 1477 .clkdm_name = "pcie_clkdm",
1478 .main_clk = "l4_root_clk_div", 1478 .main_clk = "l4_root_clk_div",
1479 .prcm = { 1479 .prcm = {
1480 .omap4 = { 1480 .omap4 = {
1481 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL,
1483 },
1484 },
1485};
1486
1487/* pcie2 */
1488static struct omap_hwmod dra7xx_pcie2_hwmod = {
1489 .name = "pcie2",
1490 .class = &dra7xx_pcie_hwmod_class,
1491 .clkdm_name = "pcie_clkdm",
1492 .main_clk = "l4_root_clk_div",
1493 .prcm = {
1494 .omap4 = {
1495 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1496 .modulemode = MODULEMODE_SWCTRL,
1497 },
1498 },
1499};
1500
1501/*
1502 * 'PCIE PHY' class
1503 *
1504 */
1505
1506static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1507 .name = "pcie-phy",
1508};
1509
1510/* pcie1 phy */
1511static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1512 .name = "pcie1-phy",
1513 .class = &dra7xx_pcie_phy_hwmod_class,
1514 .clkdm_name = "l3init_clkdm",
1515 .main_clk = "l4_root_clk_div",
1516 .prcm = {
1517 .omap4 = {
1518 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, 1481 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1519 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, 1482 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_SWCTRL, 1483 .modulemode = MODULEMODE_SWCTRL,
@@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1522 }, 1485 },
1523}; 1486};
1524 1487
1525/* pcie2 phy */ 1488/* pcie2 */
1526static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { 1489static struct omap_hwmod dra7xx_pciess2_hwmod = {
1527 .name = "pcie2-phy", 1490 .name = "pcie2",
1528 .class = &dra7xx_pcie_phy_hwmod_class, 1491 .class = &dra7xx_pciess_hwmod_class,
1529 .clkdm_name = "l3init_clkdm", 1492 .clkdm_name = "pcie_clkdm",
1530 .main_clk = "l4_root_clk_div", 1493 .main_clk = "l4_root_clk_div",
1531 .prcm = { 1494 .prcm = {
1532 .omap4 = { 1495 .omap4 = {
@@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2877 .user = OCP_USER_MPU | OCP_USER_SDMA, 2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878}; 2841};
2879 2842
2880/* l3_main_1 -> pcie1 */ 2843/* l3_main_1 -> pciess1 */
2881static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { 2844static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2882 .master = &dra7xx_l3_main_1_hwmod, 2845 .master = &dra7xx_l3_main_1_hwmod,
2883 .slave = &dra7xx_pcie1_hwmod, 2846 .slave = &dra7xx_pciess1_hwmod,
2884 .clk = "l3_iclk_div", 2847 .clk = "l3_iclk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA, 2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886}; 2849};
2887 2850
2888/* l4_cfg -> pcie1 */ 2851/* l4_cfg -> pciess1 */
2889static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { 2852static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2890 .master = &dra7xx_l4_cfg_hwmod, 2853 .master = &dra7xx_l4_cfg_hwmod,
2891 .slave = &dra7xx_pcie1_hwmod, 2854 .slave = &dra7xx_pciess1_hwmod,
2892 .clk = "l4_root_clk_div", 2855 .clk = "l4_root_clk_div",
2893 .user = OCP_USER_MPU | OCP_USER_SDMA, 2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894}; 2857};
2895 2858
2896/* l3_main_1 -> pcie2 */ 2859/* l3_main_1 -> pciess2 */
2897static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { 2860static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2898 .master = &dra7xx_l3_main_1_hwmod, 2861 .master = &dra7xx_l3_main_1_hwmod,
2899 .slave = &dra7xx_pcie2_hwmod, 2862 .slave = &dra7xx_pciess2_hwmod,
2900 .clk = "l3_iclk_div", 2863 .clk = "l3_iclk_div",
2901 .user = OCP_USER_MPU | OCP_USER_SDMA, 2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2902}; 2865};
2903 2866
2904/* l4_cfg -> pcie2 */ 2867/* l4_cfg -> pciess2 */
2905static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { 2868static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2906 .master = &dra7xx_l4_cfg_hwmod,
2907 .slave = &dra7xx_pcie2_hwmod,
2908 .clk = "l4_root_clk_div",
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* l4_cfg -> pcie1 phy */
2913static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2914 .master = &dra7xx_l4_cfg_hwmod,
2915 .slave = &dra7xx_pcie1_phy_hwmod,
2916 .clk = "l4_root_clk_div",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2918};
2919
2920/* l4_cfg -> pcie2 phy */
2921static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2922 .master = &dra7xx_l4_cfg_hwmod, 2869 .master = &dra7xx_l4_cfg_hwmod,
2923 .slave = &dra7xx_pcie2_phy_hwmod, 2870 .slave = &dra7xx_pciess2_hwmod,
2924 .clk = "l4_root_clk_div", 2871 .clk = "l4_root_clk_div",
2925 .user = OCP_USER_MPU | OCP_USER_SDMA, 2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2926}; 2873};
@@ -3327,12 +3274,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3327 &dra7xx_l4_cfg__mpu, 3274 &dra7xx_l4_cfg__mpu,
3328 &dra7xx_l4_cfg__ocp2scp1, 3275 &dra7xx_l4_cfg__ocp2scp1,
3329 &dra7xx_l4_cfg__ocp2scp3, 3276 &dra7xx_l4_cfg__ocp2scp3,
3330 &dra7xx_l3_main_1__pcie1, 3277 &dra7xx_l3_main_1__pciess1,
3331 &dra7xx_l4_cfg__pcie1, 3278 &dra7xx_l4_cfg__pciess1,
3332 &dra7xx_l3_main_1__pcie2, 3279 &dra7xx_l3_main_1__pciess2,
3333 &dra7xx_l4_cfg__pcie2, 3280 &dra7xx_l4_cfg__pciess2,
3334 &dra7xx_l4_cfg__pcie1_phy,
3335 &dra7xx_l4_cfg__pcie2_phy,
3336 &dra7xx_l3_main_1__qspi, 3281 &dra7xx_l3_main_1__qspi,
3337 &dra7xx_l4_per3__rtcss, 3282 &dra7xx_l4_per3__rtcss,
3338 &dra7xx_l4_cfg__sata, 3283 &dra7xx_l4_cfg__sata,
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 190fa43e7479..e642b079e9f3 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -173,6 +173,7 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
173 173
174static void __init omap3_evm_legacy_init(void) 174static void __init omap3_evm_legacy_init(void)
175{ 175{
176 hsmmc2_internal_input_clk();
176 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149); 177 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
177} 178}
178 179
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617a6c11..d6d6bc39e05c 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -252,10 +252,10 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
252{ 252{
253 saved_mask[0] = 253 saved_mask[0] =
254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 254 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
255 OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 255 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
256 saved_mask[1] = 256 saved_mask[1] =
257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 257 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
258 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 258 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
259 259
260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, 260 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
261 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 261 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 7d8eab857a93..f6d02e4cbcda 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -36,6 +36,7 @@
36#include <linux/platform_data/video-pxafb.h> 36#include <linux/platform_data/video-pxafb.h>
37#include <mach/bitfield.h> 37#include <mach/bitfield.h>
38#include <linux/platform_data/mmc-pxamci.h> 38#include <linux/platform_data/mmc-pxamci.h>
39#include <linux/smc91x.h>
39 40
40#include "generic.h" 41#include "generic.h"
41#include "devices.h" 42#include "devices.h"
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 0eecd83c624e..89a7c06570d3 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -11,6 +11,7 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/bitops.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/module.h> 16#include <linux/module.h>
16#include <linux/interrupt.h> 17#include <linux/interrupt.h>
@@ -40,7 +41,6 @@
40#define ICHP_VAL_IRQ (1 << 31) 41#define ICHP_VAL_IRQ (1 << 31)
41#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) 42#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
42#define IPR_VALID (1 << 31) 43#define IPR_VALID (1 << 31)
43#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
44 44
45#define MAX_INTERNAL_IRQS 128 45#define MAX_INTERNAL_IRQS 128
46 46
@@ -51,6 +51,7 @@
51static void __iomem *pxa_irq_base; 51static void __iomem *pxa_irq_base;
52static int pxa_internal_irq_nr; 52static int pxa_internal_irq_nr;
53static bool cpu_has_ipr; 53static bool cpu_has_ipr;
54static struct irq_domain *pxa_irq_domain;
54 55
55static inline void __iomem *irq_base(int i) 56static inline void __iomem *irq_base(int i)
56{ 57{
@@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i)
66void pxa_mask_irq(struct irq_data *d) 67void pxa_mask_irq(struct irq_data *d)
67{ 68{
68 void __iomem *base = irq_data_get_irq_chip_data(d); 69 void __iomem *base = irq_data_get_irq_chip_data(d);
70 irq_hw_number_t irq = irqd_to_hwirq(d);
69 uint32_t icmr = __raw_readl(base + ICMR); 71 uint32_t icmr = __raw_readl(base + ICMR);
70 72
71 icmr &= ~(1 << IRQ_BIT(d->irq)); 73 icmr &= ~BIT(irq & 0x1f);
72 __raw_writel(icmr, base + ICMR); 74 __raw_writel(icmr, base + ICMR);
73} 75}
74 76
75void pxa_unmask_irq(struct irq_data *d) 77void pxa_unmask_irq(struct irq_data *d)
76{ 78{
77 void __iomem *base = irq_data_get_irq_chip_data(d); 79 void __iomem *base = irq_data_get_irq_chip_data(d);
80 irq_hw_number_t irq = irqd_to_hwirq(d);
78 uint32_t icmr = __raw_readl(base + ICMR); 81 uint32_t icmr = __raw_readl(base + ICMR);
79 82
80 icmr |= 1 << IRQ_BIT(d->irq); 83 icmr |= BIT(irq & 0x1f);
81 __raw_writel(icmr, base + ICMR); 84 __raw_writel(icmr, base + ICMR);
82} 85}
83 86
@@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
118 } while (1); 121 } while (1);
119} 122}
120 123
121void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) 124static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
125 irq_hw_number_t hw)
122{ 126{
123 int irq, i, n; 127 void __iomem *base = irq_base(hw / 32);
124 128
125 BUG_ON(irq_nr > MAX_INTERNAL_IRQS); 129 /* initialize interrupt priority */
130 if (cpu_has_ipr)
131 __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
132
133 irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
134 handle_level_irq);
135 irq_set_chip_data(virq, base);
136 set_irq_flags(virq, IRQF_VALID);
137
138 return 0;
139}
140
141static struct irq_domain_ops pxa_irq_ops = {
142 .map = pxa_irq_map,
143 .xlate = irq_domain_xlate_onecell,
144};
145
146static __init void
147pxa_init_irq_common(struct device_node *node, int irq_nr,
148 int (*fn)(struct irq_data *, unsigned int))
149{
150 int n;
126 151
127 pxa_internal_irq_nr = irq_nr; 152 pxa_internal_irq_nr = irq_nr;
128 cpu_has_ipr = !cpu_is_pxa25x(); 153 pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
129 pxa_irq_base = io_p2v(0x40d00000); 154 PXA_IRQ(0), 0,
155 &pxa_irq_ops, NULL);
156 if (!pxa_irq_domain)
157 panic("Unable to add PXA IRQ domain\n");
158 irq_set_default_host(pxa_irq_domain);
130 159
131 for (n = 0; n < irq_nr; n += 32) { 160 for (n = 0; n < irq_nr; n += 32) {
132 void __iomem *base = irq_base(n >> 5); 161 void __iomem *base = irq_base(n >> 5);
133 162
134 __raw_writel(0, base + ICMR); /* disable all IRQs */ 163 __raw_writel(0, base + ICMR); /* disable all IRQs */
135 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 164 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
136 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
137 /* initialize interrupt priority */
138 if (cpu_has_ipr)
139 __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
140
141 irq = PXA_IRQ(i);
142 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
143 handle_level_irq);
144 irq_set_chip_data(irq, base);
145 set_irq_flags(irq, IRQF_VALID);
146 }
147 } 165 }
148
149 /* only unmasked interrupts kick us out of idle */ 166 /* only unmasked interrupts kick us out of idle */
150 __raw_writel(1, irq_base(0) + ICCR); 167 __raw_writel(1, irq_base(0) + ICCR);
151 168
152 pxa_internal_irq_chip.irq_set_wake = fn; 169 pxa_internal_irq_chip.irq_set_wake = fn;
153} 170}
154 171
172void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
173{
174 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
175
176 pxa_irq_base = io_p2v(0x40d00000);
177 cpu_has_ipr = !cpu_is_pxa25x();
178 pxa_init_irq_common(NULL, irq_nr, fn);
179}
180
155#ifdef CONFIG_PM 181#ifdef CONFIG_PM
156static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; 182static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
157static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; 183static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
@@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = {
203}; 229};
204 230
205#ifdef CONFIG_OF 231#ifdef CONFIG_OF
206static struct irq_domain *pxa_irq_domain;
207
208static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
209 irq_hw_number_t hw)
210{
211 void __iomem *base = irq_base(hw / 32);
212
213 /* initialize interrupt priority */
214 if (cpu_has_ipr)
215 __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
216
217 irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
218 handle_level_irq);
219 irq_set_chip_data(hw, base);
220 set_irq_flags(hw, IRQF_VALID);
221
222 return 0;
223}
224
225static struct irq_domain_ops pxa_irq_ops = {
226 .map = pxa_irq_map,
227 .xlate = irq_domain_xlate_onecell,
228};
229
230static const struct of_device_id intc_ids[] __initconst = { 232static const struct of_device_id intc_ids[] __initconst = {
231 { .compatible = "marvell,pxa-intc", }, 233 { .compatible = "marvell,pxa-intc", },
232 {} 234 {}
@@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
236{ 238{
237 struct device_node *node; 239 struct device_node *node;
238 struct resource res; 240 struct resource res;
239 int n, ret; 241 int ret;
240 242
241 node = of_find_matching_node(NULL, intc_ids); 243 node = of_find_matching_node(NULL, intc_ids);
242 if (!node) { 244 if (!node) {
@@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
267 return; 269 return;
268 } 270 }
269 271
270 pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, 272 pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
271 &pxa_irq_ops, NULL);
272 if (!pxa_irq_domain)
273 panic("Unable to add PXA IRQ domain\n");
274
275 irq_set_default_host(pxa_irq_domain);
276
277 for (n = 0; n < pxa_internal_irq_nr; n += 32) {
278 void __iomem *base = irq_base(n >> 5);
279
280 __raw_writel(0, base + ICMR); /* disable all IRQs */
281 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
282 }
283
284 /* only unmasked interrupts kick us out of idle */
285 __raw_writel(1, irq_base(0) + ICCR);
286
287 pxa_internal_irq_chip.irq_set_wake = fn;
288} 273}
289#endif /* CONFIG_OF */ 274#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 28da319d389f..eaee2c20b189 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -195,7 +195,7 @@ static struct resource smc91x_resources[] = {
195}; 195};
196 196
197struct smc91x_platdata smc91x_platdata = { 197struct smc91x_platdata smc91x_platdata = {
198 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT; 198 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
199}; 199};
200 200
201static struct platform_device smc91x_device = { 201static struct platform_device smc91x_device = {
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 205f9bf3821e..ac2ae5c71ab4 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
412}; 412};
413 413
414static struct platform_device can_regulator_device = { 414static struct platform_device can_regulator_device = {
415 .name = "reg-fixed-volage", 415 .name = "reg-fixed-voltage",
416 .id = 0, 416 .id = 0,
417 .dev = { 417 .dev = {
418 .platform_data = &can_regulator_pdata, 418 .platform_data = &can_regulator_pdata,
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 7b0cd3172354..af868d258e66 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -268,8 +268,8 @@ static int neponset_probe(struct platform_device *dev)
268 .id = 0, 268 .id = 0,
269 .res = smc91x_resources, 269 .res = smc91x_resources,
270 .num_res = ARRAY_SIZE(smc91x_resources), 270 .num_res = ARRAY_SIZE(smc91x_resources),
271 .data = &smc91c_platdata, 271 .data = &smc91x_platdata,
272 .size_data = sizeof(smc91c_platdata), 272 .size_data = sizeof(smc91x_platdata),
273 }; 273 };
274 int ret, irq; 274 int ret, irq;
275 275
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 696fd0fe4806..1525d7b5f1b7 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -54,7 +54,7 @@ static struct platform_device smc91x_device = {
54 .num_resources = ARRAY_SIZE(smc91x_resources), 54 .num_resources = ARRAY_SIZE(smc91x_resources),
55 .resource = smc91x_resources, 55 .resource = smc91x_resources,
56 .dev = { 56 .dev = {
57 .platform_data = &smc91c_platdata, 57 .platform_data = &smc91x_platdata,
58 }, 58 },
59}; 59};
60 60
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 483cb467bf65..a0f3b1cd497c 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -45,6 +45,6 @@ extern char secondary_trampoline, secondary_trampoline_end;
45 45
46extern unsigned long socfpga_cpu1start_addr; 46extern unsigned long socfpga_cpu1start_addr;
47 47
48#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 48#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
49 49
50#endif 50#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 383d61e138af..f5e597c207b9 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -23,6 +23,7 @@
23#include <asm/hardware/cache-l2x0.h> 23#include <asm/hardware/cache-l2x0.h>
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/cacheflush.h>
26 27
27#include "core.h" 28#include "core.h"
28 29
@@ -73,6 +74,10 @@ void __init socfpga_sysmgr_init(void)
73 (u32 *) &socfpga_cpu1start_addr)) 74 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 75 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 76
77 /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
78 smp_wmb();
79 sync_cache_w(&socfpga_cpu1start_addr);
80
76 sys_manager_base_addr = of_iomap(np, 0); 81 sys_manager_base_addr = of_iomap(np, 0);
77 82
78 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); 83 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index b067390cef4e..b373acade338 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -18,6 +18,7 @@ static const char *stih41x_dt_match[] __initdata = {
18 "st,stih415", 18 "st,stih415",
19 "st,stih416", 19 "st,stih416",
20 "st,stih407", 20 "st,stih407",
21 "st,stih410",
21 "st,stih418", 22 "st,stih418",
22 NULL 23 NULL
23}; 24};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index a77604fbaf25..81502b90dd91 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,10 +1,12 @@
1menuconfig ARCH_SUNXI 1menuconfig ARCH_SUNXI
2 bool "Allwinner SoCs" if ARCH_MULTI_V7 2 bool "Allwinner SoCs" if ARCH_MULTI_V7
3 select ARCH_REQUIRE_GPIOLIB 3 select ARCH_REQUIRE_GPIOLIB
4 select ARCH_HAS_RESET_CONTROLLER
4 select CLKSRC_MMIO 5 select CLKSRC_MMIO
5 select GENERIC_IRQ_CHIP 6 select GENERIC_IRQ_CHIP
6 select PINCTRL 7 select PINCTRL
7 select SUN4I_TIMER 8 select SUN4I_TIMER
9 select RESET_CONTROLLER
8 10
9if ARCH_SUNXI 11if ARCH_SUNXI
10 12
@@ -20,10 +22,8 @@ config MACH_SUN5I
20config MACH_SUN6I 22config MACH_SUN6I
21 bool "Allwinner A31 (sun6i) SoCs support" 23 bool "Allwinner A31 (sun6i) SoCs support"
22 default ARCH_SUNXI 24 default ARCH_SUNXI
23 select ARCH_HAS_RESET_CONTROLLER
24 select ARM_GIC 25 select ARM_GIC
25 select MFD_SUN6I_PRCM 26 select MFD_SUN6I_PRCM
26 select RESET_CONTROLLER
27 select SUN5I_HSTIMER 27 select SUN5I_HSTIMER
28 28
29config MACH_SUN7I 29config MACH_SUN7I
@@ -37,16 +37,12 @@ config MACH_SUN7I
37config MACH_SUN8I 37config MACH_SUN8I
38 bool "Allwinner A23 (sun8i) SoCs support" 38 bool "Allwinner A23 (sun8i) SoCs support"
39 default ARCH_SUNXI 39 default ARCH_SUNXI
40 select ARCH_HAS_RESET_CONTROLLER
41 select ARM_GIC 40 select ARM_GIC
42 select MFD_SUN6I_PRCM 41 select MFD_SUN6I_PRCM
43 select RESET_CONTROLLER
44 42
45config MACH_SUN9I 43config MACH_SUN9I
46 bool "Allwinner (sun9i) SoCs support" 44 bool "Allwinner (sun9i) SoCs support"
47 default ARCH_SUNXI 45 default ARCH_SUNXI
48 select ARCH_HAS_RESET_CONTROLLER
49 select ARM_GIC 46 select ARM_GIC
50 select RESET_CONTROLLER
51 47
52endif 48endif
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c6c7696b8db9..8f15f70622a6 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1131,23 +1131,22 @@ static void __init l2c310_of_parse(const struct device_node *np,
1131 } 1131 }
1132 1132
1133 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1133 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1134 if (ret) 1134 if (!ret) {
1135 return; 1135 switch (assoc) {
1136 1136 case 16:
1137 switch (assoc) { 1137 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1138 case 16: 1138 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
1139 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1139 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1140 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16; 1140 break;
1141 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1141 case 8:
1142 break; 1142 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1143 case 8: 1143 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1144 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1144 break;
1145 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1145 default:
1146 break; 1146 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
1147 default: 1147 assoc);
1148 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", 1148 break;
1149 assoc); 1149 }
1150 break;
1151 } 1150 }
1152 1151
1153 prefetch = l2x0_saved_regs.prefetch_ctrl; 1152 prefetch = l2x0_saved_regs.prefetch_ctrl;
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 170a116d1b29..c27447653903 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -171,7 +171,7 @@ static int __dma_supported(struct device *dev, u64 mask, bool warn)
171 */ 171 */
172 if (sizeof(mask) != sizeof(dma_addr_t) && 172 if (sizeof(mask) != sizeof(dma_addr_t) &&
173 mask > (dma_addr_t)~0 && 173 mask > (dma_addr_t)~0 &&
174 dma_to_pfn(dev, ~0) < max_pfn) { 174 dma_to_pfn(dev, ~0) < max_pfn - 1) {
175 if (warn) { 175 if (warn) {
176 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", 176 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
177 mask); 177 mask);
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index a982dc3190df..6333d9c17875 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -552,6 +552,7 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
552 552
553 pr_alert("Unhandled fault: %s (0x%03x) at 0x%08lx\n", 553 pr_alert("Unhandled fault: %s (0x%03x) at 0x%08lx\n",
554 inf->name, fsr, addr); 554 inf->name, fsr, addr);
555 show_pte(current->mm, addr);
555 556
556 info.si_signo = inf->sig; 557 info.si_signo = inf->sig;
557 info.si_errno = 0; 558 info.si_errno = 0;
diff --git a/arch/arm/mm/pageattr.c b/arch/arm/mm/pageattr.c
index 004e35cdcfff..cf30daff8932 100644
--- a/arch/arm/mm/pageattr.c
+++ b/arch/arm/mm/pageattr.c
@@ -49,7 +49,10 @@ static int change_memory_common(unsigned long addr, int numpages,
49 WARN_ON_ONCE(1); 49 WARN_ON_ONCE(1);
50 } 50 }
51 51
52 if (!is_module_address(start) || !is_module_address(end - 1)) 52 if (start < MODULES_VADDR || start >= MODULES_END)
53 return -EINVAL;
54
55 if (end < MODULES_VADDR || start >= MODULES_END)
53 return -EINVAL; 56 return -EINVAL;
54 57
55 data.set_mask = set_mask; 58 data.set_mask = set_mask;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index db10169a08de..8ca94d379bc3 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
799 struct device *dev = &pdev->dev; 799 struct device *dev = &pdev->dev;
800 const struct of_device_id *match; 800 const struct of_device_id *match;
801 const struct dmtimer_platform_data *pdata; 801 const struct dmtimer_platform_data *pdata;
802 int ret;
802 803
803 match = of_match_device(of_match_ptr(omap_timer_match), dev); 804 match = of_match_device(of_match_ptr(omap_timer_match), dev);
804 pdata = match ? match->data : dev->platform_data; 805 pdata = match ? match->data : dev->platform_data;
@@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
860 } 861 }
861 862
862 if (!timer->reserved) { 863 if (!timer->reserved) {
863 pm_runtime_get_sync(dev); 864 ret = pm_runtime_get_sync(dev);
865 if (ret < 0) {
866 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
867 __func__);
868 goto err_get_sync;
869 }
864 __omap_dm_timer_init_regs(timer); 870 __omap_dm_timer_init_regs(timer);
865 pm_runtime_put(dev); 871 pm_runtime_put(dev);
866 } 872 }
@@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
873 dev_dbg(dev, "Device Probed.\n"); 879 dev_dbg(dev, "Device Probed.\n");
874 880
875 return 0; 881 return 0;
882
883err_get_sync:
884 pm_runtime_put_noidle(dev);
885 pm_runtime_disable(dev);
886 return ret;
876} 887}
877 888
878/** 889/**
@@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
899 } 910 }
900 spin_unlock_irqrestore(&dm_timer_lock, flags); 911 spin_unlock_irqrestore(&dm_timer_lock, flags);
901 912
913 pm_runtime_disable(&pdev->dev);
914
902 return ret; 915 return ret;
903} 916}
904 917
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 19:36:52 -0500